gpio-ath79.c 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Atheros AR71XX/AR724X/AR913X GPIO API support
  4. *
  5. * Copyright (C) 2015 Alban Bedel <[email protected]>
  6. * Copyright (C) 2010-2011 Jaiganesh Narayanan <[email protected]>
  7. * Copyright (C) 2008-2011 Gabor Juhos <[email protected]>
  8. * Copyright (C) 2008 Imre Kaloz <[email protected]>
  9. */
  10. #include <linux/gpio/driver.h>
  11. #include <linux/platform_data/gpio-ath79.h>
  12. #include <linux/of_device.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/module.h>
  15. #include <linux/irq.h>
  16. #define AR71XX_GPIO_REG_OE 0x00
  17. #define AR71XX_GPIO_REG_IN 0x04
  18. #define AR71XX_GPIO_REG_SET 0x0c
  19. #define AR71XX_GPIO_REG_CLEAR 0x10
  20. #define AR71XX_GPIO_REG_INT_ENABLE 0x14
  21. #define AR71XX_GPIO_REG_INT_TYPE 0x18
  22. #define AR71XX_GPIO_REG_INT_POLARITY 0x1c
  23. #define AR71XX_GPIO_REG_INT_PENDING 0x20
  24. #define AR71XX_GPIO_REG_INT_MASK 0x24
  25. struct ath79_gpio_ctrl {
  26. struct gpio_chip gc;
  27. void __iomem *base;
  28. raw_spinlock_t lock;
  29. unsigned long both_edges;
  30. };
  31. static struct ath79_gpio_ctrl *irq_data_to_ath79_gpio(struct irq_data *data)
  32. {
  33. struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
  34. return container_of(gc, struct ath79_gpio_ctrl, gc);
  35. }
  36. static u32 ath79_gpio_read(struct ath79_gpio_ctrl *ctrl, unsigned reg)
  37. {
  38. return readl(ctrl->base + reg);
  39. }
  40. static void ath79_gpio_write(struct ath79_gpio_ctrl *ctrl,
  41. unsigned reg, u32 val)
  42. {
  43. writel(val, ctrl->base + reg);
  44. }
  45. static bool ath79_gpio_update_bits(
  46. struct ath79_gpio_ctrl *ctrl, unsigned reg, u32 mask, u32 bits)
  47. {
  48. u32 old_val, new_val;
  49. old_val = ath79_gpio_read(ctrl, reg);
  50. new_val = (old_val & ~mask) | (bits & mask);
  51. if (new_val != old_val)
  52. ath79_gpio_write(ctrl, reg, new_val);
  53. return new_val != old_val;
  54. }
  55. static void ath79_gpio_irq_unmask(struct irq_data *data)
  56. {
  57. struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
  58. u32 mask = BIT(irqd_to_hwirq(data));
  59. unsigned long flags;
  60. raw_spin_lock_irqsave(&ctrl->lock, flags);
  61. ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);
  62. raw_spin_unlock_irqrestore(&ctrl->lock, flags);
  63. }
  64. static void ath79_gpio_irq_mask(struct irq_data *data)
  65. {
  66. struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
  67. u32 mask = BIT(irqd_to_hwirq(data));
  68. unsigned long flags;
  69. raw_spin_lock_irqsave(&ctrl->lock, flags);
  70. ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
  71. raw_spin_unlock_irqrestore(&ctrl->lock, flags);
  72. }
  73. static void ath79_gpio_irq_enable(struct irq_data *data)
  74. {
  75. struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
  76. u32 mask = BIT(irqd_to_hwirq(data));
  77. unsigned long flags;
  78. raw_spin_lock_irqsave(&ctrl->lock, flags);
  79. ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);
  80. ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);
  81. raw_spin_unlock_irqrestore(&ctrl->lock, flags);
  82. }
  83. static void ath79_gpio_irq_disable(struct irq_data *data)
  84. {
  85. struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
  86. u32 mask = BIT(irqd_to_hwirq(data));
  87. unsigned long flags;
  88. raw_spin_lock_irqsave(&ctrl->lock, flags);
  89. ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
  90. ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);
  91. raw_spin_unlock_irqrestore(&ctrl->lock, flags);
  92. }
  93. static int ath79_gpio_irq_set_type(struct irq_data *data,
  94. unsigned int flow_type)
  95. {
  96. struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
  97. u32 mask = BIT(irqd_to_hwirq(data));
  98. u32 type = 0, polarity = 0;
  99. unsigned long flags;
  100. bool disabled;
  101. switch (flow_type) {
  102. case IRQ_TYPE_EDGE_RISING:
  103. polarity |= mask;
  104. fallthrough;
  105. case IRQ_TYPE_EDGE_FALLING:
  106. case IRQ_TYPE_EDGE_BOTH:
  107. break;
  108. case IRQ_TYPE_LEVEL_HIGH:
  109. polarity |= mask;
  110. fallthrough;
  111. case IRQ_TYPE_LEVEL_LOW:
  112. type |= mask;
  113. break;
  114. default:
  115. return -EINVAL;
  116. }
  117. raw_spin_lock_irqsave(&ctrl->lock, flags);
  118. if (flow_type == IRQ_TYPE_EDGE_BOTH) {
  119. ctrl->both_edges |= mask;
  120. polarity = ~ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);
  121. } else {
  122. ctrl->both_edges &= ~mask;
  123. }
  124. /* As the IRQ configuration can't be loaded atomically we
  125. * have to disable the interrupt while the configuration state
  126. * is invalid.
  127. */
  128. disabled = ath79_gpio_update_bits(
  129. ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);
  130. ath79_gpio_update_bits(
  131. ctrl, AR71XX_GPIO_REG_INT_TYPE, mask, type);
  132. ath79_gpio_update_bits(
  133. ctrl, AR71XX_GPIO_REG_INT_POLARITY, mask, polarity);
  134. if (disabled)
  135. ath79_gpio_update_bits(
  136. ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);
  137. raw_spin_unlock_irqrestore(&ctrl->lock, flags);
  138. return 0;
  139. }
  140. static struct irq_chip ath79_gpio_irqchip = {
  141. .name = "gpio-ath79",
  142. .irq_enable = ath79_gpio_irq_enable,
  143. .irq_disable = ath79_gpio_irq_disable,
  144. .irq_mask = ath79_gpio_irq_mask,
  145. .irq_unmask = ath79_gpio_irq_unmask,
  146. .irq_set_type = ath79_gpio_irq_set_type,
  147. };
  148. static void ath79_gpio_irq_handler(struct irq_desc *desc)
  149. {
  150. struct gpio_chip *gc = irq_desc_get_handler_data(desc);
  151. struct irq_chip *irqchip = irq_desc_get_chip(desc);
  152. struct ath79_gpio_ctrl *ctrl =
  153. container_of(gc, struct ath79_gpio_ctrl, gc);
  154. unsigned long flags, pending;
  155. u32 both_edges, state;
  156. int irq;
  157. chained_irq_enter(irqchip, desc);
  158. raw_spin_lock_irqsave(&ctrl->lock, flags);
  159. pending = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_INT_PENDING);
  160. /* Update the polarity of the both edges irqs */
  161. both_edges = ctrl->both_edges & pending;
  162. if (both_edges) {
  163. state = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);
  164. ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_POLARITY,
  165. both_edges, ~state);
  166. }
  167. raw_spin_unlock_irqrestore(&ctrl->lock, flags);
  168. for_each_set_bit(irq, &pending, gc->ngpio)
  169. generic_handle_domain_irq(gc->irq.domain, irq);
  170. chained_irq_exit(irqchip, desc);
  171. }
  172. static const struct of_device_id ath79_gpio_of_match[] = {
  173. { .compatible = "qca,ar7100-gpio" },
  174. { .compatible = "qca,ar9340-gpio" },
  175. {},
  176. };
  177. MODULE_DEVICE_TABLE(of, ath79_gpio_of_match);
  178. static int ath79_gpio_probe(struct platform_device *pdev)
  179. {
  180. struct ath79_gpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
  181. struct device *dev = &pdev->dev;
  182. struct device_node *np = dev->of_node;
  183. struct ath79_gpio_ctrl *ctrl;
  184. struct gpio_irq_chip *girq;
  185. u32 ath79_gpio_count;
  186. bool oe_inverted;
  187. int err;
  188. ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
  189. if (!ctrl)
  190. return -ENOMEM;
  191. if (np) {
  192. err = of_property_read_u32(np, "ngpios", &ath79_gpio_count);
  193. if (err) {
  194. dev_err(dev, "ngpios property is not valid\n");
  195. return err;
  196. }
  197. oe_inverted = of_device_is_compatible(np, "qca,ar9340-gpio");
  198. } else if (pdata) {
  199. ath79_gpio_count = pdata->ngpios;
  200. oe_inverted = pdata->oe_inverted;
  201. } else {
  202. dev_err(dev, "No DT node or platform data found\n");
  203. return -EINVAL;
  204. }
  205. if (ath79_gpio_count >= 32) {
  206. dev_err(dev, "ngpios must be less than 32\n");
  207. return -EINVAL;
  208. }
  209. ctrl->base = devm_platform_ioremap_resource(pdev, 0);
  210. if (IS_ERR(ctrl->base))
  211. return PTR_ERR(ctrl->base);
  212. raw_spin_lock_init(&ctrl->lock);
  213. err = bgpio_init(&ctrl->gc, dev, 4,
  214. ctrl->base + AR71XX_GPIO_REG_IN,
  215. ctrl->base + AR71XX_GPIO_REG_SET,
  216. ctrl->base + AR71XX_GPIO_REG_CLEAR,
  217. oe_inverted ? NULL : ctrl->base + AR71XX_GPIO_REG_OE,
  218. oe_inverted ? ctrl->base + AR71XX_GPIO_REG_OE : NULL,
  219. 0);
  220. if (err) {
  221. dev_err(dev, "bgpio_init failed\n");
  222. return err;
  223. }
  224. /* Use base 0 to stay compatible with legacy platforms */
  225. ctrl->gc.base = 0;
  226. /* Optional interrupt setup */
  227. if (!np || of_property_read_bool(np, "interrupt-controller")) {
  228. girq = &ctrl->gc.irq;
  229. girq->chip = &ath79_gpio_irqchip;
  230. girq->parent_handler = ath79_gpio_irq_handler;
  231. girq->num_parents = 1;
  232. girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
  233. GFP_KERNEL);
  234. if (!girq->parents)
  235. return -ENOMEM;
  236. girq->parents[0] = platform_get_irq(pdev, 0);
  237. girq->default_type = IRQ_TYPE_NONE;
  238. girq->handler = handle_simple_irq;
  239. }
  240. return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl);
  241. }
  242. static struct platform_driver ath79_gpio_driver = {
  243. .driver = {
  244. .name = "ath79-gpio",
  245. .of_match_table = ath79_gpio_of_match,
  246. },
  247. .probe = ath79_gpio_probe,
  248. };
  249. module_platform_driver(ath79_gpio_driver);
  250. MODULE_DESCRIPTION("Atheros AR71XX/AR724X/AR913X GPIO API support");
  251. MODULE_LICENSE("GPL v2");