gpio-adnp.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2011-2012 Avionic Design GmbH
  4. */
  5. #include <linux/gpio/driver.h>
  6. #include <linux/i2c.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/mod_devicetable.h>
  9. #include <linux/module.h>
  10. #include <linux/property.h>
  11. #include <linux/seq_file.h>
  12. #include <linux/slab.h>
  13. #define GPIO_DDR(gpio) (0x00 << (gpio)->reg_shift)
  14. #define GPIO_PLR(gpio) (0x01 << (gpio)->reg_shift)
  15. #define GPIO_IER(gpio) (0x02 << (gpio)->reg_shift)
  16. #define GPIO_ISR(gpio) (0x03 << (gpio)->reg_shift)
  17. #define GPIO_PTR(gpio) (0x04 << (gpio)->reg_shift)
  18. struct adnp {
  19. struct i2c_client *client;
  20. struct gpio_chip gpio;
  21. unsigned int reg_shift;
  22. struct mutex i2c_lock;
  23. struct mutex irq_lock;
  24. u8 *irq_enable;
  25. u8 *irq_level;
  26. u8 *irq_rise;
  27. u8 *irq_fall;
  28. u8 *irq_high;
  29. u8 *irq_low;
  30. };
  31. static int adnp_read(struct adnp *adnp, unsigned offset, uint8_t *value)
  32. {
  33. int err;
  34. err = i2c_smbus_read_byte_data(adnp->client, offset);
  35. if (err < 0) {
  36. dev_err(adnp->gpio.parent, "%s failed: %d\n",
  37. "i2c_smbus_read_byte_data()", err);
  38. return err;
  39. }
  40. *value = err;
  41. return 0;
  42. }
  43. static int adnp_write(struct adnp *adnp, unsigned offset, uint8_t value)
  44. {
  45. int err;
  46. err = i2c_smbus_write_byte_data(adnp->client, offset, value);
  47. if (err < 0) {
  48. dev_err(adnp->gpio.parent, "%s failed: %d\n",
  49. "i2c_smbus_write_byte_data()", err);
  50. return err;
  51. }
  52. return 0;
  53. }
  54. static int adnp_gpio_get(struct gpio_chip *chip, unsigned offset)
  55. {
  56. struct adnp *adnp = gpiochip_get_data(chip);
  57. unsigned int reg = offset >> adnp->reg_shift;
  58. unsigned int pos = offset & 7;
  59. u8 value;
  60. int err;
  61. err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &value);
  62. if (err < 0)
  63. return err;
  64. return (value & BIT(pos)) ? 1 : 0;
  65. }
  66. static void __adnp_gpio_set(struct adnp *adnp, unsigned offset, int value)
  67. {
  68. unsigned int reg = offset >> adnp->reg_shift;
  69. unsigned int pos = offset & 7;
  70. int err;
  71. u8 val;
  72. err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &val);
  73. if (err < 0)
  74. return;
  75. if (value)
  76. val |= BIT(pos);
  77. else
  78. val &= ~BIT(pos);
  79. adnp_write(adnp, GPIO_PLR(adnp) + reg, val);
  80. }
  81. static void adnp_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  82. {
  83. struct adnp *adnp = gpiochip_get_data(chip);
  84. mutex_lock(&adnp->i2c_lock);
  85. __adnp_gpio_set(adnp, offset, value);
  86. mutex_unlock(&adnp->i2c_lock);
  87. }
  88. static int adnp_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  89. {
  90. struct adnp *adnp = gpiochip_get_data(chip);
  91. unsigned int reg = offset >> adnp->reg_shift;
  92. unsigned int pos = offset & 7;
  93. u8 value;
  94. int err;
  95. mutex_lock(&adnp->i2c_lock);
  96. err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value);
  97. if (err < 0)
  98. goto out;
  99. value &= ~BIT(pos);
  100. err = adnp_write(adnp, GPIO_DDR(adnp) + reg, value);
  101. if (err < 0)
  102. goto out;
  103. err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value);
  104. if (err < 0)
  105. goto out;
  106. if (value & BIT(pos)) {
  107. err = -EPERM;
  108. goto out;
  109. }
  110. err = 0;
  111. out:
  112. mutex_unlock(&adnp->i2c_lock);
  113. return err;
  114. }
  115. static int adnp_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
  116. int value)
  117. {
  118. struct adnp *adnp = gpiochip_get_data(chip);
  119. unsigned int reg = offset >> adnp->reg_shift;
  120. unsigned int pos = offset & 7;
  121. int err;
  122. u8 val;
  123. mutex_lock(&adnp->i2c_lock);
  124. err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val);
  125. if (err < 0)
  126. goto out;
  127. val |= BIT(pos);
  128. err = adnp_write(adnp, GPIO_DDR(adnp) + reg, val);
  129. if (err < 0)
  130. goto out;
  131. err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val);
  132. if (err < 0)
  133. goto out;
  134. if (!(val & BIT(pos))) {
  135. err = -EPERM;
  136. goto out;
  137. }
  138. __adnp_gpio_set(adnp, offset, value);
  139. err = 0;
  140. out:
  141. mutex_unlock(&adnp->i2c_lock);
  142. return err;
  143. }
  144. static void adnp_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
  145. {
  146. struct adnp *adnp = gpiochip_get_data(chip);
  147. unsigned int num_regs = 1 << adnp->reg_shift, i, j;
  148. int err;
  149. for (i = 0; i < num_regs; i++) {
  150. u8 ddr, plr, ier, isr;
  151. mutex_lock(&adnp->i2c_lock);
  152. err = adnp_read(adnp, GPIO_DDR(adnp) + i, &ddr);
  153. if (err < 0)
  154. goto unlock;
  155. err = adnp_read(adnp, GPIO_PLR(adnp) + i, &plr);
  156. if (err < 0)
  157. goto unlock;
  158. err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier);
  159. if (err < 0)
  160. goto unlock;
  161. err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr);
  162. if (err < 0)
  163. goto unlock;
  164. mutex_unlock(&adnp->i2c_lock);
  165. for (j = 0; j < 8; j++) {
  166. unsigned int bit = (i << adnp->reg_shift) + j;
  167. const char *direction = "input ";
  168. const char *level = "low ";
  169. const char *interrupt = "disabled";
  170. const char *pending = "";
  171. if (ddr & BIT(j))
  172. direction = "output";
  173. if (plr & BIT(j))
  174. level = "high";
  175. if (ier & BIT(j))
  176. interrupt = "enabled ";
  177. if (isr & BIT(j))
  178. pending = "pending";
  179. seq_printf(s, "%2u: %s %s IRQ %s %s\n", bit,
  180. direction, level, interrupt, pending);
  181. }
  182. }
  183. return;
  184. unlock:
  185. mutex_unlock(&adnp->i2c_lock);
  186. }
  187. static irqreturn_t adnp_irq(int irq, void *data)
  188. {
  189. struct adnp *adnp = data;
  190. unsigned int num_regs, i;
  191. num_regs = 1 << adnp->reg_shift;
  192. for (i = 0; i < num_regs; i++) {
  193. unsigned int base = i << adnp->reg_shift, bit;
  194. u8 changed, level, isr, ier;
  195. unsigned long pending;
  196. int err;
  197. mutex_lock(&adnp->i2c_lock);
  198. err = adnp_read(adnp, GPIO_PLR(adnp) + i, &level);
  199. if (err < 0) {
  200. mutex_unlock(&adnp->i2c_lock);
  201. continue;
  202. }
  203. err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr);
  204. if (err < 0) {
  205. mutex_unlock(&adnp->i2c_lock);
  206. continue;
  207. }
  208. err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier);
  209. if (err < 0) {
  210. mutex_unlock(&adnp->i2c_lock);
  211. continue;
  212. }
  213. mutex_unlock(&adnp->i2c_lock);
  214. /* determine pins that changed levels */
  215. changed = level ^ adnp->irq_level[i];
  216. /* compute edge-triggered interrupts */
  217. pending = changed & ((adnp->irq_fall[i] & ~level) |
  218. (adnp->irq_rise[i] & level));
  219. /* add in level-triggered interrupts */
  220. pending |= (adnp->irq_high[i] & level) |
  221. (adnp->irq_low[i] & ~level);
  222. /* mask out non-pending and disabled interrupts */
  223. pending &= isr & ier;
  224. for_each_set_bit(bit, &pending, 8) {
  225. unsigned int child_irq;
  226. child_irq = irq_find_mapping(adnp->gpio.irq.domain,
  227. base + bit);
  228. handle_nested_irq(child_irq);
  229. }
  230. }
  231. return IRQ_HANDLED;
  232. }
  233. static void adnp_irq_mask(struct irq_data *d)
  234. {
  235. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  236. struct adnp *adnp = gpiochip_get_data(gc);
  237. unsigned int reg = d->hwirq >> adnp->reg_shift;
  238. unsigned int pos = d->hwirq & 7;
  239. adnp->irq_enable[reg] &= ~BIT(pos);
  240. }
  241. static void adnp_irq_unmask(struct irq_data *d)
  242. {
  243. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  244. struct adnp *adnp = gpiochip_get_data(gc);
  245. unsigned int reg = d->hwirq >> adnp->reg_shift;
  246. unsigned int pos = d->hwirq & 7;
  247. adnp->irq_enable[reg] |= BIT(pos);
  248. }
  249. static int adnp_irq_set_type(struct irq_data *d, unsigned int type)
  250. {
  251. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  252. struct adnp *adnp = gpiochip_get_data(gc);
  253. unsigned int reg = d->hwirq >> adnp->reg_shift;
  254. unsigned int pos = d->hwirq & 7;
  255. if (type & IRQ_TYPE_EDGE_RISING)
  256. adnp->irq_rise[reg] |= BIT(pos);
  257. else
  258. adnp->irq_rise[reg] &= ~BIT(pos);
  259. if (type & IRQ_TYPE_EDGE_FALLING)
  260. adnp->irq_fall[reg] |= BIT(pos);
  261. else
  262. adnp->irq_fall[reg] &= ~BIT(pos);
  263. if (type & IRQ_TYPE_LEVEL_HIGH)
  264. adnp->irq_high[reg] |= BIT(pos);
  265. else
  266. adnp->irq_high[reg] &= ~BIT(pos);
  267. if (type & IRQ_TYPE_LEVEL_LOW)
  268. adnp->irq_low[reg] |= BIT(pos);
  269. else
  270. adnp->irq_low[reg] &= ~BIT(pos);
  271. return 0;
  272. }
  273. static void adnp_irq_bus_lock(struct irq_data *d)
  274. {
  275. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  276. struct adnp *adnp = gpiochip_get_data(gc);
  277. mutex_lock(&adnp->irq_lock);
  278. }
  279. static void adnp_irq_bus_unlock(struct irq_data *d)
  280. {
  281. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  282. struct adnp *adnp = gpiochip_get_data(gc);
  283. unsigned int num_regs = 1 << adnp->reg_shift, i;
  284. mutex_lock(&adnp->i2c_lock);
  285. for (i = 0; i < num_regs; i++)
  286. adnp_write(adnp, GPIO_IER(adnp) + i, adnp->irq_enable[i]);
  287. mutex_unlock(&adnp->i2c_lock);
  288. mutex_unlock(&adnp->irq_lock);
  289. }
  290. static struct irq_chip adnp_irq_chip = {
  291. .name = "gpio-adnp",
  292. .irq_mask = adnp_irq_mask,
  293. .irq_unmask = adnp_irq_unmask,
  294. .irq_set_type = adnp_irq_set_type,
  295. .irq_bus_lock = adnp_irq_bus_lock,
  296. .irq_bus_sync_unlock = adnp_irq_bus_unlock,
  297. };
  298. static int adnp_irq_setup(struct adnp *adnp)
  299. {
  300. unsigned int num_regs = 1 << adnp->reg_shift, i;
  301. struct gpio_chip *chip = &adnp->gpio;
  302. int err;
  303. mutex_init(&adnp->irq_lock);
  304. /*
  305. * Allocate memory to keep track of the current level and trigger
  306. * modes of the interrupts. To avoid multiple allocations, a single
  307. * large buffer is allocated and pointers are setup to point at the
  308. * corresponding offsets. For consistency, the layout of the buffer
  309. * is chosen to match the register layout of the hardware in that
  310. * each segment contains the corresponding bits for all interrupts.
  311. */
  312. adnp->irq_enable = devm_kcalloc(chip->parent, num_regs, 6,
  313. GFP_KERNEL);
  314. if (!adnp->irq_enable)
  315. return -ENOMEM;
  316. adnp->irq_level = adnp->irq_enable + (num_regs * 1);
  317. adnp->irq_rise = adnp->irq_enable + (num_regs * 2);
  318. adnp->irq_fall = adnp->irq_enable + (num_regs * 3);
  319. adnp->irq_high = adnp->irq_enable + (num_regs * 4);
  320. adnp->irq_low = adnp->irq_enable + (num_regs * 5);
  321. for (i = 0; i < num_regs; i++) {
  322. /*
  323. * Read the initial level of all pins to allow the emulation
  324. * of edge triggered interrupts.
  325. */
  326. err = adnp_read(adnp, GPIO_PLR(adnp) + i, &adnp->irq_level[i]);
  327. if (err < 0)
  328. return err;
  329. /* disable all interrupts */
  330. err = adnp_write(adnp, GPIO_IER(adnp) + i, 0);
  331. if (err < 0)
  332. return err;
  333. adnp->irq_enable[i] = 0x00;
  334. }
  335. err = devm_request_threaded_irq(chip->parent, adnp->client->irq,
  336. NULL, adnp_irq,
  337. IRQF_TRIGGER_RISING | IRQF_ONESHOT,
  338. dev_name(chip->parent), adnp);
  339. if (err != 0) {
  340. dev_err(chip->parent, "can't request IRQ#%d: %d\n",
  341. adnp->client->irq, err);
  342. return err;
  343. }
  344. return 0;
  345. }
  346. static int adnp_gpio_setup(struct adnp *adnp, unsigned int num_gpios,
  347. bool is_irq_controller)
  348. {
  349. struct gpio_chip *chip = &adnp->gpio;
  350. int err;
  351. adnp->reg_shift = get_count_order(num_gpios) - 3;
  352. chip->direction_input = adnp_gpio_direction_input;
  353. chip->direction_output = adnp_gpio_direction_output;
  354. chip->get = adnp_gpio_get;
  355. chip->set = adnp_gpio_set;
  356. chip->can_sleep = true;
  357. if (IS_ENABLED(CONFIG_DEBUG_FS))
  358. chip->dbg_show = adnp_gpio_dbg_show;
  359. chip->base = -1;
  360. chip->ngpio = num_gpios;
  361. chip->label = adnp->client->name;
  362. chip->parent = &adnp->client->dev;
  363. chip->owner = THIS_MODULE;
  364. if (is_irq_controller) {
  365. struct gpio_irq_chip *girq;
  366. err = adnp_irq_setup(adnp);
  367. if (err)
  368. return err;
  369. girq = &chip->irq;
  370. girq->chip = &adnp_irq_chip;
  371. /* This will let us handle the parent IRQ in the driver */
  372. girq->parent_handler = NULL;
  373. girq->num_parents = 0;
  374. girq->parents = NULL;
  375. girq->default_type = IRQ_TYPE_NONE;
  376. girq->handler = handle_simple_irq;
  377. girq->threaded = true;
  378. }
  379. err = devm_gpiochip_add_data(&adnp->client->dev, chip, adnp);
  380. if (err)
  381. return err;
  382. return 0;
  383. }
  384. static int adnp_i2c_probe(struct i2c_client *client)
  385. {
  386. struct device *dev = &client->dev;
  387. struct adnp *adnp;
  388. u32 num_gpios;
  389. int err;
  390. err = device_property_read_u32(dev, "nr-gpios", &num_gpios);
  391. if (err < 0)
  392. return err;
  393. adnp = devm_kzalloc(&client->dev, sizeof(*adnp), GFP_KERNEL);
  394. if (!adnp)
  395. return -ENOMEM;
  396. mutex_init(&adnp->i2c_lock);
  397. adnp->client = client;
  398. err = adnp_gpio_setup(adnp, num_gpios, device_property_read_bool(dev, "interrupt-controller"));
  399. if (err)
  400. return err;
  401. i2c_set_clientdata(client, adnp);
  402. return 0;
  403. }
  404. static const struct i2c_device_id adnp_i2c_id[] = {
  405. { "gpio-adnp" },
  406. { },
  407. };
  408. MODULE_DEVICE_TABLE(i2c, adnp_i2c_id);
  409. static const struct of_device_id adnp_of_match[] = {
  410. { .compatible = "ad,gpio-adnp", },
  411. { },
  412. };
  413. MODULE_DEVICE_TABLE(of, adnp_of_match);
  414. static struct i2c_driver adnp_i2c_driver = {
  415. .driver = {
  416. .name = "gpio-adnp",
  417. .of_match_table = adnp_of_match,
  418. },
  419. .probe_new = adnp_i2c_probe,
  420. .id_table = adnp_i2c_id,
  421. };
  422. module_i2c_driver(adnp_i2c_driver);
  423. MODULE_DESCRIPTION("Avionic Design N-bit GPIO expander");
  424. MODULE_AUTHOR("Thierry Reding <[email protected]>");
  425. MODULE_LICENSE("GPL");