versal-fpga.c 2.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2019-2021 Xilinx, Inc.
  4. */
  5. #include <linux/dma-mapping.h>
  6. #include <linux/fpga/fpga-mgr.h>
  7. #include <linux/io.h>
  8. #include <linux/kernel.h>
  9. #include <linux/module.h>
  10. #include <linux/of_address.h>
  11. #include <linux/string.h>
  12. #include <linux/firmware/xlnx-zynqmp.h>
  13. static int versal_fpga_ops_write_init(struct fpga_manager *mgr,
  14. struct fpga_image_info *info,
  15. const char *buf, size_t size)
  16. {
  17. return 0;
  18. }
  19. static int versal_fpga_ops_write(struct fpga_manager *mgr,
  20. const char *buf, size_t size)
  21. {
  22. dma_addr_t dma_addr = 0;
  23. char *kbuf;
  24. int ret;
  25. kbuf = dma_alloc_coherent(mgr->dev.parent, size, &dma_addr, GFP_KERNEL);
  26. if (!kbuf)
  27. return -ENOMEM;
  28. memcpy(kbuf, buf, size);
  29. ret = zynqmp_pm_load_pdi(PDI_SRC_DDR, dma_addr);
  30. dma_free_coherent(mgr->dev.parent, size, kbuf, dma_addr);
  31. return ret;
  32. }
  33. static const struct fpga_manager_ops versal_fpga_ops = {
  34. .write_init = versal_fpga_ops_write_init,
  35. .write = versal_fpga_ops_write,
  36. };
  37. static int versal_fpga_probe(struct platform_device *pdev)
  38. {
  39. struct device *dev = &pdev->dev;
  40. struct fpga_manager *mgr;
  41. int ret;
  42. ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
  43. if (ret < 0) {
  44. dev_err(dev, "no usable DMA configuration\n");
  45. return ret;
  46. }
  47. mgr = devm_fpga_mgr_register(dev, "Xilinx Versal FPGA Manager",
  48. &versal_fpga_ops, NULL);
  49. return PTR_ERR_OR_ZERO(mgr);
  50. }
  51. static const struct of_device_id versal_fpga_of_match[] = {
  52. { .compatible = "xlnx,versal-fpga", },
  53. {},
  54. };
  55. MODULE_DEVICE_TABLE(of, versal_fpga_of_match);
  56. static struct platform_driver versal_fpga_driver = {
  57. .probe = versal_fpga_probe,
  58. .driver = {
  59. .name = "versal_fpga_manager",
  60. .of_match_table = of_match_ptr(versal_fpga_of_match),
  61. },
  62. };
  63. module_platform_driver(versal_fpga_driver);
  64. MODULE_AUTHOR("Nava kishore Manne <[email protected]>");
  65. MODULE_AUTHOR("Appana Durga Kedareswara rao <[email protected]>");
  66. MODULE_DESCRIPTION("Xilinx Versal FPGA Manager");
  67. MODULE_LICENSE("GPL");