microchip-spi.c 9.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Microchip Polarfire FPGA programming over slave SPI interface.
  4. */
  5. #include <asm/unaligned.h>
  6. #include <linux/delay.h>
  7. #include <linux/fpga/fpga-mgr.h>
  8. #include <linux/iopoll.h>
  9. #include <linux/module.h>
  10. #include <linux/of_device.h>
  11. #include <linux/spi/spi.h>
  12. #define MPF_SPI_ISC_ENABLE 0x0B
  13. #define MPF_SPI_ISC_DISABLE 0x0C
  14. #define MPF_SPI_READ_STATUS 0x00
  15. #define MPF_SPI_READ_DATA 0x01
  16. #define MPF_SPI_FRAME_INIT 0xAE
  17. #define MPF_SPI_FRAME 0xEE
  18. #define MPF_SPI_PRG_MODE 0x01
  19. #define MPF_SPI_RELEASE 0x23
  20. #define MPF_SPI_FRAME_SIZE 16
  21. #define MPF_HEADER_SIZE_OFFSET 24
  22. #define MPF_DATA_SIZE_OFFSET 55
  23. #define MPF_LOOKUP_TABLE_RECORD_SIZE 9
  24. #define MPF_LOOKUP_TABLE_BLOCK_ID_OFFSET 0
  25. #define MPF_LOOKUP_TABLE_BLOCK_START_OFFSET 1
  26. #define MPF_COMPONENTS_SIZE_ID 5
  27. #define MPF_BITSTREAM_ID 8
  28. #define MPF_BITS_PER_COMPONENT_SIZE 22
  29. #define MPF_STATUS_POLL_TIMEOUT (2 * USEC_PER_SEC)
  30. #define MPF_STATUS_BUSY BIT(0)
  31. #define MPF_STATUS_READY BIT(1)
  32. #define MPF_STATUS_SPI_VIOLATION BIT(2)
  33. #define MPF_STATUS_SPI_ERROR BIT(3)
  34. struct mpf_priv {
  35. struct spi_device *spi;
  36. bool program_mode;
  37. u8 tx __aligned(ARCH_KMALLOC_MINALIGN);
  38. u8 rx;
  39. };
  40. static int mpf_read_status(struct mpf_priv *priv)
  41. {
  42. /*
  43. * HW status is returned on MISO in the first byte after CS went
  44. * active. However, first reading can be inadequate, so we submit
  45. * two identical SPI transfers and use result of the later one.
  46. */
  47. struct spi_transfer xfers[2] = {
  48. {
  49. .tx_buf = &priv->tx,
  50. .rx_buf = &priv->rx,
  51. .len = 1,
  52. .cs_change = 1,
  53. }, {
  54. .tx_buf = &priv->tx,
  55. .rx_buf = &priv->rx,
  56. .len = 1,
  57. },
  58. };
  59. u8 status;
  60. int ret;
  61. priv->tx = MPF_SPI_READ_STATUS;
  62. ret = spi_sync_transfer(priv->spi, xfers, 2);
  63. if (ret)
  64. return ret;
  65. status = priv->rx;
  66. if ((status & MPF_STATUS_SPI_VIOLATION) ||
  67. (status & MPF_STATUS_SPI_ERROR))
  68. return -EIO;
  69. return status;
  70. }
  71. static enum fpga_mgr_states mpf_ops_state(struct fpga_manager *mgr)
  72. {
  73. struct mpf_priv *priv = mgr->priv;
  74. bool program_mode;
  75. int status;
  76. program_mode = priv->program_mode;
  77. status = mpf_read_status(priv);
  78. if (!program_mode && !status)
  79. return FPGA_MGR_STATE_OPERATING;
  80. return FPGA_MGR_STATE_UNKNOWN;
  81. }
  82. static int mpf_ops_parse_header(struct fpga_manager *mgr,
  83. struct fpga_image_info *info,
  84. const char *buf, size_t count)
  85. {
  86. size_t component_size_byte_num, component_size_byte_off,
  87. components_size_start, bitstream_start,
  88. block_id_offset, block_start_offset;
  89. u8 header_size, blocks_num, block_id;
  90. u32 block_start, component_size;
  91. u16 components_num, i;
  92. if (!buf) {
  93. dev_err(&mgr->dev, "Image buffer is not provided\n");
  94. return -EINVAL;
  95. }
  96. header_size = *(buf + MPF_HEADER_SIZE_OFFSET);
  97. if (header_size > count) {
  98. info->header_size = header_size;
  99. return -EAGAIN;
  100. }
  101. /*
  102. * Go through look-up table to find out where actual bitstream starts
  103. * and where sizes of components of the bitstream lies.
  104. */
  105. blocks_num = *(buf + header_size - 1);
  106. block_id_offset = header_size + MPF_LOOKUP_TABLE_BLOCK_ID_OFFSET;
  107. block_start_offset = header_size + MPF_LOOKUP_TABLE_BLOCK_START_OFFSET;
  108. header_size += blocks_num * MPF_LOOKUP_TABLE_RECORD_SIZE;
  109. if (header_size > count) {
  110. info->header_size = header_size;
  111. return -EAGAIN;
  112. }
  113. components_size_start = 0;
  114. bitstream_start = 0;
  115. while (blocks_num--) {
  116. block_id = *(buf + block_id_offset);
  117. block_start = get_unaligned_le32(buf + block_start_offset);
  118. switch (block_id) {
  119. case MPF_BITSTREAM_ID:
  120. bitstream_start = block_start;
  121. info->header_size = block_start;
  122. if (block_start > count)
  123. return -EAGAIN;
  124. break;
  125. case MPF_COMPONENTS_SIZE_ID:
  126. components_size_start = block_start;
  127. break;
  128. default:
  129. break;
  130. }
  131. if (bitstream_start && components_size_start)
  132. break;
  133. block_id_offset += MPF_LOOKUP_TABLE_RECORD_SIZE;
  134. block_start_offset += MPF_LOOKUP_TABLE_RECORD_SIZE;
  135. }
  136. if (!bitstream_start || !components_size_start) {
  137. dev_err(&mgr->dev, "Failed to parse header look-up table\n");
  138. return -EFAULT;
  139. }
  140. /*
  141. * Parse bitstream size.
  142. * Sizes of components of the bitstream are 22-bits long placed next
  143. * to each other. Image header should be extended by now up to where
  144. * actual bitstream starts, so no need for overflow check anymore.
  145. */
  146. components_num = get_unaligned_le16(buf + MPF_DATA_SIZE_OFFSET);
  147. for (i = 0; i < components_num; i++) {
  148. component_size_byte_num =
  149. (i * MPF_BITS_PER_COMPONENT_SIZE) / BITS_PER_BYTE;
  150. component_size_byte_off =
  151. (i * MPF_BITS_PER_COMPONENT_SIZE) % BITS_PER_BYTE;
  152. component_size = get_unaligned_le32(buf +
  153. components_size_start +
  154. component_size_byte_num);
  155. component_size >>= component_size_byte_off;
  156. component_size &= GENMASK(MPF_BITS_PER_COMPONENT_SIZE - 1, 0);
  157. info->data_size += component_size * MPF_SPI_FRAME_SIZE;
  158. }
  159. return 0;
  160. }
  161. static int mpf_poll_status(struct mpf_priv *priv, u8 mask)
  162. {
  163. int ret, status;
  164. /*
  165. * Busy poll HW status. Polling stops if any of the following
  166. * conditions are met:
  167. * - timeout is reached
  168. * - mpf_read_status() returns an error
  169. * - busy bit is cleared AND mask bits are set
  170. */
  171. ret = read_poll_timeout(mpf_read_status, status,
  172. (status < 0) ||
  173. ((status & (MPF_STATUS_BUSY | mask)) == mask),
  174. 0, MPF_STATUS_POLL_TIMEOUT, false, priv);
  175. if (ret < 0)
  176. return ret;
  177. return status;
  178. }
  179. static int mpf_spi_write(struct mpf_priv *priv, const void *buf, size_t buf_size)
  180. {
  181. int status = mpf_poll_status(priv, 0);
  182. if (status < 0)
  183. return status;
  184. return spi_write_then_read(priv->spi, buf, buf_size, NULL, 0);
  185. }
  186. static int mpf_spi_write_then_read(struct mpf_priv *priv,
  187. const void *txbuf, size_t txbuf_size,
  188. void *rxbuf, size_t rxbuf_size)
  189. {
  190. const u8 read_command[] = { MPF_SPI_READ_DATA };
  191. int ret;
  192. ret = mpf_spi_write(priv, txbuf, txbuf_size);
  193. if (ret)
  194. return ret;
  195. ret = mpf_poll_status(priv, MPF_STATUS_READY);
  196. if (ret < 0)
  197. return ret;
  198. return spi_write_then_read(priv->spi, read_command, sizeof(read_command),
  199. rxbuf, rxbuf_size);
  200. }
  201. static int mpf_ops_write_init(struct fpga_manager *mgr,
  202. struct fpga_image_info *info, const char *buf,
  203. size_t count)
  204. {
  205. const u8 program_mode[] = { MPF_SPI_FRAME_INIT, MPF_SPI_PRG_MODE };
  206. const u8 isc_en_command[] = { MPF_SPI_ISC_ENABLE };
  207. struct mpf_priv *priv = mgr->priv;
  208. struct device *dev = &mgr->dev;
  209. u32 isc_ret = 0;
  210. int ret;
  211. if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
  212. dev_err(dev, "Partial reconfiguration is not supported\n");
  213. return -EOPNOTSUPP;
  214. }
  215. ret = mpf_spi_write_then_read(priv, isc_en_command, sizeof(isc_en_command),
  216. &isc_ret, sizeof(isc_ret));
  217. if (ret || isc_ret) {
  218. dev_err(dev, "Failed to enable ISC: spi_ret %d, isc_ret %u\n",
  219. ret, isc_ret);
  220. return -EFAULT;
  221. }
  222. ret = mpf_spi_write(priv, program_mode, sizeof(program_mode));
  223. if (ret) {
  224. dev_err(dev, "Failed to enter program mode: %d\n", ret);
  225. return ret;
  226. }
  227. priv->program_mode = true;
  228. return 0;
  229. }
  230. static int mpf_ops_write(struct fpga_manager *mgr, const char *buf, size_t count)
  231. {
  232. struct spi_transfer xfers[2] = { 0 };
  233. struct mpf_priv *priv = mgr->priv;
  234. struct device *dev = &mgr->dev;
  235. int ret, i;
  236. if (count % MPF_SPI_FRAME_SIZE) {
  237. dev_err(dev, "Bitstream size is not a multiple of %d\n",
  238. MPF_SPI_FRAME_SIZE);
  239. return -EINVAL;
  240. }
  241. xfers[0].tx_buf = &priv->tx;
  242. xfers[0].len = 1;
  243. for (i = 0; i < count / MPF_SPI_FRAME_SIZE; i++) {
  244. xfers[1].tx_buf = buf + i * MPF_SPI_FRAME_SIZE;
  245. xfers[1].len = MPF_SPI_FRAME_SIZE;
  246. ret = mpf_poll_status(priv, 0);
  247. if (ret >= 0) {
  248. priv->tx = MPF_SPI_FRAME;
  249. ret = spi_sync_transfer(priv->spi, xfers, ARRAY_SIZE(xfers));
  250. }
  251. if (ret) {
  252. dev_err(dev, "Failed to write bitstream frame %d/%zu\n",
  253. i, count / MPF_SPI_FRAME_SIZE);
  254. return ret;
  255. }
  256. }
  257. return 0;
  258. }
  259. static int mpf_ops_write_complete(struct fpga_manager *mgr,
  260. struct fpga_image_info *info)
  261. {
  262. const u8 isc_dis_command[] = { MPF_SPI_ISC_DISABLE };
  263. const u8 release_command[] = { MPF_SPI_RELEASE };
  264. struct mpf_priv *priv = mgr->priv;
  265. struct device *dev = &mgr->dev;
  266. int ret;
  267. ret = mpf_spi_write(priv, isc_dis_command, sizeof(isc_dis_command));
  268. if (ret) {
  269. dev_err(dev, "Failed to disable ISC: %d\n", ret);
  270. return ret;
  271. }
  272. usleep_range(1000, 2000);
  273. ret = mpf_spi_write(priv, release_command, sizeof(release_command));
  274. if (ret) {
  275. dev_err(dev, "Failed to exit program mode: %d\n", ret);
  276. return ret;
  277. }
  278. priv->program_mode = false;
  279. return 0;
  280. }
  281. static const struct fpga_manager_ops mpf_ops = {
  282. .state = mpf_ops_state,
  283. .initial_header_size = 71,
  284. .skip_header = true,
  285. .parse_header = mpf_ops_parse_header,
  286. .write_init = mpf_ops_write_init,
  287. .write = mpf_ops_write,
  288. .write_complete = mpf_ops_write_complete,
  289. };
  290. static int mpf_probe(struct spi_device *spi)
  291. {
  292. struct device *dev = &spi->dev;
  293. struct fpga_manager *mgr;
  294. struct mpf_priv *priv;
  295. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  296. if (!priv)
  297. return -ENOMEM;
  298. priv->spi = spi;
  299. mgr = devm_fpga_mgr_register(dev, "Microchip Polarfire SPI FPGA Manager",
  300. &mpf_ops, priv);
  301. return PTR_ERR_OR_ZERO(mgr);
  302. }
  303. static const struct spi_device_id mpf_spi_ids[] = {
  304. { .name = "mpf-spi-fpga-mgr", },
  305. {},
  306. };
  307. MODULE_DEVICE_TABLE(spi, mpf_spi_ids);
  308. #if IS_ENABLED(CONFIG_OF)
  309. static const struct of_device_id mpf_of_ids[] = {
  310. { .compatible = "microchip,mpf-spi-fpga-mgr" },
  311. {},
  312. };
  313. MODULE_DEVICE_TABLE(of, mpf_of_ids);
  314. #endif /* IS_ENABLED(CONFIG_OF) */
  315. static struct spi_driver mpf_driver = {
  316. .probe = mpf_probe,
  317. .id_table = mpf_spi_ids,
  318. .driver = {
  319. .name = "microchip_mpf_spi_fpga_mgr",
  320. .of_match_table = of_match_ptr(mpf_of_ids),
  321. },
  322. };
  323. module_spi_driver(mpf_driver);
  324. MODULE_DESCRIPTION("Microchip Polarfire SPI FPGA Manager");
  325. MODULE_AUTHOR("Ivan Bornyakov <[email protected]>");
  326. MODULE_LICENSE("GPL");