fsl_ddr_edac.h 2.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Freescale Memory Controller kernel module
  4. *
  5. * Support Power-based SoCs including MPC85xx, MPC86xx, MPC83xx and
  6. * ARM-based Layerscape SoCs including LS2xxx and LS1021A. Originally
  7. * split out from mpc85xx_edac EDAC driver.
  8. *
  9. * Author: Dave Jiang <[email protected]>
  10. *
  11. * 2006-2007 (c) MontaVista Software, Inc.
  12. */
  13. #ifndef _FSL_DDR_EDAC_H_
  14. #define _FSL_DDR_EDAC_H_
  15. #define fsl_mc_printk(mci, level, fmt, arg...) \
  16. edac_mc_chipset_printk(mci, level, "FSL_DDR", fmt, ##arg)
  17. /*
  18. * DRAM error defines
  19. */
  20. /* DDR_SDRAM_CFG */
  21. #define FSL_MC_DDR_SDRAM_CFG 0x0110
  22. #define FSL_MC_CS_BNDS_0 0x0000
  23. #define FSL_MC_CS_BNDS_OFS 0x0008
  24. #define FSL_MC_DATA_ERR_INJECT_HI 0x0e00
  25. #define FSL_MC_DATA_ERR_INJECT_LO 0x0e04
  26. #define FSL_MC_ECC_ERR_INJECT 0x0e08
  27. #define FSL_MC_CAPTURE_DATA_HI 0x0e20
  28. #define FSL_MC_CAPTURE_DATA_LO 0x0e24
  29. #define FSL_MC_CAPTURE_ECC 0x0e28
  30. #define FSL_MC_ERR_DETECT 0x0e40
  31. #define FSL_MC_ERR_DISABLE 0x0e44
  32. #define FSL_MC_ERR_INT_EN 0x0e48
  33. #define FSL_MC_CAPTURE_ATRIBUTES 0x0e4c
  34. #define FSL_MC_CAPTURE_ADDRESS 0x0e50
  35. #define FSL_MC_CAPTURE_EXT_ADDRESS 0x0e54
  36. #define FSL_MC_ERR_SBE 0x0e58
  37. #define DSC_MEM_EN 0x80000000
  38. #define DSC_ECC_EN 0x20000000
  39. #define DSC_RD_EN 0x10000000
  40. #define DSC_DBW_MASK 0x00180000
  41. #define DSC_DBW_32 0x00080000
  42. #define DSC_DBW_64 0x00000000
  43. #define DSC_SDTYPE_MASK 0x07000000
  44. #define DSC_X32_EN 0x00000020
  45. /* Err_Int_En */
  46. #define DDR_EIE_MSEE 0x1 /* memory select */
  47. #define DDR_EIE_SBEE 0x4 /* single-bit ECC error */
  48. #define DDR_EIE_MBEE 0x8 /* multi-bit ECC error */
  49. /* Err_Detect */
  50. #define DDR_EDE_MSE 0x1 /* memory select */
  51. #define DDR_EDE_SBE 0x4 /* single-bit ECC error */
  52. #define DDR_EDE_MBE 0x8 /* multi-bit ECC error */
  53. #define DDR_EDE_MME 0x80000000 /* multiple memory errors */
  54. /* Err_Disable */
  55. #define DDR_EDI_MSED 0x1 /* memory select disable */
  56. #define DDR_EDI_SBED 0x4 /* single-bit ECC error disable */
  57. #define DDR_EDI_MBED 0x8 /* multi-bit ECC error disable */
  58. struct fsl_mc_pdata {
  59. char *name;
  60. int edac_idx;
  61. void __iomem *mc_vbase;
  62. int irq;
  63. };
  64. int fsl_mc_err_probe(struct platform_device *op);
  65. int fsl_mc_err_remove(struct platform_device *op);
  66. #endif