uniphier-xdmac.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * External DMA controller driver for UniPhier SoCs
  4. * Copyright 2019 Socionext Inc.
  5. * Author: Kunihiko Hayashi <[email protected]>
  6. */
  7. #include <linux/bitops.h>
  8. #include <linux/bitfield.h>
  9. #include <linux/iopoll.h>
  10. #include <linux/module.h>
  11. #include <linux/of.h>
  12. #include <linux/of_dma.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/slab.h>
  15. #include "dmaengine.h"
  16. #include "virt-dma.h"
  17. #define XDMAC_CH_WIDTH 0x100
  18. #define XDMAC_TFA 0x08
  19. #define XDMAC_TFA_MCNT_MASK GENMASK(23, 16)
  20. #define XDMAC_TFA_MASK GENMASK(5, 0)
  21. #define XDMAC_SADM 0x10
  22. #define XDMAC_SADM_STW_MASK GENMASK(25, 24)
  23. #define XDMAC_SADM_SAM BIT(4)
  24. #define XDMAC_SADM_SAM_FIXED XDMAC_SADM_SAM
  25. #define XDMAC_SADM_SAM_INC 0
  26. #define XDMAC_DADM 0x14
  27. #define XDMAC_DADM_DTW_MASK XDMAC_SADM_STW_MASK
  28. #define XDMAC_DADM_DAM XDMAC_SADM_SAM
  29. #define XDMAC_DADM_DAM_FIXED XDMAC_SADM_SAM_FIXED
  30. #define XDMAC_DADM_DAM_INC XDMAC_SADM_SAM_INC
  31. #define XDMAC_EXSAD 0x18
  32. #define XDMAC_EXDAD 0x1c
  33. #define XDMAC_SAD 0x20
  34. #define XDMAC_DAD 0x24
  35. #define XDMAC_ITS 0x28
  36. #define XDMAC_ITS_MASK GENMASK(25, 0)
  37. #define XDMAC_TNUM 0x2c
  38. #define XDMAC_TNUM_MASK GENMASK(15, 0)
  39. #define XDMAC_TSS 0x30
  40. #define XDMAC_TSS_REQ BIT(0)
  41. #define XDMAC_IEN 0x34
  42. #define XDMAC_IEN_ERRIEN BIT(1)
  43. #define XDMAC_IEN_ENDIEN BIT(0)
  44. #define XDMAC_STAT 0x40
  45. #define XDMAC_STAT_TENF BIT(0)
  46. #define XDMAC_IR 0x44
  47. #define XDMAC_IR_ERRF BIT(1)
  48. #define XDMAC_IR_ENDF BIT(0)
  49. #define XDMAC_ID 0x48
  50. #define XDMAC_ID_ERRIDF BIT(1)
  51. #define XDMAC_ID_ENDIDF BIT(0)
  52. #define XDMAC_MAX_CHANS 16
  53. #define XDMAC_INTERVAL_CLKS 20
  54. #define XDMAC_MAX_WORDS XDMAC_TNUM_MASK
  55. /* cut lower bit for maintain alignment of maximum transfer size */
  56. #define XDMAC_MAX_WORD_SIZE (XDMAC_ITS_MASK & ~GENMASK(3, 0))
  57. #define UNIPHIER_XDMAC_BUSWIDTHS \
  58. (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
  59. BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
  60. BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
  61. BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
  62. struct uniphier_xdmac_desc_node {
  63. dma_addr_t src;
  64. dma_addr_t dst;
  65. u32 burst_size;
  66. u32 nr_burst;
  67. };
  68. struct uniphier_xdmac_desc {
  69. struct virt_dma_desc vd;
  70. unsigned int nr_node;
  71. unsigned int cur_node;
  72. enum dma_transfer_direction dir;
  73. struct uniphier_xdmac_desc_node nodes[];
  74. };
  75. struct uniphier_xdmac_chan {
  76. struct virt_dma_chan vc;
  77. struct uniphier_xdmac_device *xdev;
  78. struct uniphier_xdmac_desc *xd;
  79. void __iomem *reg_ch_base;
  80. struct dma_slave_config sconfig;
  81. int id;
  82. unsigned int req_factor;
  83. };
  84. struct uniphier_xdmac_device {
  85. struct dma_device ddev;
  86. void __iomem *reg_base;
  87. int nr_chans;
  88. struct uniphier_xdmac_chan channels[];
  89. };
  90. static struct uniphier_xdmac_chan *
  91. to_uniphier_xdmac_chan(struct virt_dma_chan *vc)
  92. {
  93. return container_of(vc, struct uniphier_xdmac_chan, vc);
  94. }
  95. static struct uniphier_xdmac_desc *
  96. to_uniphier_xdmac_desc(struct virt_dma_desc *vd)
  97. {
  98. return container_of(vd, struct uniphier_xdmac_desc, vd);
  99. }
  100. /* xc->vc.lock must be held by caller */
  101. static struct uniphier_xdmac_desc *
  102. uniphier_xdmac_next_desc(struct uniphier_xdmac_chan *xc)
  103. {
  104. struct virt_dma_desc *vd;
  105. vd = vchan_next_desc(&xc->vc);
  106. if (!vd)
  107. return NULL;
  108. list_del(&vd->node);
  109. return to_uniphier_xdmac_desc(vd);
  110. }
  111. /* xc->vc.lock must be held by caller */
  112. static void uniphier_xdmac_chan_start(struct uniphier_xdmac_chan *xc,
  113. struct uniphier_xdmac_desc *xd)
  114. {
  115. u32 src_mode, src_width;
  116. u32 dst_mode, dst_width;
  117. dma_addr_t src_addr, dst_addr;
  118. u32 val, its, tnum;
  119. enum dma_slave_buswidth buswidth;
  120. src_addr = xd->nodes[xd->cur_node].src;
  121. dst_addr = xd->nodes[xd->cur_node].dst;
  122. its = xd->nodes[xd->cur_node].burst_size;
  123. tnum = xd->nodes[xd->cur_node].nr_burst;
  124. /*
  125. * The width of MEM side must be 4 or 8 bytes, that does not
  126. * affect that of DEV side and transfer size.
  127. */
  128. if (xd->dir == DMA_DEV_TO_MEM) {
  129. src_mode = XDMAC_SADM_SAM_FIXED;
  130. buswidth = xc->sconfig.src_addr_width;
  131. } else {
  132. src_mode = XDMAC_SADM_SAM_INC;
  133. buswidth = DMA_SLAVE_BUSWIDTH_8_BYTES;
  134. }
  135. src_width = FIELD_PREP(XDMAC_SADM_STW_MASK, __ffs(buswidth));
  136. if (xd->dir == DMA_MEM_TO_DEV) {
  137. dst_mode = XDMAC_DADM_DAM_FIXED;
  138. buswidth = xc->sconfig.dst_addr_width;
  139. } else {
  140. dst_mode = XDMAC_DADM_DAM_INC;
  141. buswidth = DMA_SLAVE_BUSWIDTH_8_BYTES;
  142. }
  143. dst_width = FIELD_PREP(XDMAC_DADM_DTW_MASK, __ffs(buswidth));
  144. /* setup transfer factor */
  145. val = FIELD_PREP(XDMAC_TFA_MCNT_MASK, XDMAC_INTERVAL_CLKS);
  146. val |= FIELD_PREP(XDMAC_TFA_MASK, xc->req_factor);
  147. writel(val, xc->reg_ch_base + XDMAC_TFA);
  148. /* setup the channel */
  149. writel(lower_32_bits(src_addr), xc->reg_ch_base + XDMAC_SAD);
  150. writel(upper_32_bits(src_addr), xc->reg_ch_base + XDMAC_EXSAD);
  151. writel(lower_32_bits(dst_addr), xc->reg_ch_base + XDMAC_DAD);
  152. writel(upper_32_bits(dst_addr), xc->reg_ch_base + XDMAC_EXDAD);
  153. src_mode |= src_width;
  154. dst_mode |= dst_width;
  155. writel(src_mode, xc->reg_ch_base + XDMAC_SADM);
  156. writel(dst_mode, xc->reg_ch_base + XDMAC_DADM);
  157. writel(its, xc->reg_ch_base + XDMAC_ITS);
  158. writel(tnum, xc->reg_ch_base + XDMAC_TNUM);
  159. /* enable interrupt */
  160. writel(XDMAC_IEN_ENDIEN | XDMAC_IEN_ERRIEN,
  161. xc->reg_ch_base + XDMAC_IEN);
  162. /* start XDMAC */
  163. val = readl(xc->reg_ch_base + XDMAC_TSS);
  164. val |= XDMAC_TSS_REQ;
  165. writel(val, xc->reg_ch_base + XDMAC_TSS);
  166. }
  167. /* xc->vc.lock must be held by caller */
  168. static int uniphier_xdmac_chan_stop(struct uniphier_xdmac_chan *xc)
  169. {
  170. u32 val;
  171. /* disable interrupt */
  172. val = readl(xc->reg_ch_base + XDMAC_IEN);
  173. val &= ~(XDMAC_IEN_ENDIEN | XDMAC_IEN_ERRIEN);
  174. writel(val, xc->reg_ch_base + XDMAC_IEN);
  175. /* stop XDMAC */
  176. val = readl(xc->reg_ch_base + XDMAC_TSS);
  177. val &= ~XDMAC_TSS_REQ;
  178. writel(0, xc->reg_ch_base + XDMAC_TSS);
  179. /* wait until transfer is stopped */
  180. return readl_poll_timeout_atomic(xc->reg_ch_base + XDMAC_STAT, val,
  181. !(val & XDMAC_STAT_TENF), 100, 1000);
  182. }
  183. /* xc->vc.lock must be held by caller */
  184. static void uniphier_xdmac_start(struct uniphier_xdmac_chan *xc)
  185. {
  186. struct uniphier_xdmac_desc *xd;
  187. xd = uniphier_xdmac_next_desc(xc);
  188. if (xd)
  189. uniphier_xdmac_chan_start(xc, xd);
  190. /* set desc to chan regardless of xd is null */
  191. xc->xd = xd;
  192. }
  193. static void uniphier_xdmac_chan_irq(struct uniphier_xdmac_chan *xc)
  194. {
  195. u32 stat;
  196. int ret;
  197. spin_lock(&xc->vc.lock);
  198. stat = readl(xc->reg_ch_base + XDMAC_ID);
  199. if (stat & XDMAC_ID_ERRIDF) {
  200. ret = uniphier_xdmac_chan_stop(xc);
  201. if (ret)
  202. dev_err(xc->xdev->ddev.dev,
  203. "DMA transfer error with aborting issue\n");
  204. else
  205. dev_err(xc->xdev->ddev.dev,
  206. "DMA transfer error\n");
  207. } else if ((stat & XDMAC_ID_ENDIDF) && xc->xd) {
  208. xc->xd->cur_node++;
  209. if (xc->xd->cur_node >= xc->xd->nr_node) {
  210. vchan_cookie_complete(&xc->xd->vd);
  211. uniphier_xdmac_start(xc);
  212. } else {
  213. uniphier_xdmac_chan_start(xc, xc->xd);
  214. }
  215. }
  216. /* write bits to clear */
  217. writel(stat, xc->reg_ch_base + XDMAC_IR);
  218. spin_unlock(&xc->vc.lock);
  219. }
  220. static irqreturn_t uniphier_xdmac_irq_handler(int irq, void *dev_id)
  221. {
  222. struct uniphier_xdmac_device *xdev = dev_id;
  223. int i;
  224. for (i = 0; i < xdev->nr_chans; i++)
  225. uniphier_xdmac_chan_irq(&xdev->channels[i]);
  226. return IRQ_HANDLED;
  227. }
  228. static void uniphier_xdmac_free_chan_resources(struct dma_chan *chan)
  229. {
  230. vchan_free_chan_resources(to_virt_chan(chan));
  231. }
  232. static struct dma_async_tx_descriptor *
  233. uniphier_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
  234. dma_addr_t src, size_t len, unsigned long flags)
  235. {
  236. struct virt_dma_chan *vc = to_virt_chan(chan);
  237. struct uniphier_xdmac_desc *xd;
  238. unsigned int nr;
  239. size_t burst_size, tlen;
  240. int i;
  241. if (len > XDMAC_MAX_WORD_SIZE * XDMAC_MAX_WORDS)
  242. return NULL;
  243. nr = 1 + len / XDMAC_MAX_WORD_SIZE;
  244. xd = kzalloc(struct_size(xd, nodes, nr), GFP_NOWAIT);
  245. if (!xd)
  246. return NULL;
  247. for (i = 0; i < nr; i++) {
  248. burst_size = min_t(size_t, len, XDMAC_MAX_WORD_SIZE);
  249. xd->nodes[i].src = src;
  250. xd->nodes[i].dst = dst;
  251. xd->nodes[i].burst_size = burst_size;
  252. xd->nodes[i].nr_burst = len / burst_size;
  253. tlen = rounddown(len, burst_size);
  254. src += tlen;
  255. dst += tlen;
  256. len -= tlen;
  257. }
  258. xd->dir = DMA_MEM_TO_MEM;
  259. xd->nr_node = nr;
  260. xd->cur_node = 0;
  261. return vchan_tx_prep(vc, &xd->vd, flags);
  262. }
  263. static struct dma_async_tx_descriptor *
  264. uniphier_xdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
  265. unsigned int sg_len,
  266. enum dma_transfer_direction direction,
  267. unsigned long flags, void *context)
  268. {
  269. struct virt_dma_chan *vc = to_virt_chan(chan);
  270. struct uniphier_xdmac_chan *xc = to_uniphier_xdmac_chan(vc);
  271. struct uniphier_xdmac_desc *xd;
  272. struct scatterlist *sg;
  273. enum dma_slave_buswidth buswidth;
  274. u32 maxburst;
  275. int i;
  276. if (!is_slave_direction(direction))
  277. return NULL;
  278. if (direction == DMA_DEV_TO_MEM) {
  279. buswidth = xc->sconfig.src_addr_width;
  280. maxburst = xc->sconfig.src_maxburst;
  281. } else {
  282. buswidth = xc->sconfig.dst_addr_width;
  283. maxburst = xc->sconfig.dst_maxburst;
  284. }
  285. if (!maxburst)
  286. maxburst = 1;
  287. if (maxburst > xc->xdev->ddev.max_burst) {
  288. dev_err(xc->xdev->ddev.dev,
  289. "Exceed maximum number of burst words\n");
  290. return NULL;
  291. }
  292. xd = kzalloc(struct_size(xd, nodes, sg_len), GFP_NOWAIT);
  293. if (!xd)
  294. return NULL;
  295. for_each_sg(sgl, sg, sg_len, i) {
  296. xd->nodes[i].src = (direction == DMA_DEV_TO_MEM)
  297. ? xc->sconfig.src_addr : sg_dma_address(sg);
  298. xd->nodes[i].dst = (direction == DMA_MEM_TO_DEV)
  299. ? xc->sconfig.dst_addr : sg_dma_address(sg);
  300. xd->nodes[i].burst_size = maxburst * buswidth;
  301. xd->nodes[i].nr_burst =
  302. sg_dma_len(sg) / xd->nodes[i].burst_size;
  303. /*
  304. * Currently transfer that size doesn't align the unit size
  305. * (the number of burst words * bus-width) is not allowed,
  306. * because the driver does not support the way to transfer
  307. * residue size. As a matter of fact, in order to transfer
  308. * arbitrary size, 'src_maxburst' or 'dst_maxburst' of
  309. * dma_slave_config must be 1.
  310. */
  311. if (sg_dma_len(sg) % xd->nodes[i].burst_size) {
  312. dev_err(xc->xdev->ddev.dev,
  313. "Unaligned transfer size: %d", sg_dma_len(sg));
  314. kfree(xd);
  315. return NULL;
  316. }
  317. if (xd->nodes[i].nr_burst > XDMAC_MAX_WORDS) {
  318. dev_err(xc->xdev->ddev.dev,
  319. "Exceed maximum transfer size");
  320. kfree(xd);
  321. return NULL;
  322. }
  323. }
  324. xd->dir = direction;
  325. xd->nr_node = sg_len;
  326. xd->cur_node = 0;
  327. return vchan_tx_prep(vc, &xd->vd, flags);
  328. }
  329. static int uniphier_xdmac_slave_config(struct dma_chan *chan,
  330. struct dma_slave_config *config)
  331. {
  332. struct virt_dma_chan *vc = to_virt_chan(chan);
  333. struct uniphier_xdmac_chan *xc = to_uniphier_xdmac_chan(vc);
  334. memcpy(&xc->sconfig, config, sizeof(*config));
  335. return 0;
  336. }
  337. static int uniphier_xdmac_terminate_all(struct dma_chan *chan)
  338. {
  339. struct virt_dma_chan *vc = to_virt_chan(chan);
  340. struct uniphier_xdmac_chan *xc = to_uniphier_xdmac_chan(vc);
  341. unsigned long flags;
  342. int ret = 0;
  343. LIST_HEAD(head);
  344. spin_lock_irqsave(&vc->lock, flags);
  345. if (xc->xd) {
  346. vchan_terminate_vdesc(&xc->xd->vd);
  347. xc->xd = NULL;
  348. ret = uniphier_xdmac_chan_stop(xc);
  349. }
  350. vchan_get_all_descriptors(vc, &head);
  351. spin_unlock_irqrestore(&vc->lock, flags);
  352. vchan_dma_desc_free_list(vc, &head);
  353. return ret;
  354. }
  355. static void uniphier_xdmac_synchronize(struct dma_chan *chan)
  356. {
  357. vchan_synchronize(to_virt_chan(chan));
  358. }
  359. static void uniphier_xdmac_issue_pending(struct dma_chan *chan)
  360. {
  361. struct virt_dma_chan *vc = to_virt_chan(chan);
  362. struct uniphier_xdmac_chan *xc = to_uniphier_xdmac_chan(vc);
  363. unsigned long flags;
  364. spin_lock_irqsave(&vc->lock, flags);
  365. if (vchan_issue_pending(vc) && !xc->xd)
  366. uniphier_xdmac_start(xc);
  367. spin_unlock_irqrestore(&vc->lock, flags);
  368. }
  369. static void uniphier_xdmac_desc_free(struct virt_dma_desc *vd)
  370. {
  371. kfree(to_uniphier_xdmac_desc(vd));
  372. }
  373. static void uniphier_xdmac_chan_init(struct uniphier_xdmac_device *xdev,
  374. int ch)
  375. {
  376. struct uniphier_xdmac_chan *xc = &xdev->channels[ch];
  377. xc->xdev = xdev;
  378. xc->reg_ch_base = xdev->reg_base + XDMAC_CH_WIDTH * ch;
  379. xc->vc.desc_free = uniphier_xdmac_desc_free;
  380. vchan_init(&xc->vc, &xdev->ddev);
  381. }
  382. static struct dma_chan *of_dma_uniphier_xlate(struct of_phandle_args *dma_spec,
  383. struct of_dma *ofdma)
  384. {
  385. struct uniphier_xdmac_device *xdev = ofdma->of_dma_data;
  386. int chan_id = dma_spec->args[0];
  387. if (chan_id >= xdev->nr_chans)
  388. return NULL;
  389. xdev->channels[chan_id].id = chan_id;
  390. xdev->channels[chan_id].req_factor = dma_spec->args[1];
  391. return dma_get_slave_channel(&xdev->channels[chan_id].vc.chan);
  392. }
  393. static int uniphier_xdmac_probe(struct platform_device *pdev)
  394. {
  395. struct uniphier_xdmac_device *xdev;
  396. struct device *dev = &pdev->dev;
  397. struct dma_device *ddev;
  398. int irq;
  399. int nr_chans;
  400. int i, ret;
  401. if (of_property_read_u32(dev->of_node, "dma-channels", &nr_chans))
  402. return -EINVAL;
  403. if (nr_chans > XDMAC_MAX_CHANS)
  404. nr_chans = XDMAC_MAX_CHANS;
  405. xdev = devm_kzalloc(dev, struct_size(xdev, channels, nr_chans),
  406. GFP_KERNEL);
  407. if (!xdev)
  408. return -ENOMEM;
  409. xdev->nr_chans = nr_chans;
  410. xdev->reg_base = devm_platform_ioremap_resource(pdev, 0);
  411. if (IS_ERR(xdev->reg_base))
  412. return PTR_ERR(xdev->reg_base);
  413. ddev = &xdev->ddev;
  414. ddev->dev = dev;
  415. dma_cap_zero(ddev->cap_mask);
  416. dma_cap_set(DMA_MEMCPY, ddev->cap_mask);
  417. dma_cap_set(DMA_SLAVE, ddev->cap_mask);
  418. ddev->src_addr_widths = UNIPHIER_XDMAC_BUSWIDTHS;
  419. ddev->dst_addr_widths = UNIPHIER_XDMAC_BUSWIDTHS;
  420. ddev->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) |
  421. BIT(DMA_MEM_TO_MEM);
  422. ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
  423. ddev->max_burst = XDMAC_MAX_WORDS;
  424. ddev->device_free_chan_resources = uniphier_xdmac_free_chan_resources;
  425. ddev->device_prep_dma_memcpy = uniphier_xdmac_prep_dma_memcpy;
  426. ddev->device_prep_slave_sg = uniphier_xdmac_prep_slave_sg;
  427. ddev->device_config = uniphier_xdmac_slave_config;
  428. ddev->device_terminate_all = uniphier_xdmac_terminate_all;
  429. ddev->device_synchronize = uniphier_xdmac_synchronize;
  430. ddev->device_tx_status = dma_cookie_status;
  431. ddev->device_issue_pending = uniphier_xdmac_issue_pending;
  432. INIT_LIST_HEAD(&ddev->channels);
  433. for (i = 0; i < nr_chans; i++)
  434. uniphier_xdmac_chan_init(xdev, i);
  435. irq = platform_get_irq(pdev, 0);
  436. if (irq < 0)
  437. return irq;
  438. ret = devm_request_irq(dev, irq, uniphier_xdmac_irq_handler,
  439. IRQF_SHARED, "xdmac", xdev);
  440. if (ret) {
  441. dev_err(dev, "Failed to request IRQ\n");
  442. return ret;
  443. }
  444. ret = dma_async_device_register(ddev);
  445. if (ret) {
  446. dev_err(dev, "Failed to register XDMA device\n");
  447. return ret;
  448. }
  449. ret = of_dma_controller_register(dev->of_node,
  450. of_dma_uniphier_xlate, xdev);
  451. if (ret) {
  452. dev_err(dev, "Failed to register XDMA controller\n");
  453. goto out_unregister_dmac;
  454. }
  455. platform_set_drvdata(pdev, xdev);
  456. dev_info(&pdev->dev, "UniPhier XDMAC driver (%d channels)\n",
  457. nr_chans);
  458. return 0;
  459. out_unregister_dmac:
  460. dma_async_device_unregister(ddev);
  461. return ret;
  462. }
  463. static int uniphier_xdmac_remove(struct platform_device *pdev)
  464. {
  465. struct uniphier_xdmac_device *xdev = platform_get_drvdata(pdev);
  466. struct dma_device *ddev = &xdev->ddev;
  467. struct dma_chan *chan;
  468. int ret;
  469. /*
  470. * Before reaching here, almost all descriptors have been freed by the
  471. * ->device_free_chan_resources() hook. However, each channel might
  472. * be still holding one descriptor that was on-flight at that moment.
  473. * Terminate it to make sure this hardware is no longer running. Then,
  474. * free the channel resources once again to avoid memory leak.
  475. */
  476. list_for_each_entry(chan, &ddev->channels, device_node) {
  477. ret = dmaengine_terminate_sync(chan);
  478. if (ret)
  479. return ret;
  480. uniphier_xdmac_free_chan_resources(chan);
  481. }
  482. of_dma_controller_free(pdev->dev.of_node);
  483. dma_async_device_unregister(ddev);
  484. return 0;
  485. }
  486. static const struct of_device_id uniphier_xdmac_match[] = {
  487. { .compatible = "socionext,uniphier-xdmac" },
  488. { /* sentinel */ }
  489. };
  490. MODULE_DEVICE_TABLE(of, uniphier_xdmac_match);
  491. static struct platform_driver uniphier_xdmac_driver = {
  492. .probe = uniphier_xdmac_probe,
  493. .remove = uniphier_xdmac_remove,
  494. .driver = {
  495. .name = "uniphier-xdmac",
  496. .of_match_table = uniphier_xdmac_match,
  497. },
  498. };
  499. module_platform_driver(uniphier_xdmac_driver);
  500. MODULE_AUTHOR("Kunihiko Hayashi <[email protected]>");
  501. MODULE_DESCRIPTION("UniPhier external DMA controller driver");
  502. MODULE_LICENSE("GPL v2");