moxart-dma.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * MOXA ART SoCs DMA Engine support.
  4. *
  5. * Copyright (C) 2013 Jonas Jensen
  6. *
  7. * Jonas Jensen <[email protected]>
  8. */
  9. #include <linux/dmaengine.h>
  10. #include <linux/dma-mapping.h>
  11. #include <linux/err.h>
  12. #include <linux/init.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/list.h>
  15. #include <linux/module.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/slab.h>
  18. #include <linux/spinlock.h>
  19. #include <linux/of_address.h>
  20. #include <linux/of_irq.h>
  21. #include <linux/of_dma.h>
  22. #include <linux/bitops.h>
  23. #include <asm/cacheflush.h>
  24. #include "dmaengine.h"
  25. #include "virt-dma.h"
  26. #define APB_DMA_MAX_CHANNEL 4
  27. #define REG_OFF_ADDRESS_SOURCE 0
  28. #define REG_OFF_ADDRESS_DEST 4
  29. #define REG_OFF_CYCLES 8
  30. #define REG_OFF_CTRL 12
  31. #define REG_OFF_CHAN_SIZE 16
  32. #define APB_DMA_ENABLE BIT(0)
  33. #define APB_DMA_FIN_INT_STS BIT(1)
  34. #define APB_DMA_FIN_INT_EN BIT(2)
  35. #define APB_DMA_BURST_MODE BIT(3)
  36. #define APB_DMA_ERR_INT_STS BIT(4)
  37. #define APB_DMA_ERR_INT_EN BIT(5)
  38. /*
  39. * Unset: APB
  40. * Set: AHB
  41. */
  42. #define APB_DMA_SOURCE_SELECT 0x40
  43. #define APB_DMA_DEST_SELECT 0x80
  44. #define APB_DMA_SOURCE 0x100
  45. #define APB_DMA_DEST 0x1000
  46. #define APB_DMA_SOURCE_MASK 0x700
  47. #define APB_DMA_DEST_MASK 0x7000
  48. /*
  49. * 000: No increment
  50. * 001: +1 (Burst=0), +4 (Burst=1)
  51. * 010: +2 (Burst=0), +8 (Burst=1)
  52. * 011: +4 (Burst=0), +16 (Burst=1)
  53. * 101: -1 (Burst=0), -4 (Burst=1)
  54. * 110: -2 (Burst=0), -8 (Burst=1)
  55. * 111: -4 (Burst=0), -16 (Burst=1)
  56. */
  57. #define APB_DMA_SOURCE_INC_0 0
  58. #define APB_DMA_SOURCE_INC_1_4 0x100
  59. #define APB_DMA_SOURCE_INC_2_8 0x200
  60. #define APB_DMA_SOURCE_INC_4_16 0x300
  61. #define APB_DMA_SOURCE_DEC_1_4 0x500
  62. #define APB_DMA_SOURCE_DEC_2_8 0x600
  63. #define APB_DMA_SOURCE_DEC_4_16 0x700
  64. #define APB_DMA_DEST_INC_0 0
  65. #define APB_DMA_DEST_INC_1_4 0x1000
  66. #define APB_DMA_DEST_INC_2_8 0x2000
  67. #define APB_DMA_DEST_INC_4_16 0x3000
  68. #define APB_DMA_DEST_DEC_1_4 0x5000
  69. #define APB_DMA_DEST_DEC_2_8 0x6000
  70. #define APB_DMA_DEST_DEC_4_16 0x7000
  71. /*
  72. * Request signal select source/destination address for DMA hardware handshake.
  73. *
  74. * The request line number is a property of the DMA controller itself,
  75. * e.g. MMC must always request channels where dma_slave_config->slave_id is 5.
  76. *
  77. * 0: No request / Grant signal
  78. * 1-15: Request / Grant signal
  79. */
  80. #define APB_DMA_SOURCE_REQ_NO 0x1000000
  81. #define APB_DMA_SOURCE_REQ_NO_MASK 0xf000000
  82. #define APB_DMA_DEST_REQ_NO 0x10000
  83. #define APB_DMA_DEST_REQ_NO_MASK 0xf0000
  84. #define APB_DMA_DATA_WIDTH 0x100000
  85. #define APB_DMA_DATA_WIDTH_MASK 0x300000
  86. /*
  87. * Data width of transfer:
  88. *
  89. * 00: Word
  90. * 01: Half
  91. * 10: Byte
  92. */
  93. #define APB_DMA_DATA_WIDTH_4 0
  94. #define APB_DMA_DATA_WIDTH_2 0x100000
  95. #define APB_DMA_DATA_WIDTH_1 0x200000
  96. #define APB_DMA_CYCLES_MASK 0x00ffffff
  97. #define MOXART_DMA_DATA_TYPE_S8 0x00
  98. #define MOXART_DMA_DATA_TYPE_S16 0x01
  99. #define MOXART_DMA_DATA_TYPE_S32 0x02
  100. struct moxart_sg {
  101. dma_addr_t addr;
  102. uint32_t len;
  103. };
  104. struct moxart_desc {
  105. enum dma_transfer_direction dma_dir;
  106. dma_addr_t dev_addr;
  107. unsigned int sglen;
  108. unsigned int dma_cycles;
  109. struct virt_dma_desc vd;
  110. uint8_t es;
  111. struct moxart_sg sg[];
  112. };
  113. struct moxart_chan {
  114. struct virt_dma_chan vc;
  115. void __iomem *base;
  116. struct moxart_desc *desc;
  117. struct dma_slave_config cfg;
  118. bool allocated;
  119. bool error;
  120. int ch_num;
  121. unsigned int line_reqno;
  122. unsigned int sgidx;
  123. };
  124. struct moxart_dmadev {
  125. struct dma_device dma_slave;
  126. struct moxart_chan slave_chans[APB_DMA_MAX_CHANNEL];
  127. unsigned int irq;
  128. };
  129. struct moxart_filter_data {
  130. struct moxart_dmadev *mdc;
  131. struct of_phandle_args *dma_spec;
  132. };
  133. static const unsigned int es_bytes[] = {
  134. [MOXART_DMA_DATA_TYPE_S8] = 1,
  135. [MOXART_DMA_DATA_TYPE_S16] = 2,
  136. [MOXART_DMA_DATA_TYPE_S32] = 4,
  137. };
  138. static struct device *chan2dev(struct dma_chan *chan)
  139. {
  140. return &chan->dev->device;
  141. }
  142. static inline struct moxart_chan *to_moxart_dma_chan(struct dma_chan *c)
  143. {
  144. return container_of(c, struct moxart_chan, vc.chan);
  145. }
  146. static inline struct moxart_desc *to_moxart_dma_desc(
  147. struct dma_async_tx_descriptor *t)
  148. {
  149. return container_of(t, struct moxart_desc, vd.tx);
  150. }
  151. static void moxart_dma_desc_free(struct virt_dma_desc *vd)
  152. {
  153. kfree(container_of(vd, struct moxart_desc, vd));
  154. }
  155. static int moxart_terminate_all(struct dma_chan *chan)
  156. {
  157. struct moxart_chan *ch = to_moxart_dma_chan(chan);
  158. unsigned long flags;
  159. LIST_HEAD(head);
  160. u32 ctrl;
  161. dev_dbg(chan2dev(chan), "%s: ch=%p\n", __func__, ch);
  162. spin_lock_irqsave(&ch->vc.lock, flags);
  163. if (ch->desc) {
  164. moxart_dma_desc_free(&ch->desc->vd);
  165. ch->desc = NULL;
  166. }
  167. ctrl = readl(ch->base + REG_OFF_CTRL);
  168. ctrl &= ~(APB_DMA_ENABLE | APB_DMA_FIN_INT_EN | APB_DMA_ERR_INT_EN);
  169. writel(ctrl, ch->base + REG_OFF_CTRL);
  170. vchan_get_all_descriptors(&ch->vc, &head);
  171. spin_unlock_irqrestore(&ch->vc.lock, flags);
  172. vchan_dma_desc_free_list(&ch->vc, &head);
  173. return 0;
  174. }
  175. static int moxart_slave_config(struct dma_chan *chan,
  176. struct dma_slave_config *cfg)
  177. {
  178. struct moxart_chan *ch = to_moxart_dma_chan(chan);
  179. u32 ctrl;
  180. ch->cfg = *cfg;
  181. ctrl = readl(ch->base + REG_OFF_CTRL);
  182. ctrl |= APB_DMA_BURST_MODE;
  183. ctrl &= ~(APB_DMA_DEST_MASK | APB_DMA_SOURCE_MASK);
  184. ctrl &= ~(APB_DMA_DEST_REQ_NO_MASK | APB_DMA_SOURCE_REQ_NO_MASK);
  185. switch (ch->cfg.src_addr_width) {
  186. case DMA_SLAVE_BUSWIDTH_1_BYTE:
  187. ctrl |= APB_DMA_DATA_WIDTH_1;
  188. if (ch->cfg.direction != DMA_MEM_TO_DEV)
  189. ctrl |= APB_DMA_DEST_INC_1_4;
  190. else
  191. ctrl |= APB_DMA_SOURCE_INC_1_4;
  192. break;
  193. case DMA_SLAVE_BUSWIDTH_2_BYTES:
  194. ctrl |= APB_DMA_DATA_WIDTH_2;
  195. if (ch->cfg.direction != DMA_MEM_TO_DEV)
  196. ctrl |= APB_DMA_DEST_INC_2_8;
  197. else
  198. ctrl |= APB_DMA_SOURCE_INC_2_8;
  199. break;
  200. case DMA_SLAVE_BUSWIDTH_4_BYTES:
  201. ctrl &= ~APB_DMA_DATA_WIDTH;
  202. if (ch->cfg.direction != DMA_MEM_TO_DEV)
  203. ctrl |= APB_DMA_DEST_INC_4_16;
  204. else
  205. ctrl |= APB_DMA_SOURCE_INC_4_16;
  206. break;
  207. default:
  208. return -EINVAL;
  209. }
  210. if (ch->cfg.direction == DMA_MEM_TO_DEV) {
  211. ctrl &= ~APB_DMA_DEST_SELECT;
  212. ctrl |= APB_DMA_SOURCE_SELECT;
  213. ctrl |= (ch->line_reqno << 16 &
  214. APB_DMA_DEST_REQ_NO_MASK);
  215. } else {
  216. ctrl |= APB_DMA_DEST_SELECT;
  217. ctrl &= ~APB_DMA_SOURCE_SELECT;
  218. ctrl |= (ch->line_reqno << 24 &
  219. APB_DMA_SOURCE_REQ_NO_MASK);
  220. }
  221. writel(ctrl, ch->base + REG_OFF_CTRL);
  222. return 0;
  223. }
  224. static struct dma_async_tx_descriptor *moxart_prep_slave_sg(
  225. struct dma_chan *chan, struct scatterlist *sgl,
  226. unsigned int sg_len, enum dma_transfer_direction dir,
  227. unsigned long tx_flags, void *context)
  228. {
  229. struct moxart_chan *ch = to_moxart_dma_chan(chan);
  230. struct moxart_desc *d;
  231. enum dma_slave_buswidth dev_width;
  232. dma_addr_t dev_addr;
  233. struct scatterlist *sgent;
  234. unsigned int es;
  235. unsigned int i;
  236. if (!is_slave_direction(dir)) {
  237. dev_err(chan2dev(chan), "%s: invalid DMA direction\n",
  238. __func__);
  239. return NULL;
  240. }
  241. if (dir == DMA_DEV_TO_MEM) {
  242. dev_addr = ch->cfg.src_addr;
  243. dev_width = ch->cfg.src_addr_width;
  244. } else {
  245. dev_addr = ch->cfg.dst_addr;
  246. dev_width = ch->cfg.dst_addr_width;
  247. }
  248. switch (dev_width) {
  249. case DMA_SLAVE_BUSWIDTH_1_BYTE:
  250. es = MOXART_DMA_DATA_TYPE_S8;
  251. break;
  252. case DMA_SLAVE_BUSWIDTH_2_BYTES:
  253. es = MOXART_DMA_DATA_TYPE_S16;
  254. break;
  255. case DMA_SLAVE_BUSWIDTH_4_BYTES:
  256. es = MOXART_DMA_DATA_TYPE_S32;
  257. break;
  258. default:
  259. dev_err(chan2dev(chan), "%s: unsupported data width (%u)\n",
  260. __func__, dev_width);
  261. return NULL;
  262. }
  263. d = kzalloc(struct_size(d, sg, sg_len), GFP_ATOMIC);
  264. if (!d)
  265. return NULL;
  266. d->dma_dir = dir;
  267. d->dev_addr = dev_addr;
  268. d->es = es;
  269. for_each_sg(sgl, sgent, sg_len, i) {
  270. d->sg[i].addr = sg_dma_address(sgent);
  271. d->sg[i].len = sg_dma_len(sgent);
  272. }
  273. d->sglen = sg_len;
  274. ch->error = 0;
  275. return vchan_tx_prep(&ch->vc, &d->vd, tx_flags);
  276. }
  277. static struct dma_chan *moxart_of_xlate(struct of_phandle_args *dma_spec,
  278. struct of_dma *ofdma)
  279. {
  280. struct moxart_dmadev *mdc = ofdma->of_dma_data;
  281. struct dma_chan *chan;
  282. struct moxart_chan *ch;
  283. chan = dma_get_any_slave_channel(&mdc->dma_slave);
  284. if (!chan)
  285. return NULL;
  286. ch = to_moxart_dma_chan(chan);
  287. ch->line_reqno = dma_spec->args[0];
  288. return chan;
  289. }
  290. static int moxart_alloc_chan_resources(struct dma_chan *chan)
  291. {
  292. struct moxart_chan *ch = to_moxart_dma_chan(chan);
  293. dev_dbg(chan2dev(chan), "%s: allocating channel #%u\n",
  294. __func__, ch->ch_num);
  295. ch->allocated = 1;
  296. return 0;
  297. }
  298. static void moxart_free_chan_resources(struct dma_chan *chan)
  299. {
  300. struct moxart_chan *ch = to_moxart_dma_chan(chan);
  301. vchan_free_chan_resources(&ch->vc);
  302. dev_dbg(chan2dev(chan), "%s: freeing channel #%u\n",
  303. __func__, ch->ch_num);
  304. ch->allocated = 0;
  305. }
  306. static void moxart_dma_set_params(struct moxart_chan *ch, dma_addr_t src_addr,
  307. dma_addr_t dst_addr)
  308. {
  309. writel(src_addr, ch->base + REG_OFF_ADDRESS_SOURCE);
  310. writel(dst_addr, ch->base + REG_OFF_ADDRESS_DEST);
  311. }
  312. static void moxart_set_transfer_params(struct moxart_chan *ch, unsigned int len)
  313. {
  314. struct moxart_desc *d = ch->desc;
  315. unsigned int sglen_div = es_bytes[d->es];
  316. d->dma_cycles = len >> sglen_div;
  317. /*
  318. * There are 4 cycles on 64 bytes copied, i.e. one cycle copies 16
  319. * bytes ( when width is APB_DMAB_DATA_WIDTH_4 ).
  320. */
  321. writel(d->dma_cycles, ch->base + REG_OFF_CYCLES);
  322. dev_dbg(chan2dev(&ch->vc.chan), "%s: set %u DMA cycles (len=%u)\n",
  323. __func__, d->dma_cycles, len);
  324. }
  325. static void moxart_start_dma(struct moxart_chan *ch)
  326. {
  327. u32 ctrl;
  328. ctrl = readl(ch->base + REG_OFF_CTRL);
  329. ctrl |= (APB_DMA_ENABLE | APB_DMA_FIN_INT_EN | APB_DMA_ERR_INT_EN);
  330. writel(ctrl, ch->base + REG_OFF_CTRL);
  331. }
  332. static void moxart_dma_start_sg(struct moxart_chan *ch, unsigned int idx)
  333. {
  334. struct moxart_desc *d = ch->desc;
  335. struct moxart_sg *sg = ch->desc->sg + idx;
  336. if (ch->desc->dma_dir == DMA_MEM_TO_DEV)
  337. moxart_dma_set_params(ch, sg->addr, d->dev_addr);
  338. else if (ch->desc->dma_dir == DMA_DEV_TO_MEM)
  339. moxart_dma_set_params(ch, d->dev_addr, sg->addr);
  340. moxart_set_transfer_params(ch, sg->len);
  341. moxart_start_dma(ch);
  342. }
  343. static void moxart_dma_start_desc(struct dma_chan *chan)
  344. {
  345. struct moxart_chan *ch = to_moxart_dma_chan(chan);
  346. struct virt_dma_desc *vd;
  347. vd = vchan_next_desc(&ch->vc);
  348. if (!vd) {
  349. ch->desc = NULL;
  350. return;
  351. }
  352. list_del(&vd->node);
  353. ch->desc = to_moxart_dma_desc(&vd->tx);
  354. ch->sgidx = 0;
  355. moxart_dma_start_sg(ch, 0);
  356. }
  357. static void moxart_issue_pending(struct dma_chan *chan)
  358. {
  359. struct moxart_chan *ch = to_moxart_dma_chan(chan);
  360. unsigned long flags;
  361. spin_lock_irqsave(&ch->vc.lock, flags);
  362. if (vchan_issue_pending(&ch->vc) && !ch->desc)
  363. moxart_dma_start_desc(chan);
  364. spin_unlock_irqrestore(&ch->vc.lock, flags);
  365. }
  366. static size_t moxart_dma_desc_size(struct moxart_desc *d,
  367. unsigned int completed_sgs)
  368. {
  369. unsigned int i;
  370. size_t size;
  371. for (size = i = completed_sgs; i < d->sglen; i++)
  372. size += d->sg[i].len;
  373. return size;
  374. }
  375. static size_t moxart_dma_desc_size_in_flight(struct moxart_chan *ch)
  376. {
  377. size_t size;
  378. unsigned int completed_cycles, cycles;
  379. size = moxart_dma_desc_size(ch->desc, ch->sgidx);
  380. cycles = readl(ch->base + REG_OFF_CYCLES);
  381. completed_cycles = (ch->desc->dma_cycles - cycles);
  382. size -= completed_cycles << es_bytes[ch->desc->es];
  383. dev_dbg(chan2dev(&ch->vc.chan), "%s: size=%zu\n", __func__, size);
  384. return size;
  385. }
  386. static enum dma_status moxart_tx_status(struct dma_chan *chan,
  387. dma_cookie_t cookie,
  388. struct dma_tx_state *txstate)
  389. {
  390. struct moxart_chan *ch = to_moxart_dma_chan(chan);
  391. struct virt_dma_desc *vd;
  392. struct moxart_desc *d;
  393. enum dma_status ret;
  394. unsigned long flags;
  395. /*
  396. * dma_cookie_status() assigns initial residue value.
  397. */
  398. ret = dma_cookie_status(chan, cookie, txstate);
  399. spin_lock_irqsave(&ch->vc.lock, flags);
  400. vd = vchan_find_desc(&ch->vc, cookie);
  401. if (vd) {
  402. d = to_moxart_dma_desc(&vd->tx);
  403. txstate->residue = moxart_dma_desc_size(d, 0);
  404. } else if (ch->desc && ch->desc->vd.tx.cookie == cookie) {
  405. txstate->residue = moxart_dma_desc_size_in_flight(ch);
  406. }
  407. spin_unlock_irqrestore(&ch->vc.lock, flags);
  408. if (ch->error)
  409. return DMA_ERROR;
  410. return ret;
  411. }
  412. static void moxart_dma_init(struct dma_device *dma, struct device *dev)
  413. {
  414. dma->device_prep_slave_sg = moxart_prep_slave_sg;
  415. dma->device_alloc_chan_resources = moxart_alloc_chan_resources;
  416. dma->device_free_chan_resources = moxart_free_chan_resources;
  417. dma->device_issue_pending = moxart_issue_pending;
  418. dma->device_tx_status = moxart_tx_status;
  419. dma->device_config = moxart_slave_config;
  420. dma->device_terminate_all = moxart_terminate_all;
  421. dma->dev = dev;
  422. INIT_LIST_HEAD(&dma->channels);
  423. }
  424. static irqreturn_t moxart_dma_interrupt(int irq, void *devid)
  425. {
  426. struct moxart_dmadev *mc = devid;
  427. struct moxart_chan *ch = &mc->slave_chans[0];
  428. unsigned int i;
  429. u32 ctrl;
  430. dev_dbg(chan2dev(&ch->vc.chan), "%s\n", __func__);
  431. for (i = 0; i < APB_DMA_MAX_CHANNEL; i++, ch++) {
  432. if (!ch->allocated)
  433. continue;
  434. ctrl = readl(ch->base + REG_OFF_CTRL);
  435. dev_dbg(chan2dev(&ch->vc.chan), "%s: ch=%p ch->base=%p ctrl=%x\n",
  436. __func__, ch, ch->base, ctrl);
  437. if (ctrl & APB_DMA_FIN_INT_STS) {
  438. ctrl &= ~APB_DMA_FIN_INT_STS;
  439. if (ch->desc) {
  440. spin_lock(&ch->vc.lock);
  441. if (++ch->sgidx < ch->desc->sglen) {
  442. moxart_dma_start_sg(ch, ch->sgidx);
  443. } else {
  444. vchan_cookie_complete(&ch->desc->vd);
  445. moxart_dma_start_desc(&ch->vc.chan);
  446. }
  447. spin_unlock(&ch->vc.lock);
  448. }
  449. }
  450. if (ctrl & APB_DMA_ERR_INT_STS) {
  451. ctrl &= ~APB_DMA_ERR_INT_STS;
  452. ch->error = 1;
  453. }
  454. writel(ctrl, ch->base + REG_OFF_CTRL);
  455. }
  456. return IRQ_HANDLED;
  457. }
  458. static int moxart_probe(struct platform_device *pdev)
  459. {
  460. struct device *dev = &pdev->dev;
  461. struct device_node *node = dev->of_node;
  462. struct resource *res;
  463. void __iomem *dma_base_addr;
  464. int ret, i;
  465. unsigned int irq;
  466. struct moxart_chan *ch;
  467. struct moxart_dmadev *mdc;
  468. mdc = devm_kzalloc(dev, sizeof(*mdc), GFP_KERNEL);
  469. if (!mdc)
  470. return -ENOMEM;
  471. irq = irq_of_parse_and_map(node, 0);
  472. if (!irq) {
  473. dev_err(dev, "no IRQ resource\n");
  474. return -EINVAL;
  475. }
  476. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  477. dma_base_addr = devm_ioremap_resource(dev, res);
  478. if (IS_ERR(dma_base_addr))
  479. return PTR_ERR(dma_base_addr);
  480. dma_cap_zero(mdc->dma_slave.cap_mask);
  481. dma_cap_set(DMA_SLAVE, mdc->dma_slave.cap_mask);
  482. dma_cap_set(DMA_PRIVATE, mdc->dma_slave.cap_mask);
  483. moxart_dma_init(&mdc->dma_slave, dev);
  484. ch = &mdc->slave_chans[0];
  485. for (i = 0; i < APB_DMA_MAX_CHANNEL; i++, ch++) {
  486. ch->ch_num = i;
  487. ch->base = dma_base_addr + i * REG_OFF_CHAN_SIZE;
  488. ch->allocated = 0;
  489. ch->vc.desc_free = moxart_dma_desc_free;
  490. vchan_init(&ch->vc, &mdc->dma_slave);
  491. dev_dbg(dev, "%s: chs[%d]: ch->ch_num=%u ch->base=%p\n",
  492. __func__, i, ch->ch_num, ch->base);
  493. }
  494. platform_set_drvdata(pdev, mdc);
  495. ret = devm_request_irq(dev, irq, moxart_dma_interrupt, 0,
  496. "moxart-dma-engine", mdc);
  497. if (ret) {
  498. dev_err(dev, "devm_request_irq failed\n");
  499. return ret;
  500. }
  501. mdc->irq = irq;
  502. ret = dma_async_device_register(&mdc->dma_slave);
  503. if (ret) {
  504. dev_err(dev, "dma_async_device_register failed\n");
  505. return ret;
  506. }
  507. ret = of_dma_controller_register(node, moxart_of_xlate, mdc);
  508. if (ret) {
  509. dev_err(dev, "of_dma_controller_register failed\n");
  510. dma_async_device_unregister(&mdc->dma_slave);
  511. return ret;
  512. }
  513. dev_dbg(dev, "%s: IRQ=%u\n", __func__, irq);
  514. return 0;
  515. }
  516. static int moxart_remove(struct platform_device *pdev)
  517. {
  518. struct moxart_dmadev *m = platform_get_drvdata(pdev);
  519. devm_free_irq(&pdev->dev, m->irq, m);
  520. dma_async_device_unregister(&m->dma_slave);
  521. if (pdev->dev.of_node)
  522. of_dma_controller_free(pdev->dev.of_node);
  523. return 0;
  524. }
  525. static const struct of_device_id moxart_dma_match[] = {
  526. { .compatible = "moxa,moxart-dma" },
  527. { }
  528. };
  529. MODULE_DEVICE_TABLE(of, moxart_dma_match);
  530. static struct platform_driver moxart_driver = {
  531. .probe = moxart_probe,
  532. .remove = moxart_remove,
  533. .driver = {
  534. .name = "moxart-dma-engine",
  535. .of_match_table = moxart_dma_match,
  536. },
  537. };
  538. static int moxart_init(void)
  539. {
  540. return platform_driver_register(&moxart_driver);
  541. }
  542. subsys_initcall(moxart_init);
  543. static void __exit moxart_exit(void)
  544. {
  545. platform_driver_unregister(&moxart_driver);
  546. }
  547. module_exit(moxart_exit);
  548. MODULE_AUTHOR("Jonas Jensen <[email protected]>");
  549. MODULE_DESCRIPTION("MOXART DMA engine driver");
  550. MODULE_LICENSE("GPL v2");