dw-axi-dmac.h 12 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. // (C) 2017-2018 Synopsys, Inc. (www.synopsys.com)
  3. /*
  4. * Synopsys DesignWare AXI DMA Controller driver.
  5. *
  6. * Author: Eugeniy Paltsev <[email protected]>
  7. */
  8. #ifndef _AXI_DMA_PLATFORM_H
  9. #define _AXI_DMA_PLATFORM_H
  10. #include <linux/bitops.h>
  11. #include <linux/clk.h>
  12. #include <linux/device.h>
  13. #include <linux/dmaengine.h>
  14. #include <linux/types.h>
  15. #include "../virt-dma.h"
  16. #define DMAC_MAX_CHANNELS 16
  17. #define DMAC_MAX_MASTERS 2
  18. #define DMAC_MAX_BLK_SIZE 0x200000
  19. struct dw_axi_dma_hcfg {
  20. u32 nr_channels;
  21. u32 nr_masters;
  22. u32 m_data_width;
  23. u32 block_size[DMAC_MAX_CHANNELS];
  24. u32 priority[DMAC_MAX_CHANNELS];
  25. /* maximum supported axi burst length */
  26. u32 axi_rw_burst_len;
  27. /* Register map for DMAX_NUM_CHANNELS <= 8 */
  28. bool reg_map_8_channels;
  29. bool restrict_axi_burst_len;
  30. };
  31. struct axi_dma_chan {
  32. struct axi_dma_chip *chip;
  33. void __iomem *chan_regs;
  34. u8 id;
  35. u8 hw_handshake_num;
  36. atomic_t descs_allocated;
  37. struct dma_pool *desc_pool;
  38. struct virt_dma_chan vc;
  39. struct axi_dma_desc *desc;
  40. struct dma_slave_config config;
  41. enum dma_transfer_direction direction;
  42. bool cyclic;
  43. /* these other elements are all protected by vc.lock */
  44. bool is_paused;
  45. };
  46. struct dw_axi_dma {
  47. struct dma_device dma;
  48. struct dw_axi_dma_hcfg *hdata;
  49. struct device_dma_parameters dma_parms;
  50. /* channels */
  51. struct axi_dma_chan *chan;
  52. };
  53. struct axi_dma_chip {
  54. struct device *dev;
  55. int irq;
  56. void __iomem *regs;
  57. void __iomem *apb_regs;
  58. struct clk *core_clk;
  59. struct clk *cfgr_clk;
  60. struct dw_axi_dma *dw;
  61. };
  62. /* LLI == Linked List Item */
  63. struct __packed axi_dma_lli {
  64. __le64 sar;
  65. __le64 dar;
  66. __le32 block_ts_lo;
  67. __le32 block_ts_hi;
  68. __le64 llp;
  69. __le32 ctl_lo;
  70. __le32 ctl_hi;
  71. __le32 sstat;
  72. __le32 dstat;
  73. __le32 status_lo;
  74. __le32 status_hi;
  75. __le32 reserved_lo;
  76. __le32 reserved_hi;
  77. };
  78. struct axi_dma_hw_desc {
  79. struct axi_dma_lli *lli;
  80. dma_addr_t llp;
  81. u32 len;
  82. };
  83. struct axi_dma_desc {
  84. struct axi_dma_hw_desc *hw_desc;
  85. struct virt_dma_desc vd;
  86. struct axi_dma_chan *chan;
  87. u32 completed_blocks;
  88. u32 length;
  89. u32 period_len;
  90. };
  91. struct axi_dma_chan_config {
  92. u8 dst_multblk_type;
  93. u8 src_multblk_type;
  94. u8 dst_per;
  95. u8 src_per;
  96. u8 tt_fc;
  97. u8 prior;
  98. u8 hs_sel_dst;
  99. u8 hs_sel_src;
  100. };
  101. static inline struct device *dchan2dev(struct dma_chan *dchan)
  102. {
  103. return &dchan->dev->device;
  104. }
  105. static inline struct device *chan2dev(struct axi_dma_chan *chan)
  106. {
  107. return &chan->vc.chan.dev->device;
  108. }
  109. static inline struct axi_dma_desc *vd_to_axi_desc(struct virt_dma_desc *vd)
  110. {
  111. return container_of(vd, struct axi_dma_desc, vd);
  112. }
  113. static inline struct axi_dma_chan *vc_to_axi_dma_chan(struct virt_dma_chan *vc)
  114. {
  115. return container_of(vc, struct axi_dma_chan, vc);
  116. }
  117. static inline struct axi_dma_chan *dchan_to_axi_dma_chan(struct dma_chan *dchan)
  118. {
  119. return vc_to_axi_dma_chan(to_virt_chan(dchan));
  120. }
  121. #define COMMON_REG_LEN 0x100
  122. #define CHAN_REG_LEN 0x100
  123. /* Common registers offset */
  124. #define DMAC_ID 0x000 /* R DMAC ID */
  125. #define DMAC_COMPVER 0x008 /* R DMAC Component Version */
  126. #define DMAC_CFG 0x010 /* R/W DMAC Configuration */
  127. #define DMAC_CHEN 0x018 /* R/W DMAC Channel Enable */
  128. #define DMAC_CHEN_L 0x018 /* R/W DMAC Channel Enable 00-31 */
  129. #define DMAC_CHEN_H 0x01C /* R/W DMAC Channel Enable 32-63 */
  130. #define DMAC_CHSUSPREG 0x020 /* R/W DMAC Channel Suspend */
  131. #define DMAC_CHABORTREG 0x028 /* R/W DMAC Channel Abort */
  132. #define DMAC_INTSTATUS 0x030 /* R DMAC Interrupt Status */
  133. #define DMAC_COMMON_INTCLEAR 0x038 /* W DMAC Interrupt Clear */
  134. #define DMAC_COMMON_INTSTATUS_ENA 0x040 /* R DMAC Interrupt Status Enable */
  135. #define DMAC_COMMON_INTSIGNAL_ENA 0x048 /* R/W DMAC Interrupt Signal Enable */
  136. #define DMAC_COMMON_INTSTATUS 0x050 /* R DMAC Interrupt Status */
  137. #define DMAC_RESET 0x058 /* R DMAC Reset Register1 */
  138. /* DMA channel registers offset */
  139. #define CH_SAR 0x000 /* R/W Chan Source Address */
  140. #define CH_DAR 0x008 /* R/W Chan Destination Address */
  141. #define CH_BLOCK_TS 0x010 /* R/W Chan Block Transfer Size */
  142. #define CH_CTL 0x018 /* R/W Chan Control */
  143. #define CH_CTL_L 0x018 /* R/W Chan Control 00-31 */
  144. #define CH_CTL_H 0x01C /* R/W Chan Control 32-63 */
  145. #define CH_CFG 0x020 /* R/W Chan Configuration */
  146. #define CH_CFG_L 0x020 /* R/W Chan Configuration 00-31 */
  147. #define CH_CFG_H 0x024 /* R/W Chan Configuration 32-63 */
  148. #define CH_LLP 0x028 /* R/W Chan Linked List Pointer */
  149. #define CH_STATUS 0x030 /* R Chan Status */
  150. #define CH_SWHSSRC 0x038 /* R/W Chan SW Handshake Source */
  151. #define CH_SWHSDST 0x040 /* R/W Chan SW Handshake Destination */
  152. #define CH_BLK_TFR_RESUMEREQ 0x048 /* W Chan Block Transfer Resume Req */
  153. #define CH_AXI_ID 0x050 /* R/W Chan AXI ID */
  154. #define CH_AXI_QOS 0x058 /* R/W Chan AXI QOS */
  155. #define CH_SSTAT 0x060 /* R Chan Source Status */
  156. #define CH_DSTAT 0x068 /* R Chan Destination Status */
  157. #define CH_SSTATAR 0x070 /* R/W Chan Source Status Fetch Addr */
  158. #define CH_DSTATAR 0x078 /* R/W Chan Destination Status Fetch Addr */
  159. #define CH_INTSTATUS_ENA 0x080 /* R/W Chan Interrupt Status Enable */
  160. #define CH_INTSTATUS 0x088 /* R/W Chan Interrupt Status */
  161. #define CH_INTSIGNAL_ENA 0x090 /* R/W Chan Interrupt Signal Enable */
  162. #define CH_INTCLEAR 0x098 /* W Chan Interrupt Clear */
  163. /* These Apb registers are used by Intel KeemBay SoC */
  164. #define DMAC_APB_CFG 0x000 /* DMAC Apb Configuration Register */
  165. #define DMAC_APB_STAT 0x004 /* DMAC Apb Status Register */
  166. #define DMAC_APB_DEBUG_STAT_0 0x008 /* DMAC Apb Debug Status Register 0 */
  167. #define DMAC_APB_DEBUG_STAT_1 0x00C /* DMAC Apb Debug Status Register 1 */
  168. #define DMAC_APB_HW_HS_SEL_0 0x010 /* DMAC Apb HW HS register 0 */
  169. #define DMAC_APB_HW_HS_SEL_1 0x014 /* DMAC Apb HW HS register 1 */
  170. #define DMAC_APB_LPI 0x018 /* DMAC Apb Low Power Interface Reg */
  171. #define DMAC_APB_BYTE_WR_CH_EN 0x01C /* DMAC Apb Byte Write Enable */
  172. #define DMAC_APB_HALFWORD_WR_CH_EN 0x020 /* DMAC Halfword write enables */
  173. #define UNUSED_CHANNEL 0x3F /* Set unused DMA channel to 0x3F */
  174. #define DMA_APB_HS_SEL_BIT_SIZE 0x08 /* HW handshake bits per channel */
  175. #define DMA_APB_HS_SEL_MASK 0xFF /* HW handshake select masks */
  176. #define MAX_BLOCK_SIZE 0x1000 /* 1024 blocks * 4 bytes data width */
  177. #define DMA_REG_MAP_CH_REF 0x08 /* Channel count to choose register map */
  178. /* DMAC_CFG */
  179. #define DMAC_EN_POS 0
  180. #define DMAC_EN_MASK BIT(DMAC_EN_POS)
  181. #define INT_EN_POS 1
  182. #define INT_EN_MASK BIT(INT_EN_POS)
  183. /* DMAC_CHEN */
  184. #define DMAC_CHAN_EN_SHIFT 0
  185. #define DMAC_CHAN_EN_WE_SHIFT 8
  186. #define DMAC_CHAN_SUSP_SHIFT 16
  187. #define DMAC_CHAN_SUSP_WE_SHIFT 24
  188. /* DMAC_CHEN2 */
  189. #define DMAC_CHAN_EN2_WE_SHIFT 16
  190. /* DMAC_CHSUSP */
  191. #define DMAC_CHAN_SUSP2_SHIFT 0
  192. #define DMAC_CHAN_SUSP2_WE_SHIFT 16
  193. /* CH_CTL_H */
  194. #define CH_CTL_H_ARLEN_EN BIT(6)
  195. #define CH_CTL_H_ARLEN_POS 7
  196. #define CH_CTL_H_AWLEN_EN BIT(15)
  197. #define CH_CTL_H_AWLEN_POS 16
  198. enum {
  199. DWAXIDMAC_ARWLEN_1 = 0,
  200. DWAXIDMAC_ARWLEN_2 = 1,
  201. DWAXIDMAC_ARWLEN_4 = 3,
  202. DWAXIDMAC_ARWLEN_8 = 7,
  203. DWAXIDMAC_ARWLEN_16 = 15,
  204. DWAXIDMAC_ARWLEN_32 = 31,
  205. DWAXIDMAC_ARWLEN_64 = 63,
  206. DWAXIDMAC_ARWLEN_128 = 127,
  207. DWAXIDMAC_ARWLEN_256 = 255,
  208. DWAXIDMAC_ARWLEN_MIN = DWAXIDMAC_ARWLEN_1,
  209. DWAXIDMAC_ARWLEN_MAX = DWAXIDMAC_ARWLEN_256
  210. };
  211. #define CH_CTL_H_LLI_LAST BIT(30)
  212. #define CH_CTL_H_LLI_VALID BIT(31)
  213. /* CH_CTL_L */
  214. #define CH_CTL_L_LAST_WRITE_EN BIT(30)
  215. #define CH_CTL_L_DST_MSIZE_POS 18
  216. #define CH_CTL_L_SRC_MSIZE_POS 14
  217. enum {
  218. DWAXIDMAC_BURST_TRANS_LEN_1 = 0,
  219. DWAXIDMAC_BURST_TRANS_LEN_4,
  220. DWAXIDMAC_BURST_TRANS_LEN_8,
  221. DWAXIDMAC_BURST_TRANS_LEN_16,
  222. DWAXIDMAC_BURST_TRANS_LEN_32,
  223. DWAXIDMAC_BURST_TRANS_LEN_64,
  224. DWAXIDMAC_BURST_TRANS_LEN_128,
  225. DWAXIDMAC_BURST_TRANS_LEN_256,
  226. DWAXIDMAC_BURST_TRANS_LEN_512,
  227. DWAXIDMAC_BURST_TRANS_LEN_1024
  228. };
  229. #define CH_CTL_L_DST_WIDTH_POS 11
  230. #define CH_CTL_L_SRC_WIDTH_POS 8
  231. #define CH_CTL_L_DST_INC_POS 6
  232. #define CH_CTL_L_SRC_INC_POS 4
  233. enum {
  234. DWAXIDMAC_CH_CTL_L_INC = 0,
  235. DWAXIDMAC_CH_CTL_L_NOINC
  236. };
  237. #define CH_CTL_L_DST_MAST BIT(2)
  238. #define CH_CTL_L_SRC_MAST BIT(0)
  239. /* CH_CFG_H */
  240. #define CH_CFG_H_PRIORITY_POS 17
  241. #define CH_CFG_H_DST_PER_POS 12
  242. #define CH_CFG_H_SRC_PER_POS 7
  243. #define CH_CFG_H_HS_SEL_DST_POS 4
  244. #define CH_CFG_H_HS_SEL_SRC_POS 3
  245. enum {
  246. DWAXIDMAC_HS_SEL_HW = 0,
  247. DWAXIDMAC_HS_SEL_SW
  248. };
  249. #define CH_CFG_H_TT_FC_POS 0
  250. enum {
  251. DWAXIDMAC_TT_FC_MEM_TO_MEM_DMAC = 0,
  252. DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC,
  253. DWAXIDMAC_TT_FC_PER_TO_MEM_DMAC,
  254. DWAXIDMAC_TT_FC_PER_TO_PER_DMAC,
  255. DWAXIDMAC_TT_FC_PER_TO_MEM_SRC,
  256. DWAXIDMAC_TT_FC_PER_TO_PER_SRC,
  257. DWAXIDMAC_TT_FC_MEM_TO_PER_DST,
  258. DWAXIDMAC_TT_FC_PER_TO_PER_DST
  259. };
  260. /* CH_CFG_L */
  261. #define CH_CFG_L_DST_MULTBLK_TYPE_POS 2
  262. #define CH_CFG_L_SRC_MULTBLK_TYPE_POS 0
  263. enum {
  264. DWAXIDMAC_MBLK_TYPE_CONTIGUOUS = 0,
  265. DWAXIDMAC_MBLK_TYPE_RELOAD,
  266. DWAXIDMAC_MBLK_TYPE_SHADOW_REG,
  267. DWAXIDMAC_MBLK_TYPE_LL
  268. };
  269. /* CH_CFG2 */
  270. #define CH_CFG2_L_SRC_PER_POS 4
  271. #define CH_CFG2_L_DST_PER_POS 11
  272. #define CH_CFG2_H_TT_FC_POS 0
  273. #define CH_CFG2_H_HS_SEL_SRC_POS 3
  274. #define CH_CFG2_H_HS_SEL_DST_POS 4
  275. #define CH_CFG2_H_PRIORITY_POS 20
  276. /**
  277. * DW AXI DMA channel interrupts
  278. *
  279. * @DWAXIDMAC_IRQ_NONE: Bitmask of no one interrupt
  280. * @DWAXIDMAC_IRQ_BLOCK_TRF: Block transfer complete
  281. * @DWAXIDMAC_IRQ_DMA_TRF: Dma transfer complete
  282. * @DWAXIDMAC_IRQ_SRC_TRAN: Source transaction complete
  283. * @DWAXIDMAC_IRQ_DST_TRAN: Destination transaction complete
  284. * @DWAXIDMAC_IRQ_SRC_DEC_ERR: Source decode error
  285. * @DWAXIDMAC_IRQ_DST_DEC_ERR: Destination decode error
  286. * @DWAXIDMAC_IRQ_SRC_SLV_ERR: Source slave error
  287. * @DWAXIDMAC_IRQ_DST_SLV_ERR: Destination slave error
  288. * @DWAXIDMAC_IRQ_LLI_RD_DEC_ERR: LLI read decode error
  289. * @DWAXIDMAC_IRQ_LLI_WR_DEC_ERR: LLI write decode error
  290. * @DWAXIDMAC_IRQ_LLI_RD_SLV_ERR: LLI read slave error
  291. * @DWAXIDMAC_IRQ_LLI_WR_SLV_ERR: LLI write slave error
  292. * @DWAXIDMAC_IRQ_INVALID_ERR: LLI invalid error or Shadow register error
  293. * @DWAXIDMAC_IRQ_MULTIBLKTYPE_ERR: Slave Interface Multiblock type error
  294. * @DWAXIDMAC_IRQ_DEC_ERR: Slave Interface decode error
  295. * @DWAXIDMAC_IRQ_WR2RO_ERR: Slave Interface write to read only error
  296. * @DWAXIDMAC_IRQ_RD2RWO_ERR: Slave Interface read to write only error
  297. * @DWAXIDMAC_IRQ_WRONCHEN_ERR: Slave Interface write to channel error
  298. * @DWAXIDMAC_IRQ_SHADOWREG_ERR: Slave Interface shadow reg error
  299. * @DWAXIDMAC_IRQ_WRONHOLD_ERR: Slave Interface hold error
  300. * @DWAXIDMAC_IRQ_LOCK_CLEARED: Lock Cleared Status
  301. * @DWAXIDMAC_IRQ_SRC_SUSPENDED: Source Suspended Status
  302. * @DWAXIDMAC_IRQ_SUSPENDED: Channel Suspended Status
  303. * @DWAXIDMAC_IRQ_DISABLED: Channel Disabled Status
  304. * @DWAXIDMAC_IRQ_ABORTED: Channel Aborted Status
  305. * @DWAXIDMAC_IRQ_ALL_ERR: Bitmask of all error interrupts
  306. * @DWAXIDMAC_IRQ_ALL: Bitmask of all interrupts
  307. */
  308. enum {
  309. DWAXIDMAC_IRQ_NONE = 0,
  310. DWAXIDMAC_IRQ_BLOCK_TRF = BIT(0),
  311. DWAXIDMAC_IRQ_DMA_TRF = BIT(1),
  312. DWAXIDMAC_IRQ_SRC_TRAN = BIT(3),
  313. DWAXIDMAC_IRQ_DST_TRAN = BIT(4),
  314. DWAXIDMAC_IRQ_SRC_DEC_ERR = BIT(5),
  315. DWAXIDMAC_IRQ_DST_DEC_ERR = BIT(6),
  316. DWAXIDMAC_IRQ_SRC_SLV_ERR = BIT(7),
  317. DWAXIDMAC_IRQ_DST_SLV_ERR = BIT(8),
  318. DWAXIDMAC_IRQ_LLI_RD_DEC_ERR = BIT(9),
  319. DWAXIDMAC_IRQ_LLI_WR_DEC_ERR = BIT(10),
  320. DWAXIDMAC_IRQ_LLI_RD_SLV_ERR = BIT(11),
  321. DWAXIDMAC_IRQ_LLI_WR_SLV_ERR = BIT(12),
  322. DWAXIDMAC_IRQ_INVALID_ERR = BIT(13),
  323. DWAXIDMAC_IRQ_MULTIBLKTYPE_ERR = BIT(14),
  324. DWAXIDMAC_IRQ_DEC_ERR = BIT(16),
  325. DWAXIDMAC_IRQ_WR2RO_ERR = BIT(17),
  326. DWAXIDMAC_IRQ_RD2RWO_ERR = BIT(18),
  327. DWAXIDMAC_IRQ_WRONCHEN_ERR = BIT(19),
  328. DWAXIDMAC_IRQ_SHADOWREG_ERR = BIT(20),
  329. DWAXIDMAC_IRQ_WRONHOLD_ERR = BIT(21),
  330. DWAXIDMAC_IRQ_LOCK_CLEARED = BIT(27),
  331. DWAXIDMAC_IRQ_SRC_SUSPENDED = BIT(28),
  332. DWAXIDMAC_IRQ_SUSPENDED = BIT(29),
  333. DWAXIDMAC_IRQ_DISABLED = BIT(30),
  334. DWAXIDMAC_IRQ_ABORTED = BIT(31),
  335. DWAXIDMAC_IRQ_ALL_ERR = (GENMASK(21, 16) | GENMASK(14, 5)),
  336. DWAXIDMAC_IRQ_ALL = GENMASK(31, 0)
  337. };
  338. enum {
  339. DWAXIDMAC_TRANS_WIDTH_8 = 0,
  340. DWAXIDMAC_TRANS_WIDTH_16,
  341. DWAXIDMAC_TRANS_WIDTH_32,
  342. DWAXIDMAC_TRANS_WIDTH_64,
  343. DWAXIDMAC_TRANS_WIDTH_128,
  344. DWAXIDMAC_TRANS_WIDTH_256,
  345. DWAXIDMAC_TRANS_WIDTH_512,
  346. DWAXIDMAC_TRANS_WIDTH_MAX = DWAXIDMAC_TRANS_WIDTH_512
  347. };
  348. #endif /* _AXI_DMA_PLATFORM_H */