clk-pistachio.c 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Pistachio SoC clock controllers
  4. *
  5. * Copyright (C) 2014 Google, Inc.
  6. */
  7. #include <linux/clk-provider.h>
  8. #include <linux/init.h>
  9. #include <linux/io.h>
  10. #include <linux/kernel.h>
  11. #include <linux/of.h>
  12. #include <dt-bindings/clock/pistachio-clk.h>
  13. #include "clk.h"
  14. static struct pistachio_gate pistachio_gates[] __initdata = {
  15. GATE(CLK_MIPS, "mips", "mips_div", 0x104, 0),
  16. GATE(CLK_AUDIO_IN, "audio_in", "audio_clk_in_gate", 0x104, 1),
  17. GATE(CLK_AUDIO, "audio", "audio_div", 0x104, 2),
  18. GATE(CLK_I2S, "i2s", "i2s_div", 0x104, 3),
  19. GATE(CLK_SPDIF, "spdif", "spdif_div", 0x104, 4),
  20. GATE(CLK_AUDIO_DAC, "audio_dac", "audio_dac_div", 0x104, 5),
  21. GATE(CLK_RPU_V, "rpu_v", "rpu_v_div", 0x104, 6),
  22. GATE(CLK_RPU_L, "rpu_l", "rpu_l_div", 0x104, 7),
  23. GATE(CLK_RPU_SLEEP, "rpu_sleep", "rpu_sleep_div", 0x104, 8),
  24. GATE(CLK_WIFI_PLL_GATE, "wifi_pll_gate", "wifi_pll_mux", 0x104, 9),
  25. GATE(CLK_RPU_CORE, "rpu_core", "rpu_core_div", 0x104, 10),
  26. GATE(CLK_WIFI_ADC, "wifi_adc", "wifi_div8_mux", 0x104, 11),
  27. GATE(CLK_WIFI_DAC, "wifi_dac", "wifi_div4_mux", 0x104, 12),
  28. GATE(CLK_USB_PHY, "usb_phy", "usb_phy_div", 0x104, 13),
  29. GATE(CLK_ENET_IN, "enet_in", "enet_clk_in_gate", 0x104, 14),
  30. GATE(CLK_ENET, "enet", "enet_div", 0x104, 15),
  31. GATE(CLK_UART0, "uart0", "uart0_div", 0x104, 16),
  32. GATE(CLK_UART1, "uart1", "uart1_div", 0x104, 17),
  33. GATE(CLK_PERIPH_SYS, "periph_sys", "sys_internal_div", 0x104, 18),
  34. GATE(CLK_SPI0, "spi0", "spi0_div", 0x104, 19),
  35. GATE(CLK_SPI1, "spi1", "spi1_div", 0x104, 20),
  36. GATE(CLK_EVENT_TIMER, "event_timer", "event_timer_div", 0x104, 21),
  37. GATE(CLK_AUX_ADC_INTERNAL, "aux_adc_internal", "sys_internal_div",
  38. 0x104, 22),
  39. GATE(CLK_AUX_ADC, "aux_adc", "aux_adc_div", 0x104, 23),
  40. GATE(CLK_SD_HOST, "sd_host", "sd_host_div", 0x104, 24),
  41. GATE(CLK_BT, "bt", "bt_div", 0x104, 25),
  42. GATE(CLK_BT_DIV4, "bt_div4", "bt_div4_div", 0x104, 26),
  43. GATE(CLK_BT_DIV8, "bt_div8", "bt_div8_div", 0x104, 27),
  44. GATE(CLK_BT_1MHZ, "bt_1mhz", "bt_1mhz_div", 0x104, 28),
  45. };
  46. static struct pistachio_fixed_factor pistachio_ffs[] __initdata = {
  47. FIXED_FACTOR(CLK_WIFI_DIV4, "wifi_div4", "wifi_pll", 4),
  48. FIXED_FACTOR(CLK_WIFI_DIV8, "wifi_div8", "wifi_pll", 8),
  49. };
  50. static struct pistachio_div pistachio_divs[] __initdata = {
  51. DIV(CLK_MIPS_INTERNAL_DIV, "mips_internal_div", "mips_pll_mux",
  52. 0x204, 2),
  53. DIV(CLK_MIPS_DIV, "mips_div", "mips_internal_div", 0x208, 8),
  54. DIV_F(CLK_AUDIO_DIV, "audio_div", "audio_mux",
  55. 0x20c, 8, CLK_DIVIDER_ROUND_CLOSEST),
  56. DIV_F(CLK_I2S_DIV, "i2s_div", "audio_pll_mux",
  57. 0x210, 8, CLK_DIVIDER_ROUND_CLOSEST),
  58. DIV_F(CLK_SPDIF_DIV, "spdif_div", "audio_pll_mux",
  59. 0x214, 8, CLK_DIVIDER_ROUND_CLOSEST),
  60. DIV_F(CLK_AUDIO_DAC_DIV, "audio_dac_div", "audio_pll_mux",
  61. 0x218, 8, CLK_DIVIDER_ROUND_CLOSEST),
  62. DIV(CLK_RPU_V_DIV, "rpu_v_div", "rpu_v_pll_mux", 0x21c, 2),
  63. DIV(CLK_RPU_L_DIV, "rpu_l_div", "rpu_l_mux", 0x220, 2),
  64. DIV(CLK_RPU_SLEEP_DIV, "rpu_sleep_div", "xtal", 0x224, 10),
  65. DIV(CLK_RPU_CORE_DIV, "rpu_core_div", "rpu_core_mux", 0x228, 3),
  66. DIV(CLK_USB_PHY_DIV, "usb_phy_div", "sys_internal_div", 0x22c, 6),
  67. DIV(CLK_ENET_DIV, "enet_div", "enet_mux", 0x230, 6),
  68. DIV_F(CLK_UART0_INTERNAL_DIV, "uart0_internal_div", "sys_pll_mux",
  69. 0x234, 3, CLK_DIVIDER_ROUND_CLOSEST),
  70. DIV_F(CLK_UART0_DIV, "uart0_div", "uart0_internal_div", 0x238, 10,
  71. CLK_DIVIDER_ROUND_CLOSEST),
  72. DIV_F(CLK_UART1_INTERNAL_DIV, "uart1_internal_div", "sys_pll_mux",
  73. 0x23c, 3, CLK_DIVIDER_ROUND_CLOSEST),
  74. DIV_F(CLK_UART1_DIV, "uart1_div", "uart1_internal_div", 0x240, 10,
  75. CLK_DIVIDER_ROUND_CLOSEST),
  76. DIV(CLK_SYS_INTERNAL_DIV, "sys_internal_div", "sys_pll_mux", 0x244, 3),
  77. DIV(CLK_SPI0_INTERNAL_DIV, "spi0_internal_div", "sys_pll_mux",
  78. 0x248, 3),
  79. DIV(CLK_SPI0_DIV, "spi0_div", "spi0_internal_div", 0x24c, 7),
  80. DIV(CLK_SPI1_INTERNAL_DIV, "spi1_internal_div", "sys_pll_mux",
  81. 0x250, 3),
  82. DIV(CLK_SPI1_DIV, "spi1_div", "spi1_internal_div", 0x254, 7),
  83. DIV(CLK_EVENT_TIMER_INTERNAL_DIV, "event_timer_internal_div",
  84. "event_timer_mux", 0x258, 3),
  85. DIV(CLK_EVENT_TIMER_DIV, "event_timer_div", "event_timer_internal_div",
  86. 0x25c, 12),
  87. DIV(CLK_AUX_ADC_INTERNAL_DIV, "aux_adc_internal_div",
  88. "aux_adc_internal", 0x260, 3),
  89. DIV(CLK_AUX_ADC_DIV, "aux_adc_div", "aux_adc_internal_div", 0x264, 10),
  90. DIV(CLK_SD_HOST_DIV, "sd_host_div", "sd_host_mux", 0x268, 6),
  91. DIV(CLK_BT_DIV, "bt_div", "bt_pll_mux", 0x26c, 6),
  92. DIV(CLK_BT_DIV4_DIV, "bt_div4_div", "bt_pll_mux", 0x270, 6),
  93. DIV(CLK_BT_DIV8_DIV, "bt_div8_div", "bt_pll_mux", 0x274, 6),
  94. DIV(CLK_BT_1MHZ_INTERNAL_DIV, "bt_1mhz_internal_div", "bt_pll_mux",
  95. 0x278, 3),
  96. DIV(CLK_BT_1MHZ_DIV, "bt_1mhz_div", "bt_1mhz_internal_div", 0x27c, 10),
  97. };
  98. PNAME(mux_xtal_audio_refclk) = { "xtal", "audio_clk_in_gate" };
  99. PNAME(mux_xtal_mips) = { "xtal", "mips_pll" };
  100. PNAME(mux_xtal_audio) = { "xtal", "audio_pll", "audio_in" };
  101. PNAME(mux_audio_debug) = { "audio_pll_mux", "debug_mux" };
  102. PNAME(mux_xtal_rpu_v) = { "xtal", "rpu_v_pll" };
  103. PNAME(mux_xtal_rpu_l) = { "xtal", "rpu_l_pll" };
  104. PNAME(mux_rpu_l_mips) = { "rpu_l_pll_mux", "mips_pll_mux" };
  105. PNAME(mux_xtal_wifi) = { "xtal", "wifi_pll" };
  106. PNAME(mux_xtal_wifi_div4) = { "xtal", "wifi_div4" };
  107. PNAME(mux_xtal_wifi_div8) = { "xtal", "wifi_div8" };
  108. PNAME(mux_wifi_div4_rpu_l) = { "wifi_pll_gate", "wifi_div4_mux",
  109. "rpu_l_pll_mux" };
  110. PNAME(mux_xtal_sys) = { "xtal", "sys_pll" };
  111. PNAME(mux_sys_enet) = { "sys_internal_div", "enet_in" };
  112. PNAME(mux_audio_sys) = { "audio_pll_mux", "sys_internal_div" };
  113. PNAME(mux_sys_bt) = { "sys_internal_div", "bt_pll_mux" };
  114. PNAME(mux_xtal_bt) = { "xtal", "bt_pll" };
  115. static struct pistachio_mux pistachio_muxes[] __initdata = {
  116. MUX(CLK_AUDIO_REF_MUX, "audio_refclk_mux", mux_xtal_audio_refclk,
  117. 0x200, 0),
  118. MUX(CLK_MIPS_PLL_MUX, "mips_pll_mux", mux_xtal_mips, 0x200, 1),
  119. MUX(CLK_AUDIO_PLL_MUX, "audio_pll_mux", mux_xtal_audio, 0x200, 2),
  120. MUX(CLK_AUDIO_MUX, "audio_mux", mux_audio_debug, 0x200, 4),
  121. MUX(CLK_RPU_V_PLL_MUX, "rpu_v_pll_mux", mux_xtal_rpu_v, 0x200, 5),
  122. MUX(CLK_RPU_L_PLL_MUX, "rpu_l_pll_mux", mux_xtal_rpu_l, 0x200, 6),
  123. MUX(CLK_RPU_L_MUX, "rpu_l_mux", mux_rpu_l_mips, 0x200, 7),
  124. MUX(CLK_WIFI_PLL_MUX, "wifi_pll_mux", mux_xtal_wifi, 0x200, 8),
  125. MUX(CLK_WIFI_DIV4_MUX, "wifi_div4_mux", mux_xtal_wifi_div4, 0x200, 9),
  126. MUX(CLK_WIFI_DIV8_MUX, "wifi_div8_mux", mux_xtal_wifi_div8, 0x200, 10),
  127. MUX(CLK_RPU_CORE_MUX, "rpu_core_mux", mux_wifi_div4_rpu_l, 0x200, 11),
  128. MUX(CLK_SYS_PLL_MUX, "sys_pll_mux", mux_xtal_sys, 0x200, 13),
  129. MUX(CLK_ENET_MUX, "enet_mux", mux_sys_enet, 0x200, 14),
  130. MUX(CLK_EVENT_TIMER_MUX, "event_timer_mux", mux_audio_sys, 0x200, 15),
  131. MUX(CLK_SD_HOST_MUX, "sd_host_mux", mux_sys_bt, 0x200, 16),
  132. MUX(CLK_BT_PLL_MUX, "bt_pll_mux", mux_xtal_bt, 0x200, 17),
  133. };
  134. static struct pistachio_pll pistachio_plls[] __initdata = {
  135. PLL_FIXED(CLK_MIPS_PLL, "mips_pll", "xtal", PLL_GF40LP_LAINT, 0x0),
  136. PLL_FIXED(CLK_AUDIO_PLL, "audio_pll", "audio_refclk_mux",
  137. PLL_GF40LP_FRAC, 0xc),
  138. PLL_FIXED(CLK_RPU_V_PLL, "rpu_v_pll", "xtal", PLL_GF40LP_LAINT, 0x20),
  139. PLL_FIXED(CLK_RPU_L_PLL, "rpu_l_pll", "xtal", PLL_GF40LP_LAINT, 0x2c),
  140. PLL_FIXED(CLK_SYS_PLL, "sys_pll", "xtal", PLL_GF40LP_FRAC, 0x38),
  141. PLL_FIXED(CLK_WIFI_PLL, "wifi_pll", "xtal", PLL_GF40LP_FRAC, 0x4c),
  142. PLL_FIXED(CLK_BT_PLL, "bt_pll", "xtal", PLL_GF40LP_LAINT, 0x60),
  143. };
  144. PNAME(mux_debug) = { "mips_pll_mux", "rpu_v_pll_mux",
  145. "rpu_l_pll_mux", "sys_pll_mux",
  146. "wifi_pll_mux", "bt_pll_mux" };
  147. static const u32 mux_debug_idx[] = { 0x0, 0x1, 0x2, 0x4, 0x8, 0x10 };
  148. static unsigned int pistachio_critical_clks_core[] __initdata = {
  149. CLK_MIPS
  150. };
  151. static unsigned int pistachio_critical_clks_sys[] __initdata = {
  152. PERIPH_CLK_SYS,
  153. PERIPH_CLK_SYS_BUS,
  154. PERIPH_CLK_DDR,
  155. PERIPH_CLK_ROM,
  156. };
  157. static void __init pistachio_clk_init(struct device_node *np)
  158. {
  159. struct pistachio_clk_provider *p;
  160. struct clk *debug_clk;
  161. p = pistachio_clk_alloc_provider(np, CLK_NR_CLKS);
  162. if (!p)
  163. return;
  164. pistachio_clk_register_pll(p, pistachio_plls,
  165. ARRAY_SIZE(pistachio_plls));
  166. pistachio_clk_register_mux(p, pistachio_muxes,
  167. ARRAY_SIZE(pistachio_muxes));
  168. pistachio_clk_register_div(p, pistachio_divs,
  169. ARRAY_SIZE(pistachio_divs));
  170. pistachio_clk_register_fixed_factor(p, pistachio_ffs,
  171. ARRAY_SIZE(pistachio_ffs));
  172. pistachio_clk_register_gate(p, pistachio_gates,
  173. ARRAY_SIZE(pistachio_gates));
  174. debug_clk = clk_register_mux_table(NULL, "debug_mux", mux_debug,
  175. ARRAY_SIZE(mux_debug),
  176. CLK_SET_RATE_NO_REPARENT,
  177. p->base + 0x200, 18, 0x1f, 0,
  178. mux_debug_idx, NULL);
  179. p->clk_data.clks[CLK_DEBUG_MUX] = debug_clk;
  180. pistachio_clk_register_provider(p);
  181. pistachio_clk_force_enable(p, pistachio_critical_clks_core,
  182. ARRAY_SIZE(pistachio_critical_clks_core));
  183. }
  184. CLK_OF_DECLARE(pistachio_clk, "img,pistachio-clk", pistachio_clk_init);
  185. static struct pistachio_gate pistachio_periph_gates[] __initdata = {
  186. GATE(PERIPH_CLK_SYS, "sys", "periph_sys", 0x100, 0),
  187. GATE(PERIPH_CLK_SYS_BUS, "bus_sys", "periph_sys", 0x100, 1),
  188. GATE(PERIPH_CLK_DDR, "ddr", "periph_sys", 0x100, 2),
  189. GATE(PERIPH_CLK_ROM, "rom", "rom_div", 0x100, 3),
  190. GATE(PERIPH_CLK_COUNTER_FAST, "counter_fast", "counter_fast_div",
  191. 0x100, 4),
  192. GATE(PERIPH_CLK_COUNTER_SLOW, "counter_slow", "counter_slow_div",
  193. 0x100, 5),
  194. GATE(PERIPH_CLK_IR, "ir", "ir_div", 0x100, 6),
  195. GATE(PERIPH_CLK_WD, "wd", "wd_div", 0x100, 7),
  196. GATE(PERIPH_CLK_PDM, "pdm", "pdm_div", 0x100, 8),
  197. GATE(PERIPH_CLK_PWM, "pwm", "pwm_div", 0x100, 9),
  198. GATE(PERIPH_CLK_I2C0, "i2c0", "i2c0_div", 0x100, 10),
  199. GATE(PERIPH_CLK_I2C1, "i2c1", "i2c1_div", 0x100, 11),
  200. GATE(PERIPH_CLK_I2C2, "i2c2", "i2c2_div", 0x100, 12),
  201. GATE(PERIPH_CLK_I2C3, "i2c3", "i2c3_div", 0x100, 13),
  202. };
  203. static struct pistachio_div pistachio_periph_divs[] __initdata = {
  204. DIV(PERIPH_CLK_ROM_DIV, "rom_div", "periph_sys", 0x10c, 7),
  205. DIV(PERIPH_CLK_COUNTER_FAST_DIV, "counter_fast_div", "periph_sys",
  206. 0x110, 7),
  207. DIV(PERIPH_CLK_COUNTER_SLOW_PRE_DIV, "counter_slow_pre_div",
  208. "periph_sys", 0x114, 7),
  209. DIV(PERIPH_CLK_COUNTER_SLOW_DIV, "counter_slow_div",
  210. "counter_slow_pre_div", 0x118, 7),
  211. DIV_F(PERIPH_CLK_IR_PRE_DIV, "ir_pre_div", "periph_sys", 0x11c, 7,
  212. CLK_DIVIDER_ROUND_CLOSEST),
  213. DIV_F(PERIPH_CLK_IR_DIV, "ir_div", "ir_pre_div", 0x120, 7,
  214. CLK_DIVIDER_ROUND_CLOSEST),
  215. DIV_F(PERIPH_CLK_WD_PRE_DIV, "wd_pre_div", "periph_sys", 0x124, 7,
  216. CLK_DIVIDER_ROUND_CLOSEST),
  217. DIV_F(PERIPH_CLK_WD_DIV, "wd_div", "wd_pre_div", 0x128, 7,
  218. CLK_DIVIDER_ROUND_CLOSEST),
  219. DIV(PERIPH_CLK_PDM_PRE_DIV, "pdm_pre_div", "periph_sys", 0x12c, 7),
  220. DIV(PERIPH_CLK_PDM_DIV, "pdm_div", "pdm_pre_div", 0x130, 7),
  221. DIV(PERIPH_CLK_PWM_PRE_DIV, "pwm_pre_div", "periph_sys", 0x134, 7),
  222. DIV(PERIPH_CLK_PWM_DIV, "pwm_div", "pwm_pre_div", 0x138, 7),
  223. DIV(PERIPH_CLK_I2C0_PRE_DIV, "i2c0_pre_div", "periph_sys", 0x13c, 7),
  224. DIV(PERIPH_CLK_I2C0_DIV, "i2c0_div", "i2c0_pre_div", 0x140, 7),
  225. DIV(PERIPH_CLK_I2C1_PRE_DIV, "i2c1_pre_div", "periph_sys", 0x144, 7),
  226. DIV(PERIPH_CLK_I2C1_DIV, "i2c1_div", "i2c1_pre_div", 0x148, 7),
  227. DIV(PERIPH_CLK_I2C2_PRE_DIV, "i2c2_pre_div", "periph_sys", 0x14c, 7),
  228. DIV(PERIPH_CLK_I2C2_DIV, "i2c2_div", "i2c2_pre_div", 0x150, 7),
  229. DIV(PERIPH_CLK_I2C3_PRE_DIV, "i2c3_pre_div", "periph_sys", 0x154, 7),
  230. DIV(PERIPH_CLK_I2C3_DIV, "i2c3_div", "i2c3_pre_div", 0x158, 7),
  231. };
  232. static void __init pistachio_clk_periph_init(struct device_node *np)
  233. {
  234. struct pistachio_clk_provider *p;
  235. p = pistachio_clk_alloc_provider(np, PERIPH_CLK_NR_CLKS);
  236. if (!p)
  237. return;
  238. pistachio_clk_register_div(p, pistachio_periph_divs,
  239. ARRAY_SIZE(pistachio_periph_divs));
  240. pistachio_clk_register_gate(p, pistachio_periph_gates,
  241. ARRAY_SIZE(pistachio_periph_gates));
  242. pistachio_clk_register_provider(p);
  243. pistachio_clk_force_enable(p, pistachio_critical_clks_sys,
  244. ARRAY_SIZE(pistachio_critical_clks_sys));
  245. }
  246. CLK_OF_DECLARE(pistachio_clk_periph, "img,pistachio-clk-periph",
  247. pistachio_clk_periph_init);
  248. static struct pistachio_gate pistachio_sys_gates[] __initdata = {
  249. GATE(SYS_CLK_I2C0, "i2c0_sys", "sys", 0x8, 0),
  250. GATE(SYS_CLK_I2C1, "i2c1_sys", "sys", 0x8, 1),
  251. GATE(SYS_CLK_I2C2, "i2c2_sys", "sys", 0x8, 2),
  252. GATE(SYS_CLK_I2C3, "i2c3_sys", "sys", 0x8, 3),
  253. GATE(SYS_CLK_I2S_IN, "i2s_in_sys", "sys", 0x8, 4),
  254. GATE(SYS_CLK_PAUD_OUT, "paud_out_sys", "sys", 0x8, 5),
  255. GATE(SYS_CLK_SPDIF_OUT, "spdif_out_sys", "sys", 0x8, 6),
  256. GATE(SYS_CLK_SPI0_MASTER, "spi0_master_sys", "sys", 0x8, 7),
  257. GATE(SYS_CLK_SPI0_SLAVE, "spi0_slave_sys", "sys", 0x8, 8),
  258. GATE(SYS_CLK_PWM, "pwm_sys", "sys", 0x8, 9),
  259. GATE(SYS_CLK_UART0, "uart0_sys", "sys", 0x8, 10),
  260. GATE(SYS_CLK_UART1, "uart1_sys", "sys", 0x8, 11),
  261. GATE(SYS_CLK_SPI1, "spi1_sys", "sys", 0x8, 12),
  262. GATE(SYS_CLK_MDC, "mdc_sys", "sys", 0x8, 13),
  263. GATE(SYS_CLK_SD_HOST, "sd_host_sys", "sys", 0x8, 14),
  264. GATE(SYS_CLK_ENET, "enet_sys", "sys", 0x8, 15),
  265. GATE(SYS_CLK_IR, "ir_sys", "sys", 0x8, 16),
  266. GATE(SYS_CLK_WD, "wd_sys", "sys", 0x8, 17),
  267. GATE(SYS_CLK_TIMER, "timer_sys", "sys", 0x8, 18),
  268. GATE(SYS_CLK_I2S_OUT, "i2s_out_sys", "sys", 0x8, 24),
  269. GATE(SYS_CLK_SPDIF_IN, "spdif_in_sys", "sys", 0x8, 25),
  270. GATE(SYS_CLK_EVENT_TIMER, "event_timer_sys", "sys", 0x8, 26),
  271. GATE(SYS_CLK_HASH, "hash_sys", "sys", 0x8, 27),
  272. };
  273. static void __init pistachio_cr_periph_init(struct device_node *np)
  274. {
  275. struct pistachio_clk_provider *p;
  276. p = pistachio_clk_alloc_provider(np, SYS_CLK_NR_CLKS);
  277. if (!p)
  278. return;
  279. pistachio_clk_register_gate(p, pistachio_sys_gates,
  280. ARRAY_SIZE(pistachio_sys_gates));
  281. pistachio_clk_register_provider(p);
  282. }
  283. CLK_OF_DECLARE(pistachio_cr_periph, "img,pistachio-cr-periph",
  284. pistachio_cr_periph_init);
  285. static struct pistachio_gate pistachio_ext_gates[] __initdata = {
  286. GATE(EXT_CLK_ENET_IN, "enet_clk_in_gate", "enet_clk_in", 0x58, 5),
  287. GATE(EXT_CLK_AUDIO_IN, "audio_clk_in_gate", "audio_clk_in", 0x58, 8)
  288. };
  289. static void __init pistachio_cr_top_init(struct device_node *np)
  290. {
  291. struct pistachio_clk_provider *p;
  292. p = pistachio_clk_alloc_provider(np, EXT_CLK_NR_CLKS);
  293. if (!p)
  294. return;
  295. pistachio_clk_register_gate(p, pistachio_ext_gates,
  296. ARRAY_SIZE(pistachio_ext_gates));
  297. pistachio_clk_register_provider(p);
  298. }
  299. CLK_OF_DECLARE(pistachio_cr_top, "img,pistachio-cr-top",
  300. pistachio_cr_top_init);