clk-mpfs.c 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * PolarFire SoC MSS/core complex clock control
  4. *
  5. * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved.
  6. */
  7. #include <linux/auxiliary_bus.h>
  8. #include <linux/clk-provider.h>
  9. #include <linux/io.h>
  10. #include <linux/module.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/slab.h>
  13. #include <dt-bindings/clock/microchip,mpfs-clock.h>
  14. #include <soc/microchip/mpfs.h>
  15. /* address offset of control registers */
  16. #define REG_MSSPLL_REF_CR 0x08u
  17. #define REG_MSSPLL_POSTDIV_CR 0x10u
  18. #define REG_MSSPLL_SSCG_2_CR 0x2Cu
  19. #define REG_CLOCK_CONFIG_CR 0x08u
  20. #define REG_RTC_CLOCK_CR 0x0Cu
  21. #define REG_SUBBLK_CLOCK_CR 0x84u
  22. #define REG_SUBBLK_RESET_CR 0x88u
  23. #define MSSPLL_FBDIV_SHIFT 0x00u
  24. #define MSSPLL_FBDIV_WIDTH 0x0Cu
  25. #define MSSPLL_REFDIV_SHIFT 0x08u
  26. #define MSSPLL_REFDIV_WIDTH 0x06u
  27. #define MSSPLL_POSTDIV_SHIFT 0x08u
  28. #define MSSPLL_POSTDIV_WIDTH 0x07u
  29. #define MSSPLL_FIXED_DIV 4u
  30. struct mpfs_clock_data {
  31. struct device *dev;
  32. void __iomem *base;
  33. void __iomem *msspll_base;
  34. struct clk_hw_onecell_data hw_data;
  35. };
  36. struct mpfs_msspll_hw_clock {
  37. void __iomem *base;
  38. unsigned int id;
  39. u32 reg_offset;
  40. u32 shift;
  41. u32 width;
  42. u32 flags;
  43. struct clk_hw hw;
  44. struct clk_init_data init;
  45. };
  46. #define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_clock, hw)
  47. struct mpfs_cfg_hw_clock {
  48. struct clk_divider cfg;
  49. struct clk_init_data init;
  50. unsigned int id;
  51. u32 reg_offset;
  52. };
  53. struct mpfs_periph_hw_clock {
  54. struct clk_gate periph;
  55. unsigned int id;
  56. };
  57. /*
  58. * mpfs_clk_lock prevents anything else from writing to the
  59. * mpfs clk block while a software locked register is being written.
  60. */
  61. static DEFINE_SPINLOCK(mpfs_clk_lock);
  62. static const struct clk_parent_data mpfs_ext_ref[] = {
  63. { .index = 0 },
  64. };
  65. static const struct clk_div_table mpfs_div_cpu_axi_table[] = {
  66. { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
  67. { 0, 0 }
  68. };
  69. static const struct clk_div_table mpfs_div_ahb_table[] = {
  70. { 1, 2 }, { 2, 4}, { 3, 8 },
  71. { 0, 0 }
  72. };
  73. /*
  74. * The only two supported reference clock frequencies for the PolarFire SoC are
  75. * 100 and 125 MHz, as the rtc reference is required to be 1 MHz.
  76. * It therefore only needs to have divider table entries corresponding to
  77. * divide by 100 and 125.
  78. */
  79. static const struct clk_div_table mpfs_div_rtcref_table[] = {
  80. { 100, 100 }, { 125, 125 },
  81. { 0, 0 }
  82. };
  83. static unsigned long mpfs_clk_msspll_recalc_rate(struct clk_hw *hw, unsigned long prate)
  84. {
  85. struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw);
  86. void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset;
  87. void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR;
  88. void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR;
  89. u32 mult, ref_div, postdiv;
  90. mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT;
  91. mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH);
  92. ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT;
  93. ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH);
  94. postdiv = readl_relaxed(postdiv_addr) >> MSSPLL_POSTDIV_SHIFT;
  95. postdiv &= clk_div_mask(MSSPLL_POSTDIV_WIDTH);
  96. return prate * mult / (ref_div * MSSPLL_FIXED_DIV * postdiv);
  97. }
  98. static long mpfs_clk_msspll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate)
  99. {
  100. struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw);
  101. void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset;
  102. void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR;
  103. u32 mult, ref_div;
  104. unsigned long rate_before_ctrl;
  105. mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT;
  106. mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH);
  107. ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT;
  108. ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH);
  109. rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult;
  110. return divider_round_rate(hw, rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH,
  111. msspll_hw->flags);
  112. }
  113. static int mpfs_clk_msspll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate)
  114. {
  115. struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw);
  116. void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset;
  117. void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR;
  118. void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR;
  119. u32 mult, ref_div, postdiv;
  120. int divider_setting;
  121. unsigned long rate_before_ctrl, flags;
  122. mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT;
  123. mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH);
  124. ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT;
  125. ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH);
  126. rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult;
  127. divider_setting = divider_get_val(rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH,
  128. msspll_hw->flags);
  129. if (divider_setting < 0)
  130. return divider_setting;
  131. spin_lock_irqsave(&mpfs_clk_lock, flags);
  132. postdiv = readl_relaxed(postdiv_addr);
  133. postdiv &= ~(clk_div_mask(MSSPLL_POSTDIV_WIDTH) << MSSPLL_POSTDIV_SHIFT);
  134. writel_relaxed(postdiv, postdiv_addr);
  135. spin_unlock_irqrestore(&mpfs_clk_lock, flags);
  136. return 0;
  137. }
  138. static const struct clk_ops mpfs_clk_msspll_ops = {
  139. .recalc_rate = mpfs_clk_msspll_recalc_rate,
  140. .round_rate = mpfs_clk_msspll_round_rate,
  141. .set_rate = mpfs_clk_msspll_set_rate,
  142. };
  143. #define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \
  144. .id = _id, \
  145. .shift = _shift, \
  146. .width = _width, \
  147. .reg_offset = _offset, \
  148. .flags = _flags, \
  149. .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parent, &mpfs_clk_msspll_ops, 0), \
  150. }
  151. static struct mpfs_msspll_hw_clock mpfs_msspll_clks[] = {
  152. CLK_PLL(CLK_MSSPLL, "clk_msspll", mpfs_ext_ref, MSSPLL_FBDIV_SHIFT,
  153. MSSPLL_FBDIV_WIDTH, 0, REG_MSSPLL_SSCG_2_CR),
  154. };
  155. static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_clock *msspll_hws,
  156. unsigned int num_clks, struct mpfs_clock_data *data)
  157. {
  158. unsigned int i;
  159. int ret;
  160. for (i = 0; i < num_clks; i++) {
  161. struct mpfs_msspll_hw_clock *msspll_hw = &msspll_hws[i];
  162. msspll_hw->base = data->msspll_base;
  163. ret = devm_clk_hw_register(dev, &msspll_hw->hw);
  164. if (ret)
  165. return dev_err_probe(dev, ret, "failed to register msspll id: %d\n",
  166. CLK_MSSPLL);
  167. data->hw_data.hws[msspll_hw->id] = &msspll_hw->hw;
  168. }
  169. return 0;
  170. }
  171. /*
  172. * "CFG" clocks
  173. */
  174. #define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \
  175. .id = _id, \
  176. .cfg.shift = _shift, \
  177. .cfg.width = _width, \
  178. .cfg.table = _table, \
  179. .reg_offset = _offset, \
  180. .cfg.flags = _flags, \
  181. .cfg.hw.init = CLK_HW_INIT(_name, _parent, &clk_divider_ops, 0), \
  182. .cfg.lock = &mpfs_clk_lock, \
  183. }
  184. #define CLK_CPU_OFFSET 0u
  185. #define CLK_AXI_OFFSET 1u
  186. #define CLK_AHB_OFFSET 2u
  187. #define CLK_RTCREF_OFFSET 3u
  188. static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = {
  189. CLK_CFG(CLK_CPU, "clk_cpu", "clk_msspll", 0, 2, mpfs_div_cpu_axi_table, 0,
  190. REG_CLOCK_CONFIG_CR),
  191. CLK_CFG(CLK_AXI, "clk_axi", "clk_msspll", 2, 2, mpfs_div_cpu_axi_table, 0,
  192. REG_CLOCK_CONFIG_CR),
  193. CLK_CFG(CLK_AHB, "clk_ahb", "clk_msspll", 4, 2, mpfs_div_ahb_table, 0,
  194. REG_CLOCK_CONFIG_CR),
  195. {
  196. .id = CLK_RTCREF,
  197. .cfg.shift = 0,
  198. .cfg.width = 12,
  199. .cfg.table = mpfs_div_rtcref_table,
  200. .reg_offset = REG_RTC_CLOCK_CR,
  201. .cfg.flags = CLK_DIVIDER_ONE_BASED,
  202. .cfg.hw.init =
  203. CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &clk_divider_ops, 0),
  204. }
  205. };
  206. static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hws,
  207. unsigned int num_clks, struct mpfs_clock_data *data)
  208. {
  209. unsigned int i, id;
  210. int ret;
  211. for (i = 0; i < num_clks; i++) {
  212. struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i];
  213. cfg_hw->cfg.reg = data->base + cfg_hw->reg_offset;
  214. ret = devm_clk_hw_register(dev, &cfg_hw->cfg.hw);
  215. if (ret)
  216. return dev_err_probe(dev, ret, "failed to register clock id: %d\n",
  217. cfg_hw->id);
  218. id = cfg_hw->id;
  219. data->hw_data.hws[id] = &cfg_hw->cfg.hw;
  220. }
  221. return 0;
  222. }
  223. /*
  224. * peripheral clocks - devices connected to axi or ahb buses.
  225. */
  226. #define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \
  227. .id = _id, \
  228. .periph.bit_idx = _shift, \
  229. .periph.hw.init = CLK_HW_INIT_HW(_name, _parent, &clk_gate_ops, \
  230. _flags), \
  231. .periph.lock = &mpfs_clk_lock, \
  232. }
  233. #define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].cfg.hw)
  234. /*
  235. * Critical clocks:
  236. * - CLK_ENVM: reserved by hart software services (hss) superloop monitor/m mode interrupt
  237. * trap handler
  238. * - CLK_MMUART0: reserved by the hss
  239. * - CLK_DDRC: provides clock to the ddr subsystem
  240. * - CLK_RTC: the onboard RTC's AHB bus clock must be kept running as the rtc will stop
  241. * if the AHB interface clock is disabled
  242. * - CLK_FICx: these provide the processor side clocks to the "FIC" (Fabric InterConnect)
  243. * clock domain crossers which provide the interface to the FPGA fabric. Disabling them
  244. * causes the FPGA fabric to go into reset.
  245. * - CLK_ATHENA: The athena clock is FIC4, which is reserved for the Athena TeraFire.
  246. */
  247. static struct mpfs_periph_hw_clock mpfs_periph_clks[] = {
  248. CLK_PERIPH(CLK_ENVM, "clk_periph_envm", PARENT_CLK(AHB), 0, CLK_IS_CRITICAL),
  249. CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", PARENT_CLK(AHB), 1, 0),
  250. CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", PARENT_CLK(AHB), 2, 0),
  251. CLK_PERIPH(CLK_MMC, "clk_periph_mmc", PARENT_CLK(AHB), 3, 0),
  252. CLK_PERIPH(CLK_TIMER, "clk_periph_timer", PARENT_CLK(RTCREF), 4, 0),
  253. CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", PARENT_CLK(AHB), 5, CLK_IS_CRITICAL),
  254. CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", PARENT_CLK(AHB), 6, 0),
  255. CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", PARENT_CLK(AHB), 7, 0),
  256. CLK_PERIPH(CLK_MMUART3, "clk_periph_mmuart3", PARENT_CLK(AHB), 8, 0),
  257. CLK_PERIPH(CLK_MMUART4, "clk_periph_mmuart4", PARENT_CLK(AHB), 9, 0),
  258. CLK_PERIPH(CLK_SPI0, "clk_periph_spi0", PARENT_CLK(AHB), 10, 0),
  259. CLK_PERIPH(CLK_SPI1, "clk_periph_spi1", PARENT_CLK(AHB), 11, 0),
  260. CLK_PERIPH(CLK_I2C0, "clk_periph_i2c0", PARENT_CLK(AHB), 12, 0),
  261. CLK_PERIPH(CLK_I2C1, "clk_periph_i2c1", PARENT_CLK(AHB), 13, 0),
  262. CLK_PERIPH(CLK_CAN0, "clk_periph_can0", PARENT_CLK(AHB), 14, 0),
  263. CLK_PERIPH(CLK_CAN1, "clk_periph_can1", PARENT_CLK(AHB), 15, 0),
  264. CLK_PERIPH(CLK_USB, "clk_periph_usb", PARENT_CLK(AHB), 16, 0),
  265. CLK_PERIPH(CLK_RTC, "clk_periph_rtc", PARENT_CLK(AHB), 18, CLK_IS_CRITICAL),
  266. CLK_PERIPH(CLK_QSPI, "clk_periph_qspi", PARENT_CLK(AHB), 19, 0),
  267. CLK_PERIPH(CLK_GPIO0, "clk_periph_gpio0", PARENT_CLK(AHB), 20, 0),
  268. CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", PARENT_CLK(AHB), 21, 0),
  269. CLK_PERIPH(CLK_GPIO2, "clk_periph_gpio2", PARENT_CLK(AHB), 22, 0),
  270. CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", PARENT_CLK(AHB), 23, CLK_IS_CRITICAL),
  271. CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", PARENT_CLK(AXI), 24, CLK_IS_CRITICAL),
  272. CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", PARENT_CLK(AXI), 25, CLK_IS_CRITICAL),
  273. CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", PARENT_CLK(AXI), 26, CLK_IS_CRITICAL),
  274. CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", PARENT_CLK(AXI), 27, CLK_IS_CRITICAL),
  275. CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", PARENT_CLK(AXI), 28, CLK_IS_CRITICAL),
  276. CLK_PERIPH(CLK_CFM, "clk_periph_cfm", PARENT_CLK(AHB), 29, 0),
  277. };
  278. static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_clock *periph_hws,
  279. int num_clks, struct mpfs_clock_data *data)
  280. {
  281. unsigned int i, id;
  282. int ret;
  283. for (i = 0; i < num_clks; i++) {
  284. struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i];
  285. periph_hw->periph.reg = data->base + REG_SUBBLK_CLOCK_CR;
  286. ret = devm_clk_hw_register(dev, &periph_hw->periph.hw);
  287. if (ret)
  288. return dev_err_probe(dev, ret, "failed to register clock id: %d\n",
  289. periph_hw->id);
  290. id = periph_hws[i].id;
  291. data->hw_data.hws[id] = &periph_hw->periph.hw;
  292. }
  293. return 0;
  294. }
  295. /*
  296. * Peripheral clock resets
  297. */
  298. #if IS_ENABLED(CONFIG_RESET_CONTROLLER)
  299. u32 mpfs_reset_read(struct device *dev)
  300. {
  301. struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent);
  302. return readl_relaxed(clock_data->base + REG_SUBBLK_RESET_CR);
  303. }
  304. EXPORT_SYMBOL_NS_GPL(mpfs_reset_read, MCHP_CLK_MPFS);
  305. void mpfs_reset_write(struct device *dev, u32 val)
  306. {
  307. struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent);
  308. writel_relaxed(val, clock_data->base + REG_SUBBLK_RESET_CR);
  309. }
  310. EXPORT_SYMBOL_NS_GPL(mpfs_reset_write, MCHP_CLK_MPFS);
  311. static void mpfs_reset_unregister_adev(void *_adev)
  312. {
  313. struct auxiliary_device *adev = _adev;
  314. auxiliary_device_delete(adev);
  315. auxiliary_device_uninit(adev);
  316. }
  317. static void mpfs_reset_adev_release(struct device *dev)
  318. {
  319. struct auxiliary_device *adev = to_auxiliary_dev(dev);
  320. kfree(adev);
  321. }
  322. static struct auxiliary_device *mpfs_reset_adev_alloc(struct mpfs_clock_data *clk_data)
  323. {
  324. struct auxiliary_device *adev;
  325. int ret;
  326. adev = kzalloc(sizeof(*adev), GFP_KERNEL);
  327. if (!adev)
  328. return ERR_PTR(-ENOMEM);
  329. adev->name = "reset-mpfs";
  330. adev->dev.parent = clk_data->dev;
  331. adev->dev.release = mpfs_reset_adev_release;
  332. adev->id = 666u;
  333. ret = auxiliary_device_init(adev);
  334. if (ret) {
  335. kfree(adev);
  336. return ERR_PTR(ret);
  337. }
  338. return adev;
  339. }
  340. static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data)
  341. {
  342. struct auxiliary_device *adev;
  343. int ret;
  344. adev = mpfs_reset_adev_alloc(clk_data);
  345. if (IS_ERR(adev))
  346. return PTR_ERR(adev);
  347. ret = auxiliary_device_add(adev);
  348. if (ret) {
  349. auxiliary_device_uninit(adev);
  350. return ret;
  351. }
  352. return devm_add_action_or_reset(clk_data->dev, mpfs_reset_unregister_adev, adev);
  353. }
  354. #else /* !CONFIG_RESET_CONTROLLER */
  355. static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data)
  356. {
  357. return 0;
  358. }
  359. #endif /* !CONFIG_RESET_CONTROLLER */
  360. static int mpfs_clk_probe(struct platform_device *pdev)
  361. {
  362. struct device *dev = &pdev->dev;
  363. struct mpfs_clock_data *clk_data;
  364. unsigned int num_clks;
  365. int ret;
  366. /* CLK_RESERVED is not part of clock arrays, so add 1 */
  367. num_clks = ARRAY_SIZE(mpfs_msspll_clks) + ARRAY_SIZE(mpfs_cfg_clks)
  368. + ARRAY_SIZE(mpfs_periph_clks) + 1;
  369. clk_data = devm_kzalloc(dev, struct_size(clk_data, hw_data.hws, num_clks), GFP_KERNEL);
  370. if (!clk_data)
  371. return -ENOMEM;
  372. clk_data->base = devm_platform_ioremap_resource(pdev, 0);
  373. if (IS_ERR(clk_data->base))
  374. return PTR_ERR(clk_data->base);
  375. clk_data->msspll_base = devm_platform_ioremap_resource(pdev, 1);
  376. if (IS_ERR(clk_data->msspll_base))
  377. return PTR_ERR(clk_data->msspll_base);
  378. clk_data->hw_data.num = num_clks;
  379. clk_data->dev = dev;
  380. dev_set_drvdata(dev, clk_data);
  381. ret = mpfs_clk_register_mssplls(dev, mpfs_msspll_clks, ARRAY_SIZE(mpfs_msspll_clks),
  382. clk_data);
  383. if (ret)
  384. return ret;
  385. ret = mpfs_clk_register_cfgs(dev, mpfs_cfg_clks, ARRAY_SIZE(mpfs_cfg_clks), clk_data);
  386. if (ret)
  387. return ret;
  388. ret = mpfs_clk_register_periphs(dev, mpfs_periph_clks, ARRAY_SIZE(mpfs_periph_clks),
  389. clk_data);
  390. if (ret)
  391. return ret;
  392. ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data->hw_data);
  393. if (ret)
  394. return ret;
  395. return mpfs_reset_controller_register(clk_data);
  396. }
  397. static const struct of_device_id mpfs_clk_of_match_table[] = {
  398. { .compatible = "microchip,mpfs-clkcfg", },
  399. {}
  400. };
  401. MODULE_DEVICE_TABLE(of, mpfs_clk_of_match_table);
  402. static struct platform_driver mpfs_clk_driver = {
  403. .probe = mpfs_clk_probe,
  404. .driver = {
  405. .name = "microchip-mpfs-clkcfg",
  406. .of_match_table = mpfs_clk_of_match_table,
  407. },
  408. };
  409. static int __init clk_mpfs_init(void)
  410. {
  411. return platform_driver_register(&mpfs_clk_driver);
  412. }
  413. core_initcall(clk_mpfs_init);
  414. static void __exit clk_mpfs_exit(void)
  415. {
  416. platform_driver_unregister(&mpfs_clk_driver);
  417. }
  418. module_exit(clk_mpfs_exit);
  419. MODULE_DESCRIPTION("Microchip PolarFire SoC Clock Driver");
  420. MODULE_AUTHOR("Padmarao Begari <[email protected]>");
  421. MODULE_AUTHOR("Daire McNamara <[email protected]>");
  422. MODULE_AUTHOR("Conor Dooley <[email protected]>");
  423. MODULE_LICENSE("GPL");