crg-hi3516cv300.c 9.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Hi3516CV300 Clock and Reset Generator Driver
  4. *
  5. * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
  6. */
  7. #include <dt-bindings/clock/hi3516cv300-clock.h>
  8. #include <linux/clk-provider.h>
  9. #include <linux/module.h>
  10. #include <linux/of_device.h>
  11. #include <linux/platform_device.h>
  12. #include "clk.h"
  13. #include "crg.h"
  14. #include "reset.h"
  15. /* hi3516CV300 core CRG */
  16. #define HI3516CV300_INNER_CLK_OFFSET 64
  17. #define HI3516CV300_FIXED_3M 65
  18. #define HI3516CV300_FIXED_6M 66
  19. #define HI3516CV300_FIXED_24M 67
  20. #define HI3516CV300_FIXED_49P5 68
  21. #define HI3516CV300_FIXED_50M 69
  22. #define HI3516CV300_FIXED_83P3M 70
  23. #define HI3516CV300_FIXED_99M 71
  24. #define HI3516CV300_FIXED_100M 72
  25. #define HI3516CV300_FIXED_148P5M 73
  26. #define HI3516CV300_FIXED_198M 74
  27. #define HI3516CV300_FIXED_297M 75
  28. #define HI3516CV300_UART_MUX 76
  29. #define HI3516CV300_FMC_MUX 77
  30. #define HI3516CV300_MMC0_MUX 78
  31. #define HI3516CV300_MMC1_MUX 79
  32. #define HI3516CV300_MMC2_MUX 80
  33. #define HI3516CV300_MMC3_MUX 81
  34. #define HI3516CV300_PWM_MUX 82
  35. #define HI3516CV300_CRG_NR_CLKS 128
  36. static const struct hisi_fixed_rate_clock hi3516cv300_fixed_rate_clks[] = {
  37. { HI3516CV300_FIXED_3M, "3m", NULL, 0, 3000000, },
  38. { HI3516CV300_FIXED_6M, "6m", NULL, 0, 6000000, },
  39. { HI3516CV300_FIXED_24M, "24m", NULL, 0, 24000000, },
  40. { HI3516CV300_FIXED_49P5, "49.5m", NULL, 0, 49500000, },
  41. { HI3516CV300_FIXED_50M, "50m", NULL, 0, 50000000, },
  42. { HI3516CV300_FIXED_83P3M, "83.3m", NULL, 0, 83300000, },
  43. { HI3516CV300_FIXED_99M, "99m", NULL, 0, 99000000, },
  44. { HI3516CV300_FIXED_100M, "100m", NULL, 0, 100000000, },
  45. { HI3516CV300_FIXED_148P5M, "148.5m", NULL, 0, 148500000, },
  46. { HI3516CV300_FIXED_198M, "198m", NULL, 0, 198000000, },
  47. { HI3516CV300_FIXED_297M, "297m", NULL, 0, 297000000, },
  48. { HI3516CV300_APB_CLK, "apb", NULL, 0, 50000000, },
  49. };
  50. static const char *const uart_mux_p[] = {"24m", "6m"};
  51. static const char *const fmc_mux_p[] = {
  52. "24m", "83.3m", "148.5m", "198m", "297m"
  53. };
  54. static const char *const mmc_mux_p[] = {"49.5m"};
  55. static const char *const mmc2_mux_p[] = {"99m", "49.5m"};
  56. static const char *const pwm_mux_p[] = {"3m", "50m", "24m", "24m"};
  57. static u32 uart_mux_table[] = {0, 1};
  58. static u32 fmc_mux_table[] = {0, 1, 2, 3, 4};
  59. static u32 mmc_mux_table[] = {0};
  60. static u32 mmc2_mux_table[] = {0, 2};
  61. static u32 pwm_mux_table[] = {0, 1, 2, 3};
  62. static const struct hisi_mux_clock hi3516cv300_mux_clks[] = {
  63. { HI3516CV300_UART_MUX, "uart_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
  64. CLK_SET_RATE_PARENT, 0xe4, 19, 1, 0, uart_mux_table, },
  65. { HI3516CV300_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
  66. CLK_SET_RATE_PARENT, 0xc0, 2, 3, 0, fmc_mux_table, },
  67. { HI3516CV300_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
  68. CLK_SET_RATE_PARENT, 0xc4, 4, 2, 0, mmc_mux_table, },
  69. { HI3516CV300_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
  70. CLK_SET_RATE_PARENT, 0xc4, 12, 2, 0, mmc_mux_table, },
  71. { HI3516CV300_MMC2_MUX, "mmc2_mux", mmc2_mux_p, ARRAY_SIZE(mmc2_mux_p),
  72. CLK_SET_RATE_PARENT, 0xc4, 20, 2, 0, mmc2_mux_table, },
  73. { HI3516CV300_MMC3_MUX, "mmc3_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
  74. CLK_SET_RATE_PARENT, 0xc8, 4, 2, 0, mmc_mux_table, },
  75. { HI3516CV300_PWM_MUX, "pwm_mux", pwm_mux_p, ARRAY_SIZE(pwm_mux_p),
  76. CLK_SET_RATE_PARENT, 0x38, 2, 2, 0, pwm_mux_table, },
  77. };
  78. static const struct hisi_gate_clock hi3516cv300_gate_clks[] = {
  79. { HI3516CV300_UART0_CLK, "clk_uart0", "uart_mux", CLK_SET_RATE_PARENT,
  80. 0xe4, 15, 0, },
  81. { HI3516CV300_UART1_CLK, "clk_uart1", "uart_mux", CLK_SET_RATE_PARENT,
  82. 0xe4, 16, 0, },
  83. { HI3516CV300_UART2_CLK, "clk_uart2", "uart_mux", CLK_SET_RATE_PARENT,
  84. 0xe4, 17, 0, },
  85. { HI3516CV300_SPI0_CLK, "clk_spi0", "100m", CLK_SET_RATE_PARENT,
  86. 0xe4, 13, 0, },
  87. { HI3516CV300_SPI1_CLK, "clk_spi1", "100m", CLK_SET_RATE_PARENT,
  88. 0xe4, 14, 0, },
  89. { HI3516CV300_FMC_CLK, "clk_fmc", "fmc_mux", CLK_SET_RATE_PARENT,
  90. 0xc0, 1, 0, },
  91. { HI3516CV300_MMC0_CLK, "clk_mmc0", "mmc0_mux", CLK_SET_RATE_PARENT,
  92. 0xc4, 1, 0, },
  93. { HI3516CV300_MMC1_CLK, "clk_mmc1", "mmc1_mux", CLK_SET_RATE_PARENT,
  94. 0xc4, 9, 0, },
  95. { HI3516CV300_MMC2_CLK, "clk_mmc2", "mmc2_mux", CLK_SET_RATE_PARENT,
  96. 0xc4, 17, 0, },
  97. { HI3516CV300_MMC3_CLK, "clk_mmc3", "mmc3_mux", CLK_SET_RATE_PARENT,
  98. 0xc8, 1, 0, },
  99. { HI3516CV300_ETH_CLK, "clk_eth", NULL, 0, 0xec, 1, 0, },
  100. { HI3516CV300_DMAC_CLK, "clk_dmac", NULL, 0, 0xd8, 5, 0, },
  101. { HI3516CV300_PWM_CLK, "clk_pwm", "pwm_mux", CLK_SET_RATE_PARENT,
  102. 0x38, 1, 0, },
  103. { HI3516CV300_USB2_BUS_CLK, "clk_usb2_bus", NULL, 0, 0xb8, 0, 0, },
  104. { HI3516CV300_USB2_OHCI48M_CLK, "clk_usb2_ohci48m", NULL, 0,
  105. 0xb8, 1, 0, },
  106. { HI3516CV300_USB2_OHCI12M_CLK, "clk_usb2_ohci12m", NULL, 0,
  107. 0xb8, 2, 0, },
  108. { HI3516CV300_USB2_OTG_UTMI_CLK, "clk_usb2_otg_utmi", NULL, 0,
  109. 0xb8, 3, 0, },
  110. { HI3516CV300_USB2_HST_PHY_CLK, "clk_usb2_hst_phy", NULL, 0,
  111. 0xb8, 4, 0, },
  112. { HI3516CV300_USB2_UTMI0_CLK, "clk_usb2_utmi0", NULL, 0, 0xb8, 5, 0, },
  113. { HI3516CV300_USB2_PHY_CLK, "clk_usb2_phy", NULL, 0, 0xb8, 7, 0, },
  114. };
  115. static struct hisi_clock_data *hi3516cv300_clk_register(
  116. struct platform_device *pdev)
  117. {
  118. struct hisi_clock_data *clk_data;
  119. int ret;
  120. clk_data = hisi_clk_alloc(pdev, HI3516CV300_CRG_NR_CLKS);
  121. if (!clk_data)
  122. return ERR_PTR(-ENOMEM);
  123. ret = hisi_clk_register_fixed_rate(hi3516cv300_fixed_rate_clks,
  124. ARRAY_SIZE(hi3516cv300_fixed_rate_clks), clk_data);
  125. if (ret)
  126. return ERR_PTR(ret);
  127. ret = hisi_clk_register_mux(hi3516cv300_mux_clks,
  128. ARRAY_SIZE(hi3516cv300_mux_clks), clk_data);
  129. if (ret)
  130. goto unregister_fixed_rate;
  131. ret = hisi_clk_register_gate(hi3516cv300_gate_clks,
  132. ARRAY_SIZE(hi3516cv300_gate_clks), clk_data);
  133. if (ret)
  134. goto unregister_mux;
  135. ret = of_clk_add_provider(pdev->dev.of_node,
  136. of_clk_src_onecell_get, &clk_data->clk_data);
  137. if (ret)
  138. goto unregister_gate;
  139. return clk_data;
  140. unregister_gate:
  141. hisi_clk_unregister_gate(hi3516cv300_gate_clks,
  142. ARRAY_SIZE(hi3516cv300_gate_clks), clk_data);
  143. unregister_mux:
  144. hisi_clk_unregister_mux(hi3516cv300_mux_clks,
  145. ARRAY_SIZE(hi3516cv300_mux_clks), clk_data);
  146. unregister_fixed_rate:
  147. hisi_clk_unregister_fixed_rate(hi3516cv300_fixed_rate_clks,
  148. ARRAY_SIZE(hi3516cv300_fixed_rate_clks), clk_data);
  149. return ERR_PTR(ret);
  150. }
  151. static void hi3516cv300_clk_unregister(struct platform_device *pdev)
  152. {
  153. struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
  154. of_clk_del_provider(pdev->dev.of_node);
  155. hisi_clk_unregister_gate(hi3516cv300_gate_clks,
  156. ARRAY_SIZE(hi3516cv300_gate_clks), crg->clk_data);
  157. hisi_clk_unregister_mux(hi3516cv300_mux_clks,
  158. ARRAY_SIZE(hi3516cv300_mux_clks), crg->clk_data);
  159. hisi_clk_unregister_fixed_rate(hi3516cv300_fixed_rate_clks,
  160. ARRAY_SIZE(hi3516cv300_fixed_rate_clks), crg->clk_data);
  161. }
  162. static const struct hisi_crg_funcs hi3516cv300_crg_funcs = {
  163. .register_clks = hi3516cv300_clk_register,
  164. .unregister_clks = hi3516cv300_clk_unregister,
  165. };
  166. /* hi3516CV300 sysctrl CRG */
  167. #define HI3516CV300_SYSCTRL_NR_CLKS 16
  168. static const char *const wdt_mux_p[] __initconst = { "3m", "apb" };
  169. static u32 wdt_mux_table[] = {0, 1};
  170. static const struct hisi_mux_clock hi3516cv300_sysctrl_mux_clks[] = {
  171. { HI3516CV300_WDT_CLK, "wdt", wdt_mux_p, ARRAY_SIZE(wdt_mux_p),
  172. CLK_SET_RATE_PARENT, 0x0, 23, 1, 0, wdt_mux_table, },
  173. };
  174. static struct hisi_clock_data *hi3516cv300_sysctrl_clk_register(
  175. struct platform_device *pdev)
  176. {
  177. struct hisi_clock_data *clk_data;
  178. int ret;
  179. clk_data = hisi_clk_alloc(pdev, HI3516CV300_SYSCTRL_NR_CLKS);
  180. if (!clk_data)
  181. return ERR_PTR(-ENOMEM);
  182. ret = hisi_clk_register_mux(hi3516cv300_sysctrl_mux_clks,
  183. ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks), clk_data);
  184. if (ret)
  185. return ERR_PTR(ret);
  186. ret = of_clk_add_provider(pdev->dev.of_node,
  187. of_clk_src_onecell_get, &clk_data->clk_data);
  188. if (ret)
  189. goto unregister_mux;
  190. return clk_data;
  191. unregister_mux:
  192. hisi_clk_unregister_mux(hi3516cv300_sysctrl_mux_clks,
  193. ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks), clk_data);
  194. return ERR_PTR(ret);
  195. }
  196. static void hi3516cv300_sysctrl_clk_unregister(struct platform_device *pdev)
  197. {
  198. struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
  199. of_clk_del_provider(pdev->dev.of_node);
  200. hisi_clk_unregister_mux(hi3516cv300_sysctrl_mux_clks,
  201. ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks),
  202. crg->clk_data);
  203. }
  204. static const struct hisi_crg_funcs hi3516cv300_sysctrl_funcs = {
  205. .register_clks = hi3516cv300_sysctrl_clk_register,
  206. .unregister_clks = hi3516cv300_sysctrl_clk_unregister,
  207. };
  208. static const struct of_device_id hi3516cv300_crg_match_table[] = {
  209. {
  210. .compatible = "hisilicon,hi3516cv300-crg",
  211. .data = &hi3516cv300_crg_funcs
  212. },
  213. {
  214. .compatible = "hisilicon,hi3516cv300-sysctrl",
  215. .data = &hi3516cv300_sysctrl_funcs
  216. },
  217. { }
  218. };
  219. MODULE_DEVICE_TABLE(of, hi3516cv300_crg_match_table);
  220. static int hi3516cv300_crg_probe(struct platform_device *pdev)
  221. {
  222. struct hisi_crg_dev *crg;
  223. crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL);
  224. if (!crg)
  225. return -ENOMEM;
  226. crg->funcs = of_device_get_match_data(&pdev->dev);
  227. if (!crg->funcs)
  228. return -ENOENT;
  229. crg->rstc = hisi_reset_init(pdev);
  230. if (!crg->rstc)
  231. return -ENOMEM;
  232. crg->clk_data = crg->funcs->register_clks(pdev);
  233. if (IS_ERR(crg->clk_data)) {
  234. hisi_reset_exit(crg->rstc);
  235. return PTR_ERR(crg->clk_data);
  236. }
  237. platform_set_drvdata(pdev, crg);
  238. return 0;
  239. }
  240. static int hi3516cv300_crg_remove(struct platform_device *pdev)
  241. {
  242. struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
  243. hisi_reset_exit(crg->rstc);
  244. crg->funcs->unregister_clks(pdev);
  245. return 0;
  246. }
  247. static struct platform_driver hi3516cv300_crg_driver = {
  248. .probe = hi3516cv300_crg_probe,
  249. .remove = hi3516cv300_crg_remove,
  250. .driver = {
  251. .name = "hi3516cv300-crg",
  252. .of_match_table = hi3516cv300_crg_match_table,
  253. },
  254. };
  255. static int __init hi3516cv300_crg_init(void)
  256. {
  257. return platform_driver_register(&hi3516cv300_crg_driver);
  258. }
  259. core_initcall(hi3516cv300_crg_init);
  260. static void __exit hi3516cv300_crg_exit(void)
  261. {
  262. platform_driver_unregister(&hi3516cv300_crg_driver);
  263. }
  264. module_exit(hi3516cv300_crg_exit);
  265. MODULE_LICENSE("GPL v2");
  266. MODULE_DESCRIPTION("HiSilicon Hi3516CV300 CRG Driver");