clk-hi6220-stub.c 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Hi6220 stub clock driver
  4. *
  5. * Copyright (c) 2015 Hisilicon Limited.
  6. * Copyright (c) 2015 Linaro Limited.
  7. *
  8. * Author: Leo Yan <[email protected]>
  9. */
  10. #include <linux/clk-provider.h>
  11. #include <linux/err.h>
  12. #include <linux/kernel.h>
  13. #include <linux/mfd/syscon.h>
  14. #include <linux/mailbox_client.h>
  15. #include <linux/of.h>
  16. #include <linux/of_device.h>
  17. #include <linux/regmap.h>
  18. /* Stub clocks id */
  19. #define HI6220_STUB_ACPU0 0
  20. #define HI6220_STUB_ACPU1 1
  21. #define HI6220_STUB_GPU 2
  22. #define HI6220_STUB_DDR 5
  23. /* Mailbox message */
  24. #define HI6220_MBOX_MSG_LEN 8
  25. #define HI6220_MBOX_FREQ 0xA
  26. #define HI6220_MBOX_CMD_SET 0x3
  27. #define HI6220_MBOX_OBJ_AP 0x0
  28. /* CPU dynamic frequency scaling */
  29. #define ACPU_DFS_FREQ_MAX 0x1724
  30. #define ACPU_DFS_CUR_FREQ 0x17CC
  31. #define ACPU_DFS_FLAG 0x1B30
  32. #define ACPU_DFS_FREQ_REQ 0x1B34
  33. #define ACPU_DFS_FREQ_LMT 0x1B38
  34. #define ACPU_DFS_LOCK_FLAG 0xAEAEAEAE
  35. #define to_stub_clk(hw) container_of(hw, struct hi6220_stub_clk, hw)
  36. struct hi6220_stub_clk {
  37. u32 id;
  38. struct device *dev;
  39. struct clk_hw hw;
  40. struct regmap *dfs_map;
  41. struct mbox_client cl;
  42. struct mbox_chan *mbox;
  43. };
  44. struct hi6220_mbox_msg {
  45. unsigned char type;
  46. unsigned char cmd;
  47. unsigned char obj;
  48. unsigned char src;
  49. unsigned char para[4];
  50. };
  51. union hi6220_mbox_data {
  52. unsigned int data[HI6220_MBOX_MSG_LEN];
  53. struct hi6220_mbox_msg msg;
  54. };
  55. static unsigned int hi6220_acpu_get_freq(struct hi6220_stub_clk *stub_clk)
  56. {
  57. unsigned int freq;
  58. regmap_read(stub_clk->dfs_map, ACPU_DFS_CUR_FREQ, &freq);
  59. return freq;
  60. }
  61. static int hi6220_acpu_set_freq(struct hi6220_stub_clk *stub_clk,
  62. unsigned int freq)
  63. {
  64. union hi6220_mbox_data data;
  65. /* set the frequency in sram */
  66. regmap_write(stub_clk->dfs_map, ACPU_DFS_FREQ_REQ, freq);
  67. /* compound mailbox message */
  68. data.msg.type = HI6220_MBOX_FREQ;
  69. data.msg.cmd = HI6220_MBOX_CMD_SET;
  70. data.msg.obj = HI6220_MBOX_OBJ_AP;
  71. data.msg.src = HI6220_MBOX_OBJ_AP;
  72. mbox_send_message(stub_clk->mbox, &data);
  73. return 0;
  74. }
  75. static int hi6220_acpu_round_freq(struct hi6220_stub_clk *stub_clk,
  76. unsigned int freq)
  77. {
  78. unsigned int limit_flag, limit_freq = UINT_MAX;
  79. unsigned int max_freq;
  80. /* check the constrained frequency */
  81. regmap_read(stub_clk->dfs_map, ACPU_DFS_FLAG, &limit_flag);
  82. if (limit_flag == ACPU_DFS_LOCK_FLAG)
  83. regmap_read(stub_clk->dfs_map, ACPU_DFS_FREQ_LMT, &limit_freq);
  84. /* check the supported maximum frequency */
  85. regmap_read(stub_clk->dfs_map, ACPU_DFS_FREQ_MAX, &max_freq);
  86. /* calculate the real maximum frequency */
  87. max_freq = min(max_freq, limit_freq);
  88. if (WARN_ON(freq > max_freq))
  89. freq = max_freq;
  90. return freq;
  91. }
  92. static unsigned long hi6220_stub_clk_recalc_rate(struct clk_hw *hw,
  93. unsigned long parent_rate)
  94. {
  95. u32 rate = 0;
  96. struct hi6220_stub_clk *stub_clk = to_stub_clk(hw);
  97. switch (stub_clk->id) {
  98. case HI6220_STUB_ACPU0:
  99. rate = hi6220_acpu_get_freq(stub_clk);
  100. /* convert from kHz to Hz */
  101. rate *= 1000;
  102. break;
  103. default:
  104. dev_err(stub_clk->dev, "%s: un-supported clock id %d\n",
  105. __func__, stub_clk->id);
  106. break;
  107. }
  108. return rate;
  109. }
  110. static int hi6220_stub_clk_set_rate(struct clk_hw *hw, unsigned long rate,
  111. unsigned long parent_rate)
  112. {
  113. struct hi6220_stub_clk *stub_clk = to_stub_clk(hw);
  114. unsigned long new_rate = rate / 1000; /* kHz */
  115. int ret = 0;
  116. switch (stub_clk->id) {
  117. case HI6220_STUB_ACPU0:
  118. ret = hi6220_acpu_set_freq(stub_clk, new_rate);
  119. if (ret < 0)
  120. return ret;
  121. break;
  122. default:
  123. dev_err(stub_clk->dev, "%s: un-supported clock id %d\n",
  124. __func__, stub_clk->id);
  125. break;
  126. }
  127. pr_debug("%s: set rate=%ldkHz\n", __func__, new_rate);
  128. return ret;
  129. }
  130. static long hi6220_stub_clk_round_rate(struct clk_hw *hw, unsigned long rate,
  131. unsigned long *parent_rate)
  132. {
  133. struct hi6220_stub_clk *stub_clk = to_stub_clk(hw);
  134. unsigned long new_rate = rate / 1000; /* kHz */
  135. switch (stub_clk->id) {
  136. case HI6220_STUB_ACPU0:
  137. new_rate = hi6220_acpu_round_freq(stub_clk, new_rate);
  138. /* convert from kHz to Hz */
  139. new_rate *= 1000;
  140. break;
  141. default:
  142. dev_err(stub_clk->dev, "%s: un-supported clock id %d\n",
  143. __func__, stub_clk->id);
  144. break;
  145. }
  146. return new_rate;
  147. }
  148. static const struct clk_ops hi6220_stub_clk_ops = {
  149. .recalc_rate = hi6220_stub_clk_recalc_rate,
  150. .round_rate = hi6220_stub_clk_round_rate,
  151. .set_rate = hi6220_stub_clk_set_rate,
  152. };
  153. static int hi6220_stub_clk_probe(struct platform_device *pdev)
  154. {
  155. struct device *dev = &pdev->dev;
  156. struct clk_init_data init;
  157. struct hi6220_stub_clk *stub_clk;
  158. struct clk *clk;
  159. struct device_node *np = pdev->dev.of_node;
  160. int ret;
  161. stub_clk = devm_kzalloc(dev, sizeof(*stub_clk), GFP_KERNEL);
  162. if (!stub_clk)
  163. return -ENOMEM;
  164. stub_clk->dfs_map = syscon_regmap_lookup_by_phandle(np,
  165. "hisilicon,hi6220-clk-sram");
  166. if (IS_ERR(stub_clk->dfs_map)) {
  167. dev_err(dev, "failed to get sram regmap\n");
  168. return PTR_ERR(stub_clk->dfs_map);
  169. }
  170. stub_clk->hw.init = &init;
  171. stub_clk->dev = dev;
  172. stub_clk->id = HI6220_STUB_ACPU0;
  173. /* Use mailbox client with blocking mode */
  174. stub_clk->cl.dev = dev;
  175. stub_clk->cl.tx_done = NULL;
  176. stub_clk->cl.tx_block = true;
  177. stub_clk->cl.tx_tout = 500;
  178. stub_clk->cl.knows_txdone = false;
  179. /* Allocate mailbox channel */
  180. stub_clk->mbox = mbox_request_channel(&stub_clk->cl, 0);
  181. if (IS_ERR(stub_clk->mbox)) {
  182. dev_err(dev, "failed get mailbox channel\n");
  183. return PTR_ERR(stub_clk->mbox);
  184. }
  185. init.name = "acpu0";
  186. init.ops = &hi6220_stub_clk_ops;
  187. init.num_parents = 0;
  188. init.flags = 0;
  189. clk = devm_clk_register(dev, &stub_clk->hw);
  190. if (IS_ERR(clk))
  191. return PTR_ERR(clk);
  192. ret = of_clk_add_provider(np, of_clk_src_simple_get, clk);
  193. if (ret) {
  194. dev_err(dev, "failed to register OF clock provider\n");
  195. return ret;
  196. }
  197. /* initialize buffer to zero */
  198. regmap_write(stub_clk->dfs_map, ACPU_DFS_FLAG, 0x0);
  199. regmap_write(stub_clk->dfs_map, ACPU_DFS_FREQ_REQ, 0x0);
  200. regmap_write(stub_clk->dfs_map, ACPU_DFS_FREQ_LMT, 0x0);
  201. dev_dbg(dev, "Registered clock '%s'\n", init.name);
  202. return 0;
  203. }
  204. static const struct of_device_id hi6220_stub_clk_of_match[] = {
  205. { .compatible = "hisilicon,hi6220-stub-clk", },
  206. {}
  207. };
  208. static struct platform_driver hi6220_stub_clk_driver = {
  209. .driver = {
  210. .name = "hi6220-stub-clk",
  211. .of_match_table = hi6220_stub_clk_of_match,
  212. },
  213. .probe = hi6220_stub_clk_probe,
  214. };
  215. static int __init hi6220_stub_clk_init(void)
  216. {
  217. return platform_driver_register(&hi6220_stub_clk_driver);
  218. }
  219. subsys_initcall(hi6220_stub_clk_init);