clk-scmi.c 6.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * System Control and Power Interface (SCMI) Protocol based clock driver
  4. *
  5. * Copyright (C) 2018-2022 ARM Ltd.
  6. */
  7. #include <linux/clk-provider.h>
  8. #include <linux/device.h>
  9. #include <linux/err.h>
  10. #include <linux/of.h>
  11. #include <linux/module.h>
  12. #include <linux/scmi_protocol.h>
  13. #include <asm/div64.h>
  14. static const struct scmi_clk_proto_ops *scmi_proto_clk_ops;
  15. struct scmi_clk {
  16. u32 id;
  17. struct clk_hw hw;
  18. const struct scmi_clock_info *info;
  19. const struct scmi_protocol_handle *ph;
  20. };
  21. #define to_scmi_clk(clk) container_of(clk, struct scmi_clk, hw)
  22. static unsigned long scmi_clk_recalc_rate(struct clk_hw *hw,
  23. unsigned long parent_rate)
  24. {
  25. int ret;
  26. u64 rate;
  27. struct scmi_clk *clk = to_scmi_clk(hw);
  28. ret = scmi_proto_clk_ops->rate_get(clk->ph, clk->id, &rate);
  29. if (ret)
  30. return 0;
  31. return rate;
  32. }
  33. static long scmi_clk_round_rate(struct clk_hw *hw, unsigned long rate,
  34. unsigned long *parent_rate)
  35. {
  36. u64 fmin, fmax, ftmp;
  37. struct scmi_clk *clk = to_scmi_clk(hw);
  38. /*
  39. * We can't figure out what rate it will be, so just return the
  40. * rate back to the caller. scmi_clk_recalc_rate() will be called
  41. * after the rate is set and we'll know what rate the clock is
  42. * running at then.
  43. */
  44. if (clk->info->rate_discrete)
  45. return rate;
  46. fmin = clk->info->range.min_rate;
  47. fmax = clk->info->range.max_rate;
  48. if (rate <= fmin)
  49. return fmin;
  50. else if (rate >= fmax)
  51. return fmax;
  52. ftmp = rate - fmin;
  53. ftmp += clk->info->range.step_size - 1; /* to round up */
  54. do_div(ftmp, clk->info->range.step_size);
  55. return ftmp * clk->info->range.step_size + fmin;
  56. }
  57. static int scmi_clk_set_rate(struct clk_hw *hw, unsigned long rate,
  58. unsigned long parent_rate)
  59. {
  60. struct scmi_clk *clk = to_scmi_clk(hw);
  61. return scmi_proto_clk_ops->rate_set(clk->ph, clk->id, rate);
  62. }
  63. static int scmi_clk_enable(struct clk_hw *hw)
  64. {
  65. struct scmi_clk *clk = to_scmi_clk(hw);
  66. return scmi_proto_clk_ops->enable(clk->ph, clk->id);
  67. }
  68. static void scmi_clk_disable(struct clk_hw *hw)
  69. {
  70. struct scmi_clk *clk = to_scmi_clk(hw);
  71. scmi_proto_clk_ops->disable(clk->ph, clk->id);
  72. }
  73. static int scmi_clk_atomic_enable(struct clk_hw *hw)
  74. {
  75. struct scmi_clk *clk = to_scmi_clk(hw);
  76. return scmi_proto_clk_ops->enable_atomic(clk->ph, clk->id);
  77. }
  78. static void scmi_clk_atomic_disable(struct clk_hw *hw)
  79. {
  80. struct scmi_clk *clk = to_scmi_clk(hw);
  81. scmi_proto_clk_ops->disable_atomic(clk->ph, clk->id);
  82. }
  83. /*
  84. * We can provide enable/disable atomic callbacks only if the underlying SCMI
  85. * transport for an SCMI instance is configured to handle SCMI commands in an
  86. * atomic manner.
  87. *
  88. * When no SCMI atomic transport support is available we instead provide only
  89. * the prepare/unprepare API, as allowed by the clock framework when atomic
  90. * calls are not available.
  91. *
  92. * Two distinct sets of clk_ops are provided since we could have multiple SCMI
  93. * instances with different underlying transport quality, so they cannot be
  94. * shared.
  95. */
  96. static const struct clk_ops scmi_clk_ops = {
  97. .recalc_rate = scmi_clk_recalc_rate,
  98. .round_rate = scmi_clk_round_rate,
  99. .set_rate = scmi_clk_set_rate,
  100. .prepare = scmi_clk_enable,
  101. .unprepare = scmi_clk_disable,
  102. };
  103. static const struct clk_ops scmi_atomic_clk_ops = {
  104. .recalc_rate = scmi_clk_recalc_rate,
  105. .round_rate = scmi_clk_round_rate,
  106. .set_rate = scmi_clk_set_rate,
  107. .enable = scmi_clk_atomic_enable,
  108. .disable = scmi_clk_atomic_disable,
  109. };
  110. static int scmi_clk_ops_init(struct device *dev, struct scmi_clk *sclk,
  111. const struct clk_ops *scmi_ops)
  112. {
  113. int ret;
  114. unsigned long min_rate, max_rate;
  115. struct clk_init_data init = {
  116. .flags = CLK_GET_RATE_NOCACHE,
  117. .num_parents = 0,
  118. .ops = scmi_ops,
  119. .name = sclk->info->name,
  120. };
  121. sclk->hw.init = &init;
  122. ret = devm_clk_hw_register(dev, &sclk->hw);
  123. if (ret)
  124. return ret;
  125. if (sclk->info->rate_discrete) {
  126. int num_rates = sclk->info->list.num_rates;
  127. if (num_rates <= 0)
  128. return -EINVAL;
  129. min_rate = sclk->info->list.rates[0];
  130. max_rate = sclk->info->list.rates[num_rates - 1];
  131. } else {
  132. min_rate = sclk->info->range.min_rate;
  133. max_rate = sclk->info->range.max_rate;
  134. }
  135. clk_hw_set_rate_range(&sclk->hw, min_rate, max_rate);
  136. return ret;
  137. }
  138. static int scmi_clocks_probe(struct scmi_device *sdev)
  139. {
  140. int idx, count, err;
  141. unsigned int atomic_threshold;
  142. bool is_atomic;
  143. struct clk_hw **hws;
  144. struct clk_hw_onecell_data *clk_data;
  145. struct device *dev = &sdev->dev;
  146. struct device_node *np = dev->of_node;
  147. const struct scmi_handle *handle = sdev->handle;
  148. struct scmi_protocol_handle *ph;
  149. if (!handle)
  150. return -ENODEV;
  151. scmi_proto_clk_ops =
  152. handle->devm_protocol_get(sdev, SCMI_PROTOCOL_CLOCK, &ph);
  153. if (IS_ERR(scmi_proto_clk_ops))
  154. return PTR_ERR(scmi_proto_clk_ops);
  155. count = scmi_proto_clk_ops->count_get(ph);
  156. if (count < 0) {
  157. dev_err(dev, "%pOFn: invalid clock output count\n", np);
  158. return -EINVAL;
  159. }
  160. clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, count),
  161. GFP_KERNEL);
  162. if (!clk_data)
  163. return -ENOMEM;
  164. clk_data->num = count;
  165. hws = clk_data->hws;
  166. is_atomic = handle->is_transport_atomic(handle, &atomic_threshold);
  167. for (idx = 0; idx < count; idx++) {
  168. struct scmi_clk *sclk;
  169. const struct clk_ops *scmi_ops;
  170. sclk = devm_kzalloc(dev, sizeof(*sclk), GFP_KERNEL);
  171. if (!sclk)
  172. return -ENOMEM;
  173. sclk->info = scmi_proto_clk_ops->info_get(ph, idx);
  174. if (!sclk->info) {
  175. dev_dbg(dev, "invalid clock info for idx %d\n", idx);
  176. devm_kfree(dev, sclk);
  177. continue;
  178. }
  179. sclk->id = idx;
  180. sclk->ph = ph;
  181. /*
  182. * Note that when transport is atomic but SCMI protocol did not
  183. * specify (or support) an enable_latency associated with a
  184. * clock, we default to use atomic operations mode.
  185. */
  186. if (is_atomic &&
  187. sclk->info->enable_latency <= atomic_threshold)
  188. scmi_ops = &scmi_atomic_clk_ops;
  189. else
  190. scmi_ops = &scmi_clk_ops;
  191. err = scmi_clk_ops_init(dev, sclk, scmi_ops);
  192. if (err) {
  193. dev_err(dev, "failed to register clock %d\n", idx);
  194. devm_kfree(dev, sclk);
  195. hws[idx] = NULL;
  196. } else {
  197. dev_dbg(dev, "Registered clock:%s%s\n",
  198. sclk->info->name,
  199. scmi_ops == &scmi_atomic_clk_ops ?
  200. " (atomic ops)" : "");
  201. hws[idx] = &sclk->hw;
  202. }
  203. }
  204. return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
  205. clk_data);
  206. }
  207. static const struct scmi_device_id scmi_id_table[] = {
  208. { SCMI_PROTOCOL_CLOCK, "clocks" },
  209. { },
  210. };
  211. MODULE_DEVICE_TABLE(scmi, scmi_id_table);
  212. static struct scmi_driver scmi_clocks_driver = {
  213. .name = "scmi-clocks",
  214. .probe = scmi_clocks_probe,
  215. .id_table = scmi_id_table,
  216. };
  217. module_scmi_driver(scmi_clocks_driver);
  218. MODULE_AUTHOR("Sudeep Holla <[email protected]>");
  219. MODULE_DESCRIPTION("ARM SCMI clock driver");
  220. MODULE_LICENSE("GPL v2");