clk-npcm7xx.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Nuvoton NPCM7xx Clock Generator
  4. * All the clocks are initialized by the bootloader, so this driver allow only
  5. * reading of current settings directly from the hardware.
  6. *
  7. * Copyright (C) 2018 Nuvoton Technologies [email protected]
  8. */
  9. #include <linux/module.h>
  10. #include <linux/clk-provider.h>
  11. #include <linux/io.h>
  12. #include <linux/kernel.h>
  13. #include <linux/of.h>
  14. #include <linux/of_address.h>
  15. #include <linux/slab.h>
  16. #include <linux/err.h>
  17. #include <linux/bitfield.h>
  18. #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
  19. struct npcm7xx_clk_pll {
  20. struct clk_hw hw;
  21. void __iomem *pllcon;
  22. u8 flags;
  23. };
  24. #define to_npcm7xx_clk_pll(_hw) container_of(_hw, struct npcm7xx_clk_pll, hw)
  25. #define PLLCON_LOKI BIT(31)
  26. #define PLLCON_LOKS BIT(30)
  27. #define PLLCON_FBDV GENMASK(27, 16)
  28. #define PLLCON_OTDV2 GENMASK(15, 13)
  29. #define PLLCON_PWDEN BIT(12)
  30. #define PLLCON_OTDV1 GENMASK(10, 8)
  31. #define PLLCON_INDV GENMASK(5, 0)
  32. static unsigned long npcm7xx_clk_pll_recalc_rate(struct clk_hw *hw,
  33. unsigned long parent_rate)
  34. {
  35. struct npcm7xx_clk_pll *pll = to_npcm7xx_clk_pll(hw);
  36. unsigned long fbdv, indv, otdv1, otdv2;
  37. unsigned int val;
  38. u64 ret;
  39. if (parent_rate == 0) {
  40. pr_err("%s: parent rate is zero", __func__);
  41. return 0;
  42. }
  43. val = readl_relaxed(pll->pllcon);
  44. indv = FIELD_GET(PLLCON_INDV, val);
  45. fbdv = FIELD_GET(PLLCON_FBDV, val);
  46. otdv1 = FIELD_GET(PLLCON_OTDV1, val);
  47. otdv2 = FIELD_GET(PLLCON_OTDV2, val);
  48. ret = (u64)parent_rate * fbdv;
  49. do_div(ret, indv * otdv1 * otdv2);
  50. return ret;
  51. }
  52. static const struct clk_ops npcm7xx_clk_pll_ops = {
  53. .recalc_rate = npcm7xx_clk_pll_recalc_rate,
  54. };
  55. static struct clk_hw *
  56. npcm7xx_clk_register_pll(void __iomem *pllcon, const char *name,
  57. const char *parent_name, unsigned long flags)
  58. {
  59. struct npcm7xx_clk_pll *pll;
  60. struct clk_init_data init;
  61. struct clk_hw *hw;
  62. int ret;
  63. pll = kzalloc(sizeof(*pll), GFP_KERNEL);
  64. if (!pll)
  65. return ERR_PTR(-ENOMEM);
  66. pr_debug("%s reg, name=%s, p=%s\n", __func__, name, parent_name);
  67. init.name = name;
  68. init.ops = &npcm7xx_clk_pll_ops;
  69. init.parent_names = &parent_name;
  70. init.num_parents = 1;
  71. init.flags = flags;
  72. pll->pllcon = pllcon;
  73. pll->hw.init = &init;
  74. hw = &pll->hw;
  75. ret = clk_hw_register(NULL, hw);
  76. if (ret) {
  77. kfree(pll);
  78. hw = ERR_PTR(ret);
  79. }
  80. return hw;
  81. }
  82. #define NPCM7XX_CLKEN1 (0x00)
  83. #define NPCM7XX_CLKEN2 (0x28)
  84. #define NPCM7XX_CLKEN3 (0x30)
  85. #define NPCM7XX_CLKSEL (0x04)
  86. #define NPCM7XX_CLKDIV1 (0x08)
  87. #define NPCM7XX_CLKDIV2 (0x2C)
  88. #define NPCM7XX_CLKDIV3 (0x58)
  89. #define NPCM7XX_PLLCON0 (0x0C)
  90. #define NPCM7XX_PLLCON1 (0x10)
  91. #define NPCM7XX_PLLCON2 (0x54)
  92. #define NPCM7XX_SWRSTR (0x14)
  93. #define NPCM7XX_IRQWAKECON (0x18)
  94. #define NPCM7XX_IRQWAKEFLAG (0x1C)
  95. #define NPCM7XX_IPSRST1 (0x20)
  96. #define NPCM7XX_IPSRST2 (0x24)
  97. #define NPCM7XX_IPSRST3 (0x34)
  98. #define NPCM7XX_WD0RCR (0x38)
  99. #define NPCM7XX_WD1RCR (0x3C)
  100. #define NPCM7XX_WD2RCR (0x40)
  101. #define NPCM7XX_SWRSTC1 (0x44)
  102. #define NPCM7XX_SWRSTC2 (0x48)
  103. #define NPCM7XX_SWRSTC3 (0x4C)
  104. #define NPCM7XX_SWRSTC4 (0x50)
  105. #define NPCM7XX_CORSTC (0x5C)
  106. #define NPCM7XX_PLLCONG (0x60)
  107. #define NPCM7XX_AHBCKFI (0x64)
  108. #define NPCM7XX_SECCNT (0x68)
  109. #define NPCM7XX_CNTR25M (0x6C)
  110. struct npcm7xx_clk_mux_data {
  111. u8 shift;
  112. u8 mask;
  113. u32 *table;
  114. const char *name;
  115. const char * const *parent_names;
  116. u8 num_parents;
  117. unsigned long flags;
  118. /*
  119. * If this clock is exported via DT, set onecell_idx to constant
  120. * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
  121. * this specific clock. Otherwise, set to -1.
  122. */
  123. int onecell_idx;
  124. };
  125. struct npcm7xx_clk_div_data {
  126. u32 reg;
  127. u8 shift;
  128. u8 width;
  129. const char *name;
  130. const char *parent_name;
  131. u8 clk_divider_flags;
  132. unsigned long flags;
  133. /*
  134. * If this clock is exported via DT, set onecell_idx to constant
  135. * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
  136. * this specific clock. Otherwise, set to -1.
  137. */
  138. int onecell_idx;
  139. };
  140. struct npcm7xx_clk_pll_data {
  141. u32 reg;
  142. const char *name;
  143. const char *parent_name;
  144. unsigned long flags;
  145. /*
  146. * If this clock is exported via DT, set onecell_idx to constant
  147. * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
  148. * this specific clock. Otherwise, set to -1.
  149. */
  150. int onecell_idx;
  151. };
  152. /*
  153. * Single copy of strings used to refer to clocks within this driver indexed by
  154. * above enum.
  155. */
  156. #define NPCM7XX_CLK_S_REFCLK "refclk"
  157. #define NPCM7XX_CLK_S_SYSBYPCK "sysbypck"
  158. #define NPCM7XX_CLK_S_MCBYPCK "mcbypck"
  159. #define NPCM7XX_CLK_S_GFXBYPCK "gfxbypck"
  160. #define NPCM7XX_CLK_S_PLL0 "pll0"
  161. #define NPCM7XX_CLK_S_PLL1 "pll1"
  162. #define NPCM7XX_CLK_S_PLL1_DIV2 "pll1_div2"
  163. #define NPCM7XX_CLK_S_PLL2 "pll2"
  164. #define NPCM7XX_CLK_S_PLL_GFX "pll_gfx"
  165. #define NPCM7XX_CLK_S_PLL2_DIV2 "pll2_div2"
  166. #define NPCM7XX_CLK_S_PIX_MUX "gfx_pixel"
  167. #define NPCM7XX_CLK_S_GPRFSEL_MUX "gprfsel_mux"
  168. #define NPCM7XX_CLK_S_MC_MUX "mc_phy"
  169. #define NPCM7XX_CLK_S_CPU_MUX "cpu" /*AKA system clock.*/
  170. #define NPCM7XX_CLK_S_MC "mc"
  171. #define NPCM7XX_CLK_S_AXI "axi" /*AKA CLK2*/
  172. #define NPCM7XX_CLK_S_AHB "ahb" /*AKA CLK4*/
  173. #define NPCM7XX_CLK_S_CLKOUT_MUX "clkout_mux"
  174. #define NPCM7XX_CLK_S_UART_MUX "uart_mux"
  175. #define NPCM7XX_CLK_S_TIM_MUX "timer_mux"
  176. #define NPCM7XX_CLK_S_SD_MUX "sd_mux"
  177. #define NPCM7XX_CLK_S_GFXM_MUX "gfxm_mux"
  178. #define NPCM7XX_CLK_S_SU_MUX "serial_usb_mux"
  179. #define NPCM7XX_CLK_S_DVC_MUX "dvc_mux"
  180. #define NPCM7XX_CLK_S_GFX_MUX "gfx_mux"
  181. #define NPCM7XX_CLK_S_GFX_PIXEL "gfx_pixel"
  182. #define NPCM7XX_CLK_S_SPI0 "spi0"
  183. #define NPCM7XX_CLK_S_SPI3 "spi3"
  184. #define NPCM7XX_CLK_S_SPIX "spix"
  185. #define NPCM7XX_CLK_S_APB1 "apb1"
  186. #define NPCM7XX_CLK_S_APB2 "apb2"
  187. #define NPCM7XX_CLK_S_APB3 "apb3"
  188. #define NPCM7XX_CLK_S_APB4 "apb4"
  189. #define NPCM7XX_CLK_S_APB5 "apb5"
  190. #define NPCM7XX_CLK_S_TOCK "tock"
  191. #define NPCM7XX_CLK_S_CLKOUT "clkout"
  192. #define NPCM7XX_CLK_S_UART "uart"
  193. #define NPCM7XX_CLK_S_TIMER "timer"
  194. #define NPCM7XX_CLK_S_MMC "mmc"
  195. #define NPCM7XX_CLK_S_SDHC "sdhc"
  196. #define NPCM7XX_CLK_S_ADC "adc"
  197. #define NPCM7XX_CLK_S_GFX "gfx0_gfx1_mem"
  198. #define NPCM7XX_CLK_S_USBIF "serial_usbif"
  199. #define NPCM7XX_CLK_S_USB_HOST "usb_host"
  200. #define NPCM7XX_CLK_S_USB_BRIDGE "usb_bridge"
  201. #define NPCM7XX_CLK_S_PCI "pci"
  202. static u32 pll_mux_table[] = {0, 1, 2, 3};
  203. static const char * const pll_mux_parents[] __initconst = {
  204. NPCM7XX_CLK_S_PLL0,
  205. NPCM7XX_CLK_S_PLL1_DIV2,
  206. NPCM7XX_CLK_S_REFCLK,
  207. NPCM7XX_CLK_S_PLL2_DIV2,
  208. };
  209. static u32 cpuck_mux_table[] = {0, 1, 2, 3};
  210. static const char * const cpuck_mux_parents[] __initconst = {
  211. NPCM7XX_CLK_S_PLL0,
  212. NPCM7XX_CLK_S_PLL1_DIV2,
  213. NPCM7XX_CLK_S_REFCLK,
  214. NPCM7XX_CLK_S_SYSBYPCK,
  215. };
  216. static u32 pixcksel_mux_table[] = {0, 2};
  217. static const char * const pixcksel_mux_parents[] __initconst = {
  218. NPCM7XX_CLK_S_PLL_GFX,
  219. NPCM7XX_CLK_S_REFCLK,
  220. };
  221. static u32 sucksel_mux_table[] = {2, 3};
  222. static const char * const sucksel_mux_parents[] __initconst = {
  223. NPCM7XX_CLK_S_REFCLK,
  224. NPCM7XX_CLK_S_PLL2_DIV2,
  225. };
  226. static u32 mccksel_mux_table[] = {0, 2, 3};
  227. static const char * const mccksel_mux_parents[] __initconst = {
  228. NPCM7XX_CLK_S_PLL1_DIV2,
  229. NPCM7XX_CLK_S_REFCLK,
  230. NPCM7XX_CLK_S_MCBYPCK,
  231. };
  232. static u32 clkoutsel_mux_table[] = {0, 1, 2, 3, 4};
  233. static const char * const clkoutsel_mux_parents[] __initconst = {
  234. NPCM7XX_CLK_S_PLL0,
  235. NPCM7XX_CLK_S_PLL1_DIV2,
  236. NPCM7XX_CLK_S_REFCLK,
  237. NPCM7XX_CLK_S_PLL_GFX, // divided by 2
  238. NPCM7XX_CLK_S_PLL2_DIV2,
  239. };
  240. static u32 gfxmsel_mux_table[] = {2, 3};
  241. static const char * const gfxmsel_mux_parents[] __initconst = {
  242. NPCM7XX_CLK_S_REFCLK,
  243. NPCM7XX_CLK_S_PLL2_DIV2,
  244. };
  245. static u32 dvcssel_mux_table[] = {2, 3};
  246. static const char * const dvcssel_mux_parents[] __initconst = {
  247. NPCM7XX_CLK_S_REFCLK,
  248. NPCM7XX_CLK_S_PLL2,
  249. };
  250. static const struct npcm7xx_clk_pll_data npcm7xx_plls[] __initconst = {
  251. {NPCM7XX_PLLCON0, NPCM7XX_CLK_S_PLL0, NPCM7XX_CLK_S_REFCLK, 0, -1},
  252. {NPCM7XX_PLLCON1, NPCM7XX_CLK_S_PLL1,
  253. NPCM7XX_CLK_S_REFCLK, 0, -1},
  254. {NPCM7XX_PLLCON2, NPCM7XX_CLK_S_PLL2,
  255. NPCM7XX_CLK_S_REFCLK, 0, -1},
  256. {NPCM7XX_PLLCONG, NPCM7XX_CLK_S_PLL_GFX,
  257. NPCM7XX_CLK_S_REFCLK, 0, -1},
  258. };
  259. static const struct npcm7xx_clk_mux_data npcm7xx_muxes[] __initconst = {
  260. {0, GENMASK(1, 0), cpuck_mux_table, NPCM7XX_CLK_S_CPU_MUX,
  261. cpuck_mux_parents, ARRAY_SIZE(cpuck_mux_parents), CLK_IS_CRITICAL,
  262. NPCM7XX_CLK_CPU},
  263. {4, GENMASK(1, 0), pixcksel_mux_table, NPCM7XX_CLK_S_PIX_MUX,
  264. pixcksel_mux_parents, ARRAY_SIZE(pixcksel_mux_parents), 0,
  265. NPCM7XX_CLK_GFX_PIXEL},
  266. {6, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_SD_MUX,
  267. pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
  268. {8, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_UART_MUX,
  269. pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
  270. {10, GENMASK(1, 0), sucksel_mux_table, NPCM7XX_CLK_S_SU_MUX,
  271. sucksel_mux_parents, ARRAY_SIZE(sucksel_mux_parents), 0, -1},
  272. {12, GENMASK(1, 0), mccksel_mux_table, NPCM7XX_CLK_S_MC_MUX,
  273. mccksel_mux_parents, ARRAY_SIZE(mccksel_mux_parents), 0, -1},
  274. {14, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_TIM_MUX,
  275. pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
  276. {16, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_GFX_MUX,
  277. pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
  278. {18, GENMASK(2, 0), clkoutsel_mux_table, NPCM7XX_CLK_S_CLKOUT_MUX,
  279. clkoutsel_mux_parents, ARRAY_SIZE(clkoutsel_mux_parents), 0, -1},
  280. {21, GENMASK(1, 0), gfxmsel_mux_table, NPCM7XX_CLK_S_GFXM_MUX,
  281. gfxmsel_mux_parents, ARRAY_SIZE(gfxmsel_mux_parents), 0, -1},
  282. {23, GENMASK(1, 0), dvcssel_mux_table, NPCM7XX_CLK_S_DVC_MUX,
  283. dvcssel_mux_parents, ARRAY_SIZE(dvcssel_mux_parents), 0, -1},
  284. };
  285. /* configurable dividers: */
  286. static const struct npcm7xx_clk_div_data npcm7xx_divs[] __initconst = {
  287. {NPCM7XX_CLKDIV1, 28, 3, NPCM7XX_CLK_S_ADC,
  288. NPCM7XX_CLK_S_TIMER, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_ADC},
  289. /*30-28 ADCCKDIV*/
  290. {NPCM7XX_CLKDIV1, 26, 2, NPCM7XX_CLK_S_AHB,
  291. NPCM7XX_CLK_S_AXI, 0, CLK_IS_CRITICAL, NPCM7XX_CLK_AHB},
  292. /*27-26 CLK4DIV*/
  293. {NPCM7XX_CLKDIV1, 21, 5, NPCM7XX_CLK_S_TIMER,
  294. NPCM7XX_CLK_S_TIM_MUX, 0, 0, NPCM7XX_CLK_TIMER},
  295. /*25-21 TIMCKDIV*/
  296. {NPCM7XX_CLKDIV1, 16, 5, NPCM7XX_CLK_S_UART,
  297. NPCM7XX_CLK_S_UART_MUX, 0, 0, NPCM7XX_CLK_UART},
  298. /*20-16 UARTDIV*/
  299. {NPCM7XX_CLKDIV1, 11, 5, NPCM7XX_CLK_S_MMC,
  300. NPCM7XX_CLK_S_SD_MUX, 0, 0, NPCM7XX_CLK_MMC},
  301. /*15-11 MMCCKDIV*/
  302. {NPCM7XX_CLKDIV1, 6, 5, NPCM7XX_CLK_S_SPI3,
  303. NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPI3},
  304. /*10-6 AHB3CKDIV*/
  305. {NPCM7XX_CLKDIV1, 2, 4, NPCM7XX_CLK_S_PCI,
  306. NPCM7XX_CLK_S_GFX_MUX, 0, 0, NPCM7XX_CLK_PCI},
  307. /*5-2 PCICKDIV*/
  308. {NPCM7XX_CLKDIV1, 0, 1, NPCM7XX_CLK_S_AXI,
  309. NPCM7XX_CLK_S_CPU_MUX, CLK_DIVIDER_POWER_OF_TWO, CLK_IS_CRITICAL,
  310. NPCM7XX_CLK_AXI},/*0 CLK2DIV*/
  311. {NPCM7XX_CLKDIV2, 30, 2, NPCM7XX_CLK_S_APB4,
  312. NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB4},
  313. /*31-30 APB4CKDIV*/
  314. {NPCM7XX_CLKDIV2, 28, 2, NPCM7XX_CLK_S_APB3,
  315. NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB3},
  316. /*29-28 APB3CKDIV*/
  317. {NPCM7XX_CLKDIV2, 26, 2, NPCM7XX_CLK_S_APB2,
  318. NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB2},
  319. /*27-26 APB2CKDIV*/
  320. {NPCM7XX_CLKDIV2, 24, 2, NPCM7XX_CLK_S_APB1,
  321. NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB1},
  322. /*25-24 APB1CKDIV*/
  323. {NPCM7XX_CLKDIV2, 22, 2, NPCM7XX_CLK_S_APB5,
  324. NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB5},
  325. /*23-22 APB5CKDIV*/
  326. {NPCM7XX_CLKDIV2, 16, 5, NPCM7XX_CLK_S_CLKOUT,
  327. NPCM7XX_CLK_S_CLKOUT_MUX, 0, 0, NPCM7XX_CLK_CLKOUT},
  328. /*20-16 CLKOUTDIV*/
  329. {NPCM7XX_CLKDIV2, 13, 3, NPCM7XX_CLK_S_GFX,
  330. NPCM7XX_CLK_S_GFX_MUX, 0, 0, NPCM7XX_CLK_GFX},
  331. /*15-13 GFXCKDIV*/
  332. {NPCM7XX_CLKDIV2, 8, 5, NPCM7XX_CLK_S_USB_BRIDGE,
  333. NPCM7XX_CLK_S_SU_MUX, 0, 0, NPCM7XX_CLK_SU},
  334. /*12-8 SUCKDIV*/
  335. {NPCM7XX_CLKDIV2, 4, 4, NPCM7XX_CLK_S_USB_HOST,
  336. NPCM7XX_CLK_S_SU_MUX, 0, 0, NPCM7XX_CLK_SU48},
  337. /*7-4 SU48CKDIV*/
  338. {NPCM7XX_CLKDIV2, 0, 4, NPCM7XX_CLK_S_SDHC,
  339. NPCM7XX_CLK_S_SD_MUX, 0, 0, NPCM7XX_CLK_SDHC}
  340. ,/*3-0 SD1CKDIV*/
  341. {NPCM7XX_CLKDIV3, 6, 5, NPCM7XX_CLK_S_SPI0,
  342. NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPI0},
  343. /*10-6 SPI0CKDV*/
  344. {NPCM7XX_CLKDIV3, 1, 5, NPCM7XX_CLK_S_SPIX,
  345. NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPIX},
  346. /*5-1 SPIXCKDV*/
  347. };
  348. static DEFINE_SPINLOCK(npcm7xx_clk_lock);
  349. static void __init npcm7xx_clk_init(struct device_node *clk_np)
  350. {
  351. struct clk_hw_onecell_data *npcm7xx_clk_data;
  352. void __iomem *clk_base;
  353. struct resource res;
  354. struct clk_hw *hw;
  355. int ret;
  356. int i;
  357. ret = of_address_to_resource(clk_np, 0, &res);
  358. if (ret) {
  359. pr_err("%pOFn: failed to get resource, ret %d\n", clk_np,
  360. ret);
  361. return;
  362. }
  363. clk_base = ioremap(res.start, resource_size(&res));
  364. if (!clk_base)
  365. goto npcm7xx_init_error;
  366. npcm7xx_clk_data = kzalloc(struct_size(npcm7xx_clk_data, hws,
  367. NPCM7XX_NUM_CLOCKS), GFP_KERNEL);
  368. if (!npcm7xx_clk_data)
  369. goto npcm7xx_init_np_err;
  370. npcm7xx_clk_data->num = NPCM7XX_NUM_CLOCKS;
  371. for (i = 0; i < NPCM7XX_NUM_CLOCKS; i++)
  372. npcm7xx_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
  373. /* Register plls */
  374. for (i = 0; i < ARRAY_SIZE(npcm7xx_plls); i++) {
  375. const struct npcm7xx_clk_pll_data *pll_data = &npcm7xx_plls[i];
  376. hw = npcm7xx_clk_register_pll(clk_base + pll_data->reg,
  377. pll_data->name, pll_data->parent_name, pll_data->flags);
  378. if (IS_ERR(hw)) {
  379. pr_err("npcm7xx_clk: Can't register pll\n");
  380. goto npcm7xx_init_fail;
  381. }
  382. if (pll_data->onecell_idx >= 0)
  383. npcm7xx_clk_data->hws[pll_data->onecell_idx] = hw;
  384. }
  385. /* Register fixed dividers */
  386. hw = clk_hw_register_fixed_factor(NULL, NPCM7XX_CLK_S_PLL1_DIV2,
  387. NPCM7XX_CLK_S_PLL1, 0, 1, 2);
  388. if (IS_ERR(hw)) {
  389. pr_err("npcm7xx_clk: Can't register fixed div\n");
  390. goto npcm7xx_init_fail;
  391. }
  392. hw = clk_hw_register_fixed_factor(NULL, NPCM7XX_CLK_S_PLL2_DIV2,
  393. NPCM7XX_CLK_S_PLL2, 0, 1, 2);
  394. if (IS_ERR(hw)) {
  395. pr_err("npcm7xx_clk: Can't register div2\n");
  396. goto npcm7xx_init_fail;
  397. }
  398. /* Register muxes */
  399. for (i = 0; i < ARRAY_SIZE(npcm7xx_muxes); i++) {
  400. const struct npcm7xx_clk_mux_data *mux_data = &npcm7xx_muxes[i];
  401. hw = clk_hw_register_mux_table(NULL,
  402. mux_data->name,
  403. mux_data->parent_names, mux_data->num_parents,
  404. mux_data->flags, clk_base + NPCM7XX_CLKSEL,
  405. mux_data->shift, mux_data->mask, 0,
  406. mux_data->table, &npcm7xx_clk_lock);
  407. if (IS_ERR(hw)) {
  408. pr_err("npcm7xx_clk: Can't register mux\n");
  409. goto npcm7xx_init_fail;
  410. }
  411. if (mux_data->onecell_idx >= 0)
  412. npcm7xx_clk_data->hws[mux_data->onecell_idx] = hw;
  413. }
  414. /* Register clock dividers specified in npcm7xx_divs */
  415. for (i = 0; i < ARRAY_SIZE(npcm7xx_divs); i++) {
  416. const struct npcm7xx_clk_div_data *div_data = &npcm7xx_divs[i];
  417. hw = clk_hw_register_divider(NULL, div_data->name,
  418. div_data->parent_name,
  419. div_data->flags,
  420. clk_base + div_data->reg,
  421. div_data->shift, div_data->width,
  422. div_data->clk_divider_flags, &npcm7xx_clk_lock);
  423. if (IS_ERR(hw)) {
  424. pr_err("npcm7xx_clk: Can't register div table\n");
  425. goto npcm7xx_init_fail;
  426. }
  427. if (div_data->onecell_idx >= 0)
  428. npcm7xx_clk_data->hws[div_data->onecell_idx] = hw;
  429. }
  430. ret = of_clk_add_hw_provider(clk_np, of_clk_hw_onecell_get,
  431. npcm7xx_clk_data);
  432. if (ret)
  433. pr_err("failed to add DT provider: %d\n", ret);
  434. of_node_put(clk_np);
  435. return;
  436. npcm7xx_init_fail:
  437. kfree(npcm7xx_clk_data);
  438. npcm7xx_init_np_err:
  439. iounmap(clk_base);
  440. npcm7xx_init_error:
  441. of_node_put(clk_np);
  442. }
  443. CLK_OF_DECLARE(npcm7xx_clk_init, "nuvoton,npcm750-clk", npcm7xx_clk_init);