clk-lan966x.c 6.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Microchip LAN966x SoC Clock driver.
  4. *
  5. * Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries
  6. *
  7. * Author: Kavyasree Kotagiri <[email protected]>
  8. */
  9. #include <linux/bitfield.h>
  10. #include <linux/clk-provider.h>
  11. #include <linux/io.h>
  12. #include <linux/kernel.h>
  13. #include <linux/module.h>
  14. #include <linux/of.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/slab.h>
  17. #include <dt-bindings/clock/microchip,lan966x.h>
  18. #define GCK_ENA BIT(0)
  19. #define GCK_SRC_SEL GENMASK(9, 8)
  20. #define GCK_PRESCALER GENMASK(23, 16)
  21. #define DIV_MAX 255
  22. static const char *clk_names[N_CLOCKS] = {
  23. "qspi0", "qspi1", "qspi2", "sdmmc0",
  24. "pi", "mcan0", "mcan1", "flexcom0",
  25. "flexcom1", "flexcom2", "flexcom3",
  26. "flexcom4", "timer1", "usb_refclk",
  27. };
  28. struct lan966x_gck {
  29. struct clk_hw hw;
  30. void __iomem *reg;
  31. };
  32. #define to_lan966x_gck(hw) container_of(hw, struct lan966x_gck, hw)
  33. static const struct clk_parent_data lan966x_gck_pdata[] = {
  34. { .fw_name = "cpu", },
  35. { .fw_name = "ddr", },
  36. { .fw_name = "sys", },
  37. };
  38. static struct clk_init_data init = {
  39. .parent_data = lan966x_gck_pdata,
  40. .num_parents = ARRAY_SIZE(lan966x_gck_pdata),
  41. };
  42. struct clk_gate_soc_desc {
  43. const char *name;
  44. int bit_idx;
  45. };
  46. static const struct clk_gate_soc_desc clk_gate_desc[] = {
  47. { "uhphs", 11 },
  48. { "udphs", 10 },
  49. { "mcramc", 9 },
  50. { "hmatrix", 8 },
  51. { }
  52. };
  53. static DEFINE_SPINLOCK(clk_gate_lock);
  54. static void __iomem *base;
  55. static int lan966x_gck_enable(struct clk_hw *hw)
  56. {
  57. struct lan966x_gck *gck = to_lan966x_gck(hw);
  58. u32 val = readl(gck->reg);
  59. val |= GCK_ENA;
  60. writel(val, gck->reg);
  61. return 0;
  62. }
  63. static void lan966x_gck_disable(struct clk_hw *hw)
  64. {
  65. struct lan966x_gck *gck = to_lan966x_gck(hw);
  66. u32 val = readl(gck->reg);
  67. val &= ~GCK_ENA;
  68. writel(val, gck->reg);
  69. }
  70. static int lan966x_gck_set_rate(struct clk_hw *hw,
  71. unsigned long rate,
  72. unsigned long parent_rate)
  73. {
  74. struct lan966x_gck *gck = to_lan966x_gck(hw);
  75. u32 div, val = readl(gck->reg);
  76. if (rate == 0 || parent_rate == 0)
  77. return -EINVAL;
  78. /* Set Prescalar */
  79. div = parent_rate / rate;
  80. val &= ~GCK_PRESCALER;
  81. val |= FIELD_PREP(GCK_PRESCALER, (div - 1));
  82. writel(val, gck->reg);
  83. return 0;
  84. }
  85. static long lan966x_gck_round_rate(struct clk_hw *hw, unsigned long rate,
  86. unsigned long *parent_rate)
  87. {
  88. unsigned int div;
  89. if (rate == 0 || *parent_rate == 0)
  90. return -EINVAL;
  91. if (rate >= *parent_rate)
  92. return *parent_rate;
  93. div = DIV_ROUND_CLOSEST(*parent_rate, rate);
  94. return *parent_rate / div;
  95. }
  96. static unsigned long lan966x_gck_recalc_rate(struct clk_hw *hw,
  97. unsigned long parent_rate)
  98. {
  99. struct lan966x_gck *gck = to_lan966x_gck(hw);
  100. u32 div, val = readl(gck->reg);
  101. div = FIELD_GET(GCK_PRESCALER, val);
  102. return parent_rate / (div + 1);
  103. }
  104. static int lan966x_gck_determine_rate(struct clk_hw *hw,
  105. struct clk_rate_request *req)
  106. {
  107. struct clk_hw *parent;
  108. int i;
  109. for (i = 0; i < clk_hw_get_num_parents(hw); ++i) {
  110. parent = clk_hw_get_parent_by_index(hw, i);
  111. if (!parent)
  112. continue;
  113. /* Allowed prescaler divider range is 0-255 */
  114. if (clk_hw_get_rate(parent) / req->rate <= DIV_MAX) {
  115. req->best_parent_hw = parent;
  116. req->best_parent_rate = clk_hw_get_rate(parent);
  117. return 0;
  118. }
  119. }
  120. return -EINVAL;
  121. }
  122. static u8 lan966x_gck_get_parent(struct clk_hw *hw)
  123. {
  124. struct lan966x_gck *gck = to_lan966x_gck(hw);
  125. u32 val = readl(gck->reg);
  126. return FIELD_GET(GCK_SRC_SEL, val);
  127. }
  128. static int lan966x_gck_set_parent(struct clk_hw *hw, u8 index)
  129. {
  130. struct lan966x_gck *gck = to_lan966x_gck(hw);
  131. u32 val = readl(gck->reg);
  132. val &= ~GCK_SRC_SEL;
  133. val |= FIELD_PREP(GCK_SRC_SEL, index);
  134. writel(val, gck->reg);
  135. return 0;
  136. }
  137. static const struct clk_ops lan966x_gck_ops = {
  138. .enable = lan966x_gck_enable,
  139. .disable = lan966x_gck_disable,
  140. .set_rate = lan966x_gck_set_rate,
  141. .round_rate = lan966x_gck_round_rate,
  142. .recalc_rate = lan966x_gck_recalc_rate,
  143. .determine_rate = lan966x_gck_determine_rate,
  144. .set_parent = lan966x_gck_set_parent,
  145. .get_parent = lan966x_gck_get_parent,
  146. };
  147. static struct clk_hw *lan966x_gck_clk_register(struct device *dev, int i)
  148. {
  149. struct lan966x_gck *priv;
  150. int ret;
  151. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  152. if (!priv)
  153. return ERR_PTR(-ENOMEM);
  154. priv->reg = base + (i * 4);
  155. priv->hw.init = &init;
  156. ret = devm_clk_hw_register(dev, &priv->hw);
  157. if (ret)
  158. return ERR_PTR(ret);
  159. return &priv->hw;
  160. };
  161. static int lan966x_gate_clk_register(struct device *dev,
  162. struct clk_hw_onecell_data *hw_data,
  163. void __iomem *gate_base)
  164. {
  165. int i;
  166. for (i = GCK_GATE_UHPHS; i < N_CLOCKS; ++i) {
  167. int idx = i - GCK_GATE_UHPHS;
  168. hw_data->hws[i] =
  169. devm_clk_hw_register_gate(dev, clk_gate_desc[idx].name,
  170. "lan966x", 0, gate_base,
  171. clk_gate_desc[idx].bit_idx,
  172. 0, &clk_gate_lock);
  173. if (IS_ERR(hw_data->hws[i]))
  174. return dev_err_probe(dev, PTR_ERR(hw_data->hws[i]),
  175. "failed to register %s clock\n",
  176. clk_gate_desc[idx].name);
  177. }
  178. return 0;
  179. }
  180. static int lan966x_clk_probe(struct platform_device *pdev)
  181. {
  182. struct clk_hw_onecell_data *hw_data;
  183. struct device *dev = &pdev->dev;
  184. void __iomem *gate_base;
  185. struct resource *res;
  186. int i, ret;
  187. hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, N_CLOCKS),
  188. GFP_KERNEL);
  189. if (!hw_data)
  190. return -ENOMEM;
  191. base = devm_platform_ioremap_resource(pdev, 0);
  192. if (IS_ERR(base))
  193. return PTR_ERR(base);
  194. init.ops = &lan966x_gck_ops;
  195. hw_data->num = GCK_GATE_UHPHS;
  196. for (i = 0; i < GCK_GATE_UHPHS; i++) {
  197. init.name = clk_names[i];
  198. hw_data->hws[i] = lan966x_gck_clk_register(dev, i);
  199. if (IS_ERR(hw_data->hws[i])) {
  200. dev_err(dev, "failed to register %s clock\n",
  201. init.name);
  202. return PTR_ERR(hw_data->hws[i]);
  203. }
  204. }
  205. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  206. if (res) {
  207. gate_base = devm_ioremap_resource(&pdev->dev, res);
  208. if (IS_ERR(gate_base))
  209. return PTR_ERR(gate_base);
  210. hw_data->num = N_CLOCKS;
  211. ret = lan966x_gate_clk_register(dev, hw_data, gate_base);
  212. if (ret)
  213. return ret;
  214. }
  215. return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, hw_data);
  216. }
  217. static const struct of_device_id lan966x_clk_dt_ids[] = {
  218. { .compatible = "microchip,lan966x-gck", },
  219. { }
  220. };
  221. MODULE_DEVICE_TABLE(of, lan966x_clk_dt_ids);
  222. static struct platform_driver lan966x_clk_driver = {
  223. .probe = lan966x_clk_probe,
  224. .driver = {
  225. .name = "lan966x-clk",
  226. .of_match_table = lan966x_clk_dt_ids,
  227. },
  228. };
  229. module_platform_driver(lan966x_clk_driver);
  230. MODULE_AUTHOR("Kavyasree Kotagiri <[email protected]>");
  231. MODULE_DESCRIPTION("LAN966X clock driver");
  232. MODULE_LICENSE("GPL v2");