clk-k210.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2019-20 Sean Anderson <[email protected]>
  4. * Copyright (c) 2019 Western Digital Corporation or its affiliates.
  5. */
  6. #define pr_fmt(fmt) "k210-clk: " fmt
  7. #include <linux/io.h>
  8. #include <linux/slab.h>
  9. #include <linux/spinlock.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/of.h>
  12. #include <linux/of_clk.h>
  13. #include <linux/of_platform.h>
  14. #include <linux/of_address.h>
  15. #include <linux/clk-provider.h>
  16. #include <linux/bitfield.h>
  17. #include <linux/delay.h>
  18. #include <soc/canaan/k210-sysctl.h>
  19. #include <dt-bindings/clock/k210-clk.h>
  20. struct k210_sysclk;
  21. struct k210_clk {
  22. int id;
  23. struct k210_sysclk *ksc;
  24. struct clk_hw hw;
  25. };
  26. struct k210_clk_cfg {
  27. const char *name;
  28. u8 gate_reg;
  29. u8 gate_bit;
  30. u8 div_reg;
  31. u8 div_shift;
  32. u8 div_width;
  33. u8 div_type;
  34. u8 mux_reg;
  35. u8 mux_bit;
  36. };
  37. enum k210_clk_div_type {
  38. K210_DIV_NONE,
  39. K210_DIV_ONE_BASED,
  40. K210_DIV_DOUBLE_ONE_BASED,
  41. K210_DIV_POWER_OF_TWO,
  42. };
  43. #define K210_GATE(_reg, _bit) \
  44. .gate_reg = (_reg), \
  45. .gate_bit = (_bit)
  46. #define K210_DIV(_reg, _shift, _width, _type) \
  47. .div_reg = (_reg), \
  48. .div_shift = (_shift), \
  49. .div_width = (_width), \
  50. .div_type = (_type)
  51. #define K210_MUX(_reg, _bit) \
  52. .mux_reg = (_reg), \
  53. .mux_bit = (_bit)
  54. static struct k210_clk_cfg k210_clk_cfgs[K210_NUM_CLKS] = {
  55. /* Gated clocks, no mux, no divider */
  56. [K210_CLK_CPU] = {
  57. .name = "cpu",
  58. K210_GATE(K210_SYSCTL_EN_CENT, 0)
  59. },
  60. [K210_CLK_DMA] = {
  61. .name = "dma",
  62. K210_GATE(K210_SYSCTL_EN_PERI, 1)
  63. },
  64. [K210_CLK_FFT] = {
  65. .name = "fft",
  66. K210_GATE(K210_SYSCTL_EN_PERI, 4)
  67. },
  68. [K210_CLK_GPIO] = {
  69. .name = "gpio",
  70. K210_GATE(K210_SYSCTL_EN_PERI, 5)
  71. },
  72. [K210_CLK_UART1] = {
  73. .name = "uart1",
  74. K210_GATE(K210_SYSCTL_EN_PERI, 16)
  75. },
  76. [K210_CLK_UART2] = {
  77. .name = "uart2",
  78. K210_GATE(K210_SYSCTL_EN_PERI, 17)
  79. },
  80. [K210_CLK_UART3] = {
  81. .name = "uart3",
  82. K210_GATE(K210_SYSCTL_EN_PERI, 18)
  83. },
  84. [K210_CLK_FPIOA] = {
  85. .name = "fpioa",
  86. K210_GATE(K210_SYSCTL_EN_PERI, 20)
  87. },
  88. [K210_CLK_SHA] = {
  89. .name = "sha",
  90. K210_GATE(K210_SYSCTL_EN_PERI, 26)
  91. },
  92. [K210_CLK_AES] = {
  93. .name = "aes",
  94. K210_GATE(K210_SYSCTL_EN_PERI, 19)
  95. },
  96. [K210_CLK_OTP] = {
  97. .name = "otp",
  98. K210_GATE(K210_SYSCTL_EN_PERI, 27)
  99. },
  100. [K210_CLK_RTC] = {
  101. .name = "rtc",
  102. K210_GATE(K210_SYSCTL_EN_PERI, 29)
  103. },
  104. /* Gated divider clocks */
  105. [K210_CLK_SRAM0] = {
  106. .name = "sram0",
  107. K210_GATE(K210_SYSCTL_EN_CENT, 1),
  108. K210_DIV(K210_SYSCTL_THR0, 0, 4, K210_DIV_ONE_BASED)
  109. },
  110. [K210_CLK_SRAM1] = {
  111. .name = "sram1",
  112. K210_GATE(K210_SYSCTL_EN_CENT, 2),
  113. K210_DIV(K210_SYSCTL_THR0, 4, 4, K210_DIV_ONE_BASED)
  114. },
  115. [K210_CLK_ROM] = {
  116. .name = "rom",
  117. K210_GATE(K210_SYSCTL_EN_PERI, 0),
  118. K210_DIV(K210_SYSCTL_THR0, 16, 4, K210_DIV_ONE_BASED)
  119. },
  120. [K210_CLK_DVP] = {
  121. .name = "dvp",
  122. K210_GATE(K210_SYSCTL_EN_PERI, 3),
  123. K210_DIV(K210_SYSCTL_THR0, 12, 4, K210_DIV_ONE_BASED)
  124. },
  125. [K210_CLK_APB0] = {
  126. .name = "apb0",
  127. K210_GATE(K210_SYSCTL_EN_CENT, 3),
  128. K210_DIV(K210_SYSCTL_SEL0, 3, 3, K210_DIV_ONE_BASED)
  129. },
  130. [K210_CLK_APB1] = {
  131. .name = "apb1",
  132. K210_GATE(K210_SYSCTL_EN_CENT, 4),
  133. K210_DIV(K210_SYSCTL_SEL0, 6, 3, K210_DIV_ONE_BASED)
  134. },
  135. [K210_CLK_APB2] = {
  136. .name = "apb2",
  137. K210_GATE(K210_SYSCTL_EN_CENT, 5),
  138. K210_DIV(K210_SYSCTL_SEL0, 9, 3, K210_DIV_ONE_BASED)
  139. },
  140. [K210_CLK_AI] = {
  141. .name = "ai",
  142. K210_GATE(K210_SYSCTL_EN_PERI, 2),
  143. K210_DIV(K210_SYSCTL_THR0, 8, 4, K210_DIV_ONE_BASED)
  144. },
  145. [K210_CLK_SPI0] = {
  146. .name = "spi0",
  147. K210_GATE(K210_SYSCTL_EN_PERI, 6),
  148. K210_DIV(K210_SYSCTL_THR1, 0, 8, K210_DIV_DOUBLE_ONE_BASED)
  149. },
  150. [K210_CLK_SPI1] = {
  151. .name = "spi1",
  152. K210_GATE(K210_SYSCTL_EN_PERI, 7),
  153. K210_DIV(K210_SYSCTL_THR1, 8, 8, K210_DIV_DOUBLE_ONE_BASED)
  154. },
  155. [K210_CLK_SPI2] = {
  156. .name = "spi2",
  157. K210_GATE(K210_SYSCTL_EN_PERI, 8),
  158. K210_DIV(K210_SYSCTL_THR1, 16, 8, K210_DIV_DOUBLE_ONE_BASED)
  159. },
  160. [K210_CLK_I2C0] = {
  161. .name = "i2c0",
  162. K210_GATE(K210_SYSCTL_EN_PERI, 13),
  163. K210_DIV(K210_SYSCTL_THR5, 8, 8, K210_DIV_DOUBLE_ONE_BASED)
  164. },
  165. [K210_CLK_I2C1] = {
  166. .name = "i2c1",
  167. K210_GATE(K210_SYSCTL_EN_PERI, 14),
  168. K210_DIV(K210_SYSCTL_THR5, 16, 8, K210_DIV_DOUBLE_ONE_BASED)
  169. },
  170. [K210_CLK_I2C2] = {
  171. .name = "i2c2",
  172. K210_GATE(K210_SYSCTL_EN_PERI, 15),
  173. K210_DIV(K210_SYSCTL_THR5, 24, 8, K210_DIV_DOUBLE_ONE_BASED)
  174. },
  175. [K210_CLK_WDT0] = {
  176. .name = "wdt0",
  177. K210_GATE(K210_SYSCTL_EN_PERI, 24),
  178. K210_DIV(K210_SYSCTL_THR6, 0, 8, K210_DIV_DOUBLE_ONE_BASED)
  179. },
  180. [K210_CLK_WDT1] = {
  181. .name = "wdt1",
  182. K210_GATE(K210_SYSCTL_EN_PERI, 25),
  183. K210_DIV(K210_SYSCTL_THR6, 8, 8, K210_DIV_DOUBLE_ONE_BASED)
  184. },
  185. [K210_CLK_I2S0] = {
  186. .name = "i2s0",
  187. K210_GATE(K210_SYSCTL_EN_PERI, 10),
  188. K210_DIV(K210_SYSCTL_THR3, 0, 16, K210_DIV_DOUBLE_ONE_BASED)
  189. },
  190. [K210_CLK_I2S1] = {
  191. .name = "i2s1",
  192. K210_GATE(K210_SYSCTL_EN_PERI, 11),
  193. K210_DIV(K210_SYSCTL_THR3, 16, 16, K210_DIV_DOUBLE_ONE_BASED)
  194. },
  195. [K210_CLK_I2S2] = {
  196. .name = "i2s2",
  197. K210_GATE(K210_SYSCTL_EN_PERI, 12),
  198. K210_DIV(K210_SYSCTL_THR4, 0, 16, K210_DIV_DOUBLE_ONE_BASED)
  199. },
  200. /* Divider clocks, no gate, no mux */
  201. [K210_CLK_I2S0_M] = {
  202. .name = "i2s0_m",
  203. K210_DIV(K210_SYSCTL_THR4, 16, 8, K210_DIV_DOUBLE_ONE_BASED)
  204. },
  205. [K210_CLK_I2S1_M] = {
  206. .name = "i2s1_m",
  207. K210_DIV(K210_SYSCTL_THR4, 24, 8, K210_DIV_DOUBLE_ONE_BASED)
  208. },
  209. [K210_CLK_I2S2_M] = {
  210. .name = "i2s2_m",
  211. K210_DIV(K210_SYSCTL_THR4, 0, 8, K210_DIV_DOUBLE_ONE_BASED)
  212. },
  213. /* Muxed gated divider clocks */
  214. [K210_CLK_SPI3] = {
  215. .name = "spi3",
  216. K210_GATE(K210_SYSCTL_EN_PERI, 9),
  217. K210_DIV(K210_SYSCTL_THR1, 24, 8, K210_DIV_DOUBLE_ONE_BASED),
  218. K210_MUX(K210_SYSCTL_SEL0, 12)
  219. },
  220. [K210_CLK_TIMER0] = {
  221. .name = "timer0",
  222. K210_GATE(K210_SYSCTL_EN_PERI, 21),
  223. K210_DIV(K210_SYSCTL_THR2, 0, 8, K210_DIV_DOUBLE_ONE_BASED),
  224. K210_MUX(K210_SYSCTL_SEL0, 13)
  225. },
  226. [K210_CLK_TIMER1] = {
  227. .name = "timer1",
  228. K210_GATE(K210_SYSCTL_EN_PERI, 22),
  229. K210_DIV(K210_SYSCTL_THR2, 8, 8, K210_DIV_DOUBLE_ONE_BASED),
  230. K210_MUX(K210_SYSCTL_SEL0, 14)
  231. },
  232. [K210_CLK_TIMER2] = {
  233. .name = "timer2",
  234. K210_GATE(K210_SYSCTL_EN_PERI, 23),
  235. K210_DIV(K210_SYSCTL_THR2, 16, 8, K210_DIV_DOUBLE_ONE_BASED),
  236. K210_MUX(K210_SYSCTL_SEL0, 15)
  237. },
  238. };
  239. /*
  240. * PLL control register bits.
  241. */
  242. #define K210_PLL_CLKR GENMASK(3, 0)
  243. #define K210_PLL_CLKF GENMASK(9, 4)
  244. #define K210_PLL_CLKOD GENMASK(13, 10)
  245. #define K210_PLL_BWADJ GENMASK(19, 14)
  246. #define K210_PLL_RESET (1 << 20)
  247. #define K210_PLL_PWRD (1 << 21)
  248. #define K210_PLL_INTFB (1 << 22)
  249. #define K210_PLL_BYPASS (1 << 23)
  250. #define K210_PLL_TEST (1 << 24)
  251. #define K210_PLL_EN (1 << 25)
  252. #define K210_PLL_SEL GENMASK(27, 26) /* PLL2 only */
  253. /*
  254. * PLL lock register bits.
  255. */
  256. #define K210_PLL_LOCK 0
  257. #define K210_PLL_CLEAR_SLIP 2
  258. #define K210_PLL_TEST_OUT 3
  259. /*
  260. * Clock selector register bits.
  261. */
  262. #define K210_ACLK_SEL BIT(0)
  263. #define K210_ACLK_DIV GENMASK(2, 1)
  264. /*
  265. * PLLs.
  266. */
  267. enum k210_pll_id {
  268. K210_PLL0, K210_PLL1, K210_PLL2, K210_PLL_NUM
  269. };
  270. struct k210_pll {
  271. enum k210_pll_id id;
  272. struct k210_sysclk *ksc;
  273. void __iomem *base;
  274. void __iomem *reg;
  275. void __iomem *lock;
  276. u8 lock_shift;
  277. u8 lock_width;
  278. struct clk_hw hw;
  279. };
  280. #define to_k210_pll(_hw) container_of(_hw, struct k210_pll, hw)
  281. /*
  282. * PLLs configuration: by default PLL0 runs at 780 MHz and PLL1 at 299 MHz.
  283. * The first 2 SRAM banks depend on ACLK/CPU clock which is by default PLL0
  284. * rate divided by 2. Set PLL1 to 390 MHz so that the third SRAM bank has the
  285. * same clock as the first 2.
  286. */
  287. struct k210_pll_cfg {
  288. u32 reg;
  289. u8 lock_shift;
  290. u8 lock_width;
  291. u32 r;
  292. u32 f;
  293. u32 od;
  294. u32 bwadj;
  295. };
  296. static struct k210_pll_cfg k210_plls_cfg[] = {
  297. { K210_SYSCTL_PLL0, 0, 2, 0, 59, 1, 59 }, /* 780 MHz */
  298. { K210_SYSCTL_PLL1, 8, 1, 0, 59, 3, 59 }, /* 390 MHz */
  299. { K210_SYSCTL_PLL2, 16, 1, 0, 22, 1, 22 }, /* 299 MHz */
  300. };
  301. /**
  302. * struct k210_sysclk - sysclk driver data
  303. * @regs: system controller registers start address
  304. * @clk_lock: clock setting spinlock
  305. * @plls: SoC PLLs descriptors
  306. * @aclk: ACLK clock
  307. * @clks: All other clocks
  308. */
  309. struct k210_sysclk {
  310. void __iomem *regs;
  311. spinlock_t clk_lock;
  312. struct k210_pll plls[K210_PLL_NUM];
  313. struct clk_hw aclk;
  314. struct k210_clk clks[K210_NUM_CLKS];
  315. };
  316. #define to_k210_sysclk(_hw) container_of(_hw, struct k210_sysclk, aclk)
  317. /*
  318. * Set ACLK parent selector: 0 for IN0, 1 for PLL0.
  319. */
  320. static void k210_aclk_set_selector(void __iomem *regs, u8 sel)
  321. {
  322. u32 reg = readl(regs + K210_SYSCTL_SEL0);
  323. if (sel)
  324. reg |= K210_ACLK_SEL;
  325. else
  326. reg &= K210_ACLK_SEL;
  327. writel(reg, regs + K210_SYSCTL_SEL0);
  328. }
  329. static void k210_init_pll(void __iomem *regs, enum k210_pll_id pllid,
  330. struct k210_pll *pll)
  331. {
  332. pll->id = pllid;
  333. pll->reg = regs + k210_plls_cfg[pllid].reg;
  334. pll->lock = regs + K210_SYSCTL_PLL_LOCK;
  335. pll->lock_shift = k210_plls_cfg[pllid].lock_shift;
  336. pll->lock_width = k210_plls_cfg[pllid].lock_width;
  337. }
  338. static void k210_pll_wait_for_lock(struct k210_pll *pll)
  339. {
  340. u32 reg, mask = GENMASK(pll->lock_shift + pll->lock_width - 1,
  341. pll->lock_shift);
  342. while (true) {
  343. reg = readl(pll->lock);
  344. if ((reg & mask) == mask)
  345. break;
  346. reg |= BIT(pll->lock_shift + K210_PLL_CLEAR_SLIP);
  347. writel(reg, pll->lock);
  348. }
  349. }
  350. static bool k210_pll_hw_is_enabled(struct k210_pll *pll)
  351. {
  352. u32 reg = readl(pll->reg);
  353. u32 mask = K210_PLL_PWRD | K210_PLL_EN;
  354. if (reg & K210_PLL_RESET)
  355. return false;
  356. return (reg & mask) == mask;
  357. }
  358. static void k210_pll_enable_hw(void __iomem *regs, struct k210_pll *pll)
  359. {
  360. struct k210_pll_cfg *pll_cfg = &k210_plls_cfg[pll->id];
  361. u32 reg;
  362. if (k210_pll_hw_is_enabled(pll))
  363. return;
  364. /*
  365. * For PLL0, we need to re-parent ACLK to IN0 to keep the CPU cores and
  366. * SRAM running.
  367. */
  368. if (pll->id == K210_PLL0)
  369. k210_aclk_set_selector(regs, 0);
  370. /* Set PLL factors */
  371. reg = readl(pll->reg);
  372. reg &= ~GENMASK(19, 0);
  373. reg |= FIELD_PREP(K210_PLL_CLKR, pll_cfg->r);
  374. reg |= FIELD_PREP(K210_PLL_CLKF, pll_cfg->f);
  375. reg |= FIELD_PREP(K210_PLL_CLKOD, pll_cfg->od);
  376. reg |= FIELD_PREP(K210_PLL_BWADJ, pll_cfg->bwadj);
  377. reg |= K210_PLL_PWRD;
  378. writel(reg, pll->reg);
  379. /*
  380. * Reset the PLL: ensure reset is low before asserting it.
  381. * The magic NOPs come from the Kendryte reference SDK.
  382. */
  383. reg &= ~K210_PLL_RESET;
  384. writel(reg, pll->reg);
  385. reg |= K210_PLL_RESET;
  386. writel(reg, pll->reg);
  387. nop();
  388. nop();
  389. reg &= ~K210_PLL_RESET;
  390. writel(reg, pll->reg);
  391. k210_pll_wait_for_lock(pll);
  392. reg &= ~K210_PLL_BYPASS;
  393. reg |= K210_PLL_EN;
  394. writel(reg, pll->reg);
  395. if (pll->id == K210_PLL0)
  396. k210_aclk_set_selector(regs, 1);
  397. }
  398. static int k210_pll_enable(struct clk_hw *hw)
  399. {
  400. struct k210_pll *pll = to_k210_pll(hw);
  401. struct k210_sysclk *ksc = pll->ksc;
  402. unsigned long flags;
  403. spin_lock_irqsave(&ksc->clk_lock, flags);
  404. k210_pll_enable_hw(ksc->regs, pll);
  405. spin_unlock_irqrestore(&ksc->clk_lock, flags);
  406. return 0;
  407. }
  408. static void k210_pll_disable(struct clk_hw *hw)
  409. {
  410. struct k210_pll *pll = to_k210_pll(hw);
  411. struct k210_sysclk *ksc = pll->ksc;
  412. unsigned long flags;
  413. u32 reg;
  414. /*
  415. * Bypassing before powering off is important so child clocks do not
  416. * stop working. This is especially important for pll0, the indirect
  417. * parent of the cpu clock.
  418. */
  419. spin_lock_irqsave(&ksc->clk_lock, flags);
  420. reg = readl(pll->reg);
  421. reg |= K210_PLL_BYPASS;
  422. writel(reg, pll->reg);
  423. reg &= ~K210_PLL_PWRD;
  424. reg &= ~K210_PLL_EN;
  425. writel(reg, pll->reg);
  426. spin_unlock_irqrestore(&ksc->clk_lock, flags);
  427. }
  428. static int k210_pll_is_enabled(struct clk_hw *hw)
  429. {
  430. return k210_pll_hw_is_enabled(to_k210_pll(hw));
  431. }
  432. static unsigned long k210_pll_get_rate(struct clk_hw *hw,
  433. unsigned long parent_rate)
  434. {
  435. struct k210_pll *pll = to_k210_pll(hw);
  436. u32 reg = readl(pll->reg);
  437. u32 r, f, od;
  438. if (reg & K210_PLL_BYPASS)
  439. return parent_rate;
  440. if (!(reg & K210_PLL_PWRD))
  441. return 0;
  442. r = FIELD_GET(K210_PLL_CLKR, reg) + 1;
  443. f = FIELD_GET(K210_PLL_CLKF, reg) + 1;
  444. od = FIELD_GET(K210_PLL_CLKOD, reg) + 1;
  445. return (u64)parent_rate * f / (r * od);
  446. }
  447. static const struct clk_ops k210_pll_ops = {
  448. .enable = k210_pll_enable,
  449. .disable = k210_pll_disable,
  450. .is_enabled = k210_pll_is_enabled,
  451. .recalc_rate = k210_pll_get_rate,
  452. };
  453. static int k210_pll2_set_parent(struct clk_hw *hw, u8 index)
  454. {
  455. struct k210_pll *pll = to_k210_pll(hw);
  456. struct k210_sysclk *ksc = pll->ksc;
  457. unsigned long flags;
  458. u32 reg;
  459. spin_lock_irqsave(&ksc->clk_lock, flags);
  460. reg = readl(pll->reg);
  461. reg &= ~K210_PLL_SEL;
  462. reg |= FIELD_PREP(K210_PLL_SEL, index);
  463. writel(reg, pll->reg);
  464. spin_unlock_irqrestore(&ksc->clk_lock, flags);
  465. return 0;
  466. }
  467. static u8 k210_pll2_get_parent(struct clk_hw *hw)
  468. {
  469. struct k210_pll *pll = to_k210_pll(hw);
  470. u32 reg = readl(pll->reg);
  471. return FIELD_GET(K210_PLL_SEL, reg);
  472. }
  473. static const struct clk_ops k210_pll2_ops = {
  474. .enable = k210_pll_enable,
  475. .disable = k210_pll_disable,
  476. .is_enabled = k210_pll_is_enabled,
  477. .recalc_rate = k210_pll_get_rate,
  478. .set_parent = k210_pll2_set_parent,
  479. .get_parent = k210_pll2_get_parent,
  480. };
  481. static int __init k210_register_pll(struct device_node *np,
  482. struct k210_sysclk *ksc,
  483. enum k210_pll_id pllid, const char *name,
  484. int num_parents, const struct clk_ops *ops)
  485. {
  486. struct k210_pll *pll = &ksc->plls[pllid];
  487. struct clk_init_data init = {};
  488. const struct clk_parent_data parent_data[] = {
  489. { /* .index = 0 for in0 */ },
  490. { .hw = &ksc->plls[K210_PLL0].hw },
  491. { .hw = &ksc->plls[K210_PLL1].hw },
  492. };
  493. init.name = name;
  494. init.parent_data = parent_data;
  495. init.num_parents = num_parents;
  496. init.ops = ops;
  497. pll->hw.init = &init;
  498. pll->ksc = ksc;
  499. return of_clk_hw_register(np, &pll->hw);
  500. }
  501. static int __init k210_register_plls(struct device_node *np,
  502. struct k210_sysclk *ksc)
  503. {
  504. int i, ret;
  505. for (i = 0; i < K210_PLL_NUM; i++)
  506. k210_init_pll(ksc->regs, i, &ksc->plls[i]);
  507. /* PLL0 and PLL1 only have IN0 as parent */
  508. ret = k210_register_pll(np, ksc, K210_PLL0, "pll0", 1, &k210_pll_ops);
  509. if (ret) {
  510. pr_err("%pOFP: register PLL0 failed\n", np);
  511. return ret;
  512. }
  513. ret = k210_register_pll(np, ksc, K210_PLL1, "pll1", 1, &k210_pll_ops);
  514. if (ret) {
  515. pr_err("%pOFP: register PLL1 failed\n", np);
  516. return ret;
  517. }
  518. /* PLL2 has IN0, PLL0 and PLL1 as parents */
  519. ret = k210_register_pll(np, ksc, K210_PLL2, "pll2", 3, &k210_pll2_ops);
  520. if (ret) {
  521. pr_err("%pOFP: register PLL2 failed\n", np);
  522. return ret;
  523. }
  524. return 0;
  525. }
  526. static int k210_aclk_set_parent(struct clk_hw *hw, u8 index)
  527. {
  528. struct k210_sysclk *ksc = to_k210_sysclk(hw);
  529. unsigned long flags;
  530. spin_lock_irqsave(&ksc->clk_lock, flags);
  531. k210_aclk_set_selector(ksc->regs, index);
  532. spin_unlock_irqrestore(&ksc->clk_lock, flags);
  533. return 0;
  534. }
  535. static u8 k210_aclk_get_parent(struct clk_hw *hw)
  536. {
  537. struct k210_sysclk *ksc = to_k210_sysclk(hw);
  538. u32 sel;
  539. sel = readl(ksc->regs + K210_SYSCTL_SEL0) & K210_ACLK_SEL;
  540. return sel ? 1 : 0;
  541. }
  542. static unsigned long k210_aclk_get_rate(struct clk_hw *hw,
  543. unsigned long parent_rate)
  544. {
  545. struct k210_sysclk *ksc = to_k210_sysclk(hw);
  546. u32 reg = readl(ksc->regs + K210_SYSCTL_SEL0);
  547. unsigned int shift;
  548. if (!(reg & 0x1))
  549. return parent_rate;
  550. shift = FIELD_GET(K210_ACLK_DIV, reg);
  551. return parent_rate / (2UL << shift);
  552. }
  553. static const struct clk_ops k210_aclk_ops = {
  554. .set_parent = k210_aclk_set_parent,
  555. .get_parent = k210_aclk_get_parent,
  556. .recalc_rate = k210_aclk_get_rate,
  557. };
  558. /*
  559. * ACLK has IN0 and PLL0 as parents.
  560. */
  561. static int __init k210_register_aclk(struct device_node *np,
  562. struct k210_sysclk *ksc)
  563. {
  564. struct clk_init_data init = {};
  565. const struct clk_parent_data parent_data[] = {
  566. { /* .index = 0 for in0 */ },
  567. { .hw = &ksc->plls[K210_PLL0].hw },
  568. };
  569. int ret;
  570. init.name = "aclk";
  571. init.parent_data = parent_data;
  572. init.num_parents = 2;
  573. init.ops = &k210_aclk_ops;
  574. ksc->aclk.init = &init;
  575. ret = of_clk_hw_register(np, &ksc->aclk);
  576. if (ret) {
  577. pr_err("%pOFP: register aclk failed\n", np);
  578. return ret;
  579. }
  580. return 0;
  581. }
  582. #define to_k210_clk(_hw) container_of(_hw, struct k210_clk, hw)
  583. static int k210_clk_enable(struct clk_hw *hw)
  584. {
  585. struct k210_clk *kclk = to_k210_clk(hw);
  586. struct k210_sysclk *ksc = kclk->ksc;
  587. struct k210_clk_cfg *cfg = &k210_clk_cfgs[kclk->id];
  588. unsigned long flags;
  589. u32 reg;
  590. if (!cfg->gate_reg)
  591. return 0;
  592. spin_lock_irqsave(&ksc->clk_lock, flags);
  593. reg = readl(ksc->regs + cfg->gate_reg);
  594. reg |= BIT(cfg->gate_bit);
  595. writel(reg, ksc->regs + cfg->gate_reg);
  596. spin_unlock_irqrestore(&ksc->clk_lock, flags);
  597. return 0;
  598. }
  599. static void k210_clk_disable(struct clk_hw *hw)
  600. {
  601. struct k210_clk *kclk = to_k210_clk(hw);
  602. struct k210_sysclk *ksc = kclk->ksc;
  603. struct k210_clk_cfg *cfg = &k210_clk_cfgs[kclk->id];
  604. unsigned long flags;
  605. u32 reg;
  606. if (!cfg->gate_reg)
  607. return;
  608. spin_lock_irqsave(&ksc->clk_lock, flags);
  609. reg = readl(ksc->regs + cfg->gate_reg);
  610. reg &= ~BIT(cfg->gate_bit);
  611. writel(reg, ksc->regs + cfg->gate_reg);
  612. spin_unlock_irqrestore(&ksc->clk_lock, flags);
  613. }
  614. static int k210_clk_set_parent(struct clk_hw *hw, u8 index)
  615. {
  616. struct k210_clk *kclk = to_k210_clk(hw);
  617. struct k210_sysclk *ksc = kclk->ksc;
  618. struct k210_clk_cfg *cfg = &k210_clk_cfgs[kclk->id];
  619. unsigned long flags;
  620. u32 reg;
  621. spin_lock_irqsave(&ksc->clk_lock, flags);
  622. reg = readl(ksc->regs + cfg->mux_reg);
  623. if (index)
  624. reg |= BIT(cfg->mux_bit);
  625. else
  626. reg &= ~BIT(cfg->mux_bit);
  627. writel(reg, ksc->regs + cfg->mux_reg);
  628. spin_unlock_irqrestore(&ksc->clk_lock, flags);
  629. return 0;
  630. }
  631. static u8 k210_clk_get_parent(struct clk_hw *hw)
  632. {
  633. struct k210_clk *kclk = to_k210_clk(hw);
  634. struct k210_sysclk *ksc = kclk->ksc;
  635. struct k210_clk_cfg *cfg = &k210_clk_cfgs[kclk->id];
  636. unsigned long flags;
  637. u32 reg, idx;
  638. spin_lock_irqsave(&ksc->clk_lock, flags);
  639. reg = readl(ksc->regs + cfg->mux_reg);
  640. idx = (reg & BIT(cfg->mux_bit)) ? 1 : 0;
  641. spin_unlock_irqrestore(&ksc->clk_lock, flags);
  642. return idx;
  643. }
  644. static unsigned long k210_clk_get_rate(struct clk_hw *hw,
  645. unsigned long parent_rate)
  646. {
  647. struct k210_clk *kclk = to_k210_clk(hw);
  648. struct k210_sysclk *ksc = kclk->ksc;
  649. struct k210_clk_cfg *cfg = &k210_clk_cfgs[kclk->id];
  650. u32 reg, div_val;
  651. if (!cfg->div_reg)
  652. return parent_rate;
  653. reg = readl(ksc->regs + cfg->div_reg);
  654. div_val = (reg >> cfg->div_shift) & GENMASK(cfg->div_width - 1, 0);
  655. switch (cfg->div_type) {
  656. case K210_DIV_ONE_BASED:
  657. return parent_rate / (div_val + 1);
  658. case K210_DIV_DOUBLE_ONE_BASED:
  659. return parent_rate / ((div_val + 1) * 2);
  660. case K210_DIV_POWER_OF_TWO:
  661. return parent_rate / (2UL << div_val);
  662. case K210_DIV_NONE:
  663. default:
  664. return 0;
  665. }
  666. }
  667. static const struct clk_ops k210_clk_mux_ops = {
  668. .enable = k210_clk_enable,
  669. .disable = k210_clk_disable,
  670. .set_parent = k210_clk_set_parent,
  671. .get_parent = k210_clk_get_parent,
  672. .recalc_rate = k210_clk_get_rate,
  673. };
  674. static const struct clk_ops k210_clk_ops = {
  675. .enable = k210_clk_enable,
  676. .disable = k210_clk_disable,
  677. .recalc_rate = k210_clk_get_rate,
  678. };
  679. static void __init k210_register_clk(struct device_node *np,
  680. struct k210_sysclk *ksc, int id,
  681. const struct clk_parent_data *parent_data,
  682. int num_parents, unsigned long flags)
  683. {
  684. struct k210_clk *kclk = &ksc->clks[id];
  685. struct clk_init_data init = {};
  686. int ret;
  687. init.name = k210_clk_cfgs[id].name;
  688. init.flags = flags;
  689. init.parent_data = parent_data;
  690. init.num_parents = num_parents;
  691. if (num_parents > 1)
  692. init.ops = &k210_clk_mux_ops;
  693. else
  694. init.ops = &k210_clk_ops;
  695. kclk->id = id;
  696. kclk->ksc = ksc;
  697. kclk->hw.init = &init;
  698. ret = of_clk_hw_register(np, &kclk->hw);
  699. if (ret) {
  700. pr_err("%pOFP: register clock %s failed\n",
  701. np, k210_clk_cfgs[id].name);
  702. kclk->id = -1;
  703. }
  704. }
  705. /*
  706. * All muxed clocks have IN0 and PLL0 as parents.
  707. */
  708. static inline void __init k210_register_mux_clk(struct device_node *np,
  709. struct k210_sysclk *ksc, int id)
  710. {
  711. const struct clk_parent_data parent_data[2] = {
  712. { /* .index = 0 for in0 */ },
  713. { .hw = &ksc->plls[K210_PLL0].hw }
  714. };
  715. k210_register_clk(np, ksc, id, parent_data, 2, 0);
  716. }
  717. static inline void __init k210_register_in0_child(struct device_node *np,
  718. struct k210_sysclk *ksc, int id)
  719. {
  720. const struct clk_parent_data parent_data = {
  721. /* .index = 0 for in0 */
  722. };
  723. k210_register_clk(np, ksc, id, &parent_data, 1, 0);
  724. }
  725. static inline void __init k210_register_pll_child(struct device_node *np,
  726. struct k210_sysclk *ksc, int id,
  727. enum k210_pll_id pllid,
  728. unsigned long flags)
  729. {
  730. const struct clk_parent_data parent_data = {
  731. .hw = &ksc->plls[pllid].hw,
  732. };
  733. k210_register_clk(np, ksc, id, &parent_data, 1, flags);
  734. }
  735. static inline void __init k210_register_aclk_child(struct device_node *np,
  736. struct k210_sysclk *ksc, int id,
  737. unsigned long flags)
  738. {
  739. const struct clk_parent_data parent_data = {
  740. .hw = &ksc->aclk,
  741. };
  742. k210_register_clk(np, ksc, id, &parent_data, 1, flags);
  743. }
  744. static inline void __init k210_register_clk_child(struct device_node *np,
  745. struct k210_sysclk *ksc, int id,
  746. int parent_id)
  747. {
  748. const struct clk_parent_data parent_data = {
  749. .hw = &ksc->clks[parent_id].hw,
  750. };
  751. k210_register_clk(np, ksc, id, &parent_data, 1, 0);
  752. }
  753. static struct clk_hw *k210_clk_hw_onecell_get(struct of_phandle_args *clkspec,
  754. void *data)
  755. {
  756. struct k210_sysclk *ksc = data;
  757. unsigned int idx = clkspec->args[0];
  758. if (idx >= K210_NUM_CLKS)
  759. return ERR_PTR(-EINVAL);
  760. return &ksc->clks[idx].hw;
  761. }
  762. static void __init k210_clk_init(struct device_node *np)
  763. {
  764. struct device_node *sysctl_np;
  765. struct k210_sysclk *ksc;
  766. int i, ret;
  767. ksc = kzalloc(sizeof(*ksc), GFP_KERNEL);
  768. if (!ksc)
  769. return;
  770. spin_lock_init(&ksc->clk_lock);
  771. sysctl_np = of_get_parent(np);
  772. ksc->regs = of_iomap(sysctl_np, 0);
  773. of_node_put(sysctl_np);
  774. if (!ksc->regs) {
  775. pr_err("%pOFP: failed to map registers\n", np);
  776. return;
  777. }
  778. ret = k210_register_plls(np, ksc);
  779. if (ret)
  780. return;
  781. ret = k210_register_aclk(np, ksc);
  782. if (ret)
  783. return;
  784. /*
  785. * Critical clocks: there are no consumers of the SRAM clocks,
  786. * including the AI clock for the third SRAM bank. The CPU clock
  787. * is only referenced by the uarths serial device and so would be
  788. * disabled if the serial console is disabled to switch to another
  789. * console. Mark all these clocks as critical so that they are never
  790. * disabled by the core clock management.
  791. */
  792. k210_register_aclk_child(np, ksc, K210_CLK_CPU, CLK_IS_CRITICAL);
  793. k210_register_aclk_child(np, ksc, K210_CLK_SRAM0, CLK_IS_CRITICAL);
  794. k210_register_aclk_child(np, ksc, K210_CLK_SRAM1, CLK_IS_CRITICAL);
  795. k210_register_pll_child(np, ksc, K210_CLK_AI, K210_PLL1,
  796. CLK_IS_CRITICAL);
  797. /* Clocks with aclk as source */
  798. k210_register_aclk_child(np, ksc, K210_CLK_DMA, 0);
  799. k210_register_aclk_child(np, ksc, K210_CLK_FFT, 0);
  800. k210_register_aclk_child(np, ksc, K210_CLK_ROM, 0);
  801. k210_register_aclk_child(np, ksc, K210_CLK_DVP, 0);
  802. k210_register_aclk_child(np, ksc, K210_CLK_APB0, 0);
  803. k210_register_aclk_child(np, ksc, K210_CLK_APB1, 0);
  804. k210_register_aclk_child(np, ksc, K210_CLK_APB2, 0);
  805. /* Clocks with PLL0 as source */
  806. k210_register_pll_child(np, ksc, K210_CLK_SPI0, K210_PLL0, 0);
  807. k210_register_pll_child(np, ksc, K210_CLK_SPI1, K210_PLL0, 0);
  808. k210_register_pll_child(np, ksc, K210_CLK_SPI2, K210_PLL0, 0);
  809. k210_register_pll_child(np, ksc, K210_CLK_I2C0, K210_PLL0, 0);
  810. k210_register_pll_child(np, ksc, K210_CLK_I2C1, K210_PLL0, 0);
  811. k210_register_pll_child(np, ksc, K210_CLK_I2C2, K210_PLL0, 0);
  812. /* Clocks with PLL2 as source */
  813. k210_register_pll_child(np, ksc, K210_CLK_I2S0, K210_PLL2, 0);
  814. k210_register_pll_child(np, ksc, K210_CLK_I2S1, K210_PLL2, 0);
  815. k210_register_pll_child(np, ksc, K210_CLK_I2S2, K210_PLL2, 0);
  816. k210_register_pll_child(np, ksc, K210_CLK_I2S0_M, K210_PLL2, 0);
  817. k210_register_pll_child(np, ksc, K210_CLK_I2S1_M, K210_PLL2, 0);
  818. k210_register_pll_child(np, ksc, K210_CLK_I2S2_M, K210_PLL2, 0);
  819. /* Clocks with IN0 as source */
  820. k210_register_in0_child(np, ksc, K210_CLK_WDT0);
  821. k210_register_in0_child(np, ksc, K210_CLK_WDT1);
  822. k210_register_in0_child(np, ksc, K210_CLK_RTC);
  823. /* Clocks with APB0 as source */
  824. k210_register_clk_child(np, ksc, K210_CLK_GPIO, K210_CLK_APB0);
  825. k210_register_clk_child(np, ksc, K210_CLK_UART1, K210_CLK_APB0);
  826. k210_register_clk_child(np, ksc, K210_CLK_UART2, K210_CLK_APB0);
  827. k210_register_clk_child(np, ksc, K210_CLK_UART3, K210_CLK_APB0);
  828. k210_register_clk_child(np, ksc, K210_CLK_FPIOA, K210_CLK_APB0);
  829. k210_register_clk_child(np, ksc, K210_CLK_SHA, K210_CLK_APB0);
  830. /* Clocks with APB1 as source */
  831. k210_register_clk_child(np, ksc, K210_CLK_AES, K210_CLK_APB1);
  832. k210_register_clk_child(np, ksc, K210_CLK_OTP, K210_CLK_APB1);
  833. /* Mux clocks with in0 or pll0 as source */
  834. k210_register_mux_clk(np, ksc, K210_CLK_SPI3);
  835. k210_register_mux_clk(np, ksc, K210_CLK_TIMER0);
  836. k210_register_mux_clk(np, ksc, K210_CLK_TIMER1);
  837. k210_register_mux_clk(np, ksc, K210_CLK_TIMER2);
  838. /* Check for registration errors */
  839. for (i = 0; i < K210_NUM_CLKS; i++) {
  840. if (ksc->clks[i].id != i)
  841. return;
  842. }
  843. ret = of_clk_add_hw_provider(np, k210_clk_hw_onecell_get, ksc);
  844. if (ret) {
  845. pr_err("%pOFP: add clock provider failed %d\n", np, ret);
  846. return;
  847. }
  848. pr_info("%pOFP: CPU running at %lu MHz\n",
  849. np, clk_hw_get_rate(&ksc->clks[K210_CLK_CPU].hw) / 1000000);
  850. }
  851. CLK_OF_DECLARE(k210_clk, "canaan,k210-clk", k210_clk_init);
  852. /*
  853. * Enable PLL1 to be able to use the AI SRAM.
  854. */
  855. void __init k210_clk_early_init(void __iomem *regs)
  856. {
  857. struct k210_pll pll1;
  858. /* Make sure ACLK selector is set to PLL0 */
  859. k210_aclk_set_selector(regs, 1);
  860. /* Startup PLL1 to enable the aisram bank for general memory use */
  861. k210_init_pll(regs, K210_PLL1, &pll1);
  862. k210_pll_enable_hw(regs, &pll1);
  863. }