clk-axi-clkgen.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * AXI clkgen driver
  4. *
  5. * Copyright 2012-2013 Analog Devices Inc.
  6. * Author: Lars-Peter Clausen <[email protected]>
  7. */
  8. #include <linux/platform_device.h>
  9. #include <linux/clk-provider.h>
  10. #include <linux/slab.h>
  11. #include <linux/io.h>
  12. #include <linux/of.h>
  13. #include <linux/module.h>
  14. #include <linux/err.h>
  15. #define AXI_CLKGEN_V2_REG_RESET 0x40
  16. #define AXI_CLKGEN_V2_REG_CLKSEL 0x44
  17. #define AXI_CLKGEN_V2_REG_DRP_CNTRL 0x70
  18. #define AXI_CLKGEN_V2_REG_DRP_STATUS 0x74
  19. #define AXI_CLKGEN_V2_RESET_MMCM_ENABLE BIT(1)
  20. #define AXI_CLKGEN_V2_RESET_ENABLE BIT(0)
  21. #define AXI_CLKGEN_V2_DRP_CNTRL_SEL BIT(29)
  22. #define AXI_CLKGEN_V2_DRP_CNTRL_READ BIT(28)
  23. #define AXI_CLKGEN_V2_DRP_STATUS_BUSY BIT(16)
  24. #define MMCM_REG_CLKOUT5_2 0x07
  25. #define MMCM_REG_CLKOUT0_1 0x08
  26. #define MMCM_REG_CLKOUT0_2 0x09
  27. #define MMCM_REG_CLKOUT6_2 0x13
  28. #define MMCM_REG_CLK_FB1 0x14
  29. #define MMCM_REG_CLK_FB2 0x15
  30. #define MMCM_REG_CLK_DIV 0x16
  31. #define MMCM_REG_LOCK1 0x18
  32. #define MMCM_REG_LOCK2 0x19
  33. #define MMCM_REG_LOCK3 0x1a
  34. #define MMCM_REG_POWER 0x28
  35. #define MMCM_REG_FILTER1 0x4e
  36. #define MMCM_REG_FILTER2 0x4f
  37. #define MMCM_CLKOUT_NOCOUNT BIT(6)
  38. #define MMCM_CLK_DIV_DIVIDE BIT(11)
  39. #define MMCM_CLK_DIV_NOCOUNT BIT(12)
  40. struct axi_clkgen_limits {
  41. unsigned int fpfd_min;
  42. unsigned int fpfd_max;
  43. unsigned int fvco_min;
  44. unsigned int fvco_max;
  45. };
  46. struct axi_clkgen {
  47. void __iomem *base;
  48. struct clk_hw clk_hw;
  49. struct axi_clkgen_limits limits;
  50. };
  51. static uint32_t axi_clkgen_lookup_filter(unsigned int m)
  52. {
  53. switch (m) {
  54. case 0:
  55. return 0x01001990;
  56. case 1:
  57. return 0x01001190;
  58. case 2:
  59. return 0x01009890;
  60. case 3:
  61. return 0x01001890;
  62. case 4:
  63. return 0x01008890;
  64. case 5 ... 8:
  65. return 0x01009090;
  66. case 9 ... 11:
  67. return 0x01000890;
  68. case 12:
  69. return 0x08009090;
  70. case 13 ... 22:
  71. return 0x01001090;
  72. case 23 ... 36:
  73. return 0x01008090;
  74. case 37 ... 46:
  75. return 0x08001090;
  76. default:
  77. return 0x08008090;
  78. }
  79. }
  80. static const uint32_t axi_clkgen_lock_table[] = {
  81. 0x060603e8, 0x060603e8, 0x080803e8, 0x0b0b03e8,
  82. 0x0e0e03e8, 0x111103e8, 0x131303e8, 0x161603e8,
  83. 0x191903e8, 0x1c1c03e8, 0x1f1f0384, 0x1f1f0339,
  84. 0x1f1f02ee, 0x1f1f02bc, 0x1f1f028a, 0x1f1f0271,
  85. 0x1f1f023f, 0x1f1f0226, 0x1f1f020d, 0x1f1f01f4,
  86. 0x1f1f01db, 0x1f1f01c2, 0x1f1f01a9, 0x1f1f0190,
  87. 0x1f1f0190, 0x1f1f0177, 0x1f1f015e, 0x1f1f015e,
  88. 0x1f1f0145, 0x1f1f0145, 0x1f1f012c, 0x1f1f012c,
  89. 0x1f1f012c, 0x1f1f0113, 0x1f1f0113, 0x1f1f0113,
  90. };
  91. static uint32_t axi_clkgen_lookup_lock(unsigned int m)
  92. {
  93. if (m < ARRAY_SIZE(axi_clkgen_lock_table))
  94. return axi_clkgen_lock_table[m];
  95. return 0x1f1f00fa;
  96. }
  97. static const struct axi_clkgen_limits axi_clkgen_zynqmp_default_limits = {
  98. .fpfd_min = 10000,
  99. .fpfd_max = 450000,
  100. .fvco_min = 800000,
  101. .fvco_max = 1600000,
  102. };
  103. static const struct axi_clkgen_limits axi_clkgen_zynq_default_limits = {
  104. .fpfd_min = 10000,
  105. .fpfd_max = 300000,
  106. .fvco_min = 600000,
  107. .fvco_max = 1200000,
  108. };
  109. static void axi_clkgen_calc_params(const struct axi_clkgen_limits *limits,
  110. unsigned long fin, unsigned long fout,
  111. unsigned int *best_d, unsigned int *best_m, unsigned int *best_dout)
  112. {
  113. unsigned long d, d_min, d_max, _d_min, _d_max;
  114. unsigned long m, m_min, m_max;
  115. unsigned long f, dout, best_f, fvco;
  116. unsigned long fract_shift = 0;
  117. unsigned long fvco_min_fract, fvco_max_fract;
  118. fin /= 1000;
  119. fout /= 1000;
  120. best_f = ULONG_MAX;
  121. *best_d = 0;
  122. *best_m = 0;
  123. *best_dout = 0;
  124. d_min = max_t(unsigned long, DIV_ROUND_UP(fin, limits->fpfd_max), 1);
  125. d_max = min_t(unsigned long, fin / limits->fpfd_min, 80);
  126. again:
  127. fvco_min_fract = limits->fvco_min << fract_shift;
  128. fvco_max_fract = limits->fvco_max << fract_shift;
  129. m_min = max_t(unsigned long, DIV_ROUND_UP(fvco_min_fract, fin) * d_min, 1);
  130. m_max = min_t(unsigned long, fvco_max_fract * d_max / fin, 64 << fract_shift);
  131. for (m = m_min; m <= m_max; m++) {
  132. _d_min = max(d_min, DIV_ROUND_UP(fin * m, fvco_max_fract));
  133. _d_max = min(d_max, fin * m / fvco_min_fract);
  134. for (d = _d_min; d <= _d_max; d++) {
  135. fvco = fin * m / d;
  136. dout = DIV_ROUND_CLOSEST(fvco, fout);
  137. dout = clamp_t(unsigned long, dout, 1, 128 << fract_shift);
  138. f = fvco / dout;
  139. if (abs(f - fout) < abs(best_f - fout)) {
  140. best_f = f;
  141. *best_d = d;
  142. *best_m = m << (3 - fract_shift);
  143. *best_dout = dout << (3 - fract_shift);
  144. if (best_f == fout)
  145. return;
  146. }
  147. }
  148. }
  149. /* Lets see if we find a better setting in fractional mode */
  150. if (fract_shift == 0) {
  151. fract_shift = 3;
  152. goto again;
  153. }
  154. }
  155. struct axi_clkgen_div_params {
  156. unsigned int low;
  157. unsigned int high;
  158. unsigned int edge;
  159. unsigned int nocount;
  160. unsigned int frac_en;
  161. unsigned int frac;
  162. unsigned int frac_wf_f;
  163. unsigned int frac_wf_r;
  164. unsigned int frac_phase;
  165. };
  166. static void axi_clkgen_calc_clk_params(unsigned int divider,
  167. unsigned int frac_divider, struct axi_clkgen_div_params *params)
  168. {
  169. memset(params, 0x0, sizeof(*params));
  170. if (divider == 1) {
  171. params->nocount = 1;
  172. return;
  173. }
  174. if (frac_divider == 0) {
  175. params->high = divider / 2;
  176. params->edge = divider % 2;
  177. params->low = divider - params->high;
  178. } else {
  179. params->frac_en = 1;
  180. params->frac = frac_divider;
  181. params->high = divider / 2;
  182. params->edge = divider % 2;
  183. params->low = params->high;
  184. if (params->edge == 0) {
  185. params->high--;
  186. params->frac_wf_r = 1;
  187. }
  188. if (params->edge == 0 || frac_divider == 1)
  189. params->low--;
  190. if (((params->edge == 0) ^ (frac_divider == 1)) ||
  191. (divider == 2 && frac_divider == 1))
  192. params->frac_wf_f = 1;
  193. params->frac_phase = params->edge * 4 + frac_divider / 2;
  194. }
  195. }
  196. static void axi_clkgen_write(struct axi_clkgen *axi_clkgen,
  197. unsigned int reg, unsigned int val)
  198. {
  199. writel(val, axi_clkgen->base + reg);
  200. }
  201. static void axi_clkgen_read(struct axi_clkgen *axi_clkgen,
  202. unsigned int reg, unsigned int *val)
  203. {
  204. *val = readl(axi_clkgen->base + reg);
  205. }
  206. static int axi_clkgen_wait_non_busy(struct axi_clkgen *axi_clkgen)
  207. {
  208. unsigned int timeout = 10000;
  209. unsigned int val;
  210. do {
  211. axi_clkgen_read(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_STATUS, &val);
  212. } while ((val & AXI_CLKGEN_V2_DRP_STATUS_BUSY) && --timeout);
  213. if (val & AXI_CLKGEN_V2_DRP_STATUS_BUSY)
  214. return -EIO;
  215. return val & 0xffff;
  216. }
  217. static int axi_clkgen_mmcm_read(struct axi_clkgen *axi_clkgen,
  218. unsigned int reg, unsigned int *val)
  219. {
  220. unsigned int reg_val;
  221. int ret;
  222. ret = axi_clkgen_wait_non_busy(axi_clkgen);
  223. if (ret < 0)
  224. return ret;
  225. reg_val = AXI_CLKGEN_V2_DRP_CNTRL_SEL | AXI_CLKGEN_V2_DRP_CNTRL_READ;
  226. reg_val |= (reg << 16);
  227. axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val);
  228. ret = axi_clkgen_wait_non_busy(axi_clkgen);
  229. if (ret < 0)
  230. return ret;
  231. *val = ret;
  232. return 0;
  233. }
  234. static int axi_clkgen_mmcm_write(struct axi_clkgen *axi_clkgen,
  235. unsigned int reg, unsigned int val, unsigned int mask)
  236. {
  237. unsigned int reg_val = 0;
  238. int ret;
  239. ret = axi_clkgen_wait_non_busy(axi_clkgen);
  240. if (ret < 0)
  241. return ret;
  242. if (mask != 0xffff) {
  243. axi_clkgen_mmcm_read(axi_clkgen, reg, &reg_val);
  244. reg_val &= ~mask;
  245. }
  246. reg_val |= AXI_CLKGEN_V2_DRP_CNTRL_SEL | (reg << 16) | (val & mask);
  247. axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val);
  248. return 0;
  249. }
  250. static void axi_clkgen_mmcm_enable(struct axi_clkgen *axi_clkgen,
  251. bool enable)
  252. {
  253. unsigned int val = AXI_CLKGEN_V2_RESET_ENABLE;
  254. if (enable)
  255. val |= AXI_CLKGEN_V2_RESET_MMCM_ENABLE;
  256. axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_RESET, val);
  257. }
  258. static struct axi_clkgen *clk_hw_to_axi_clkgen(struct clk_hw *clk_hw)
  259. {
  260. return container_of(clk_hw, struct axi_clkgen, clk_hw);
  261. }
  262. static void axi_clkgen_set_div(struct axi_clkgen *axi_clkgen,
  263. unsigned int reg1, unsigned int reg2, unsigned int reg3,
  264. struct axi_clkgen_div_params *params)
  265. {
  266. axi_clkgen_mmcm_write(axi_clkgen, reg1,
  267. (params->high << 6) | params->low, 0xefff);
  268. axi_clkgen_mmcm_write(axi_clkgen, reg2,
  269. (params->frac << 12) | (params->frac_en << 11) |
  270. (params->frac_wf_r << 10) | (params->edge << 7) |
  271. (params->nocount << 6), 0x7fff);
  272. if (reg3 != 0) {
  273. axi_clkgen_mmcm_write(axi_clkgen, reg3,
  274. (params->frac_phase << 11) | (params->frac_wf_f << 10), 0x3c00);
  275. }
  276. }
  277. static int axi_clkgen_set_rate(struct clk_hw *clk_hw,
  278. unsigned long rate, unsigned long parent_rate)
  279. {
  280. struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
  281. const struct axi_clkgen_limits *limits = &axi_clkgen->limits;
  282. unsigned int d, m, dout;
  283. struct axi_clkgen_div_params params;
  284. uint32_t power = 0;
  285. uint32_t filter;
  286. uint32_t lock;
  287. if (parent_rate == 0 || rate == 0)
  288. return -EINVAL;
  289. axi_clkgen_calc_params(limits, parent_rate, rate, &d, &m, &dout);
  290. if (d == 0 || dout == 0 || m == 0)
  291. return -EINVAL;
  292. if ((dout & 0x7) != 0 || (m & 0x7) != 0)
  293. power |= 0x9800;
  294. axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_POWER, power, 0x9800);
  295. filter = axi_clkgen_lookup_filter(m - 1);
  296. lock = axi_clkgen_lookup_lock(m - 1);
  297. axi_clkgen_calc_clk_params(dout >> 3, dout & 0x7, &params);
  298. axi_clkgen_set_div(axi_clkgen, MMCM_REG_CLKOUT0_1, MMCM_REG_CLKOUT0_2,
  299. MMCM_REG_CLKOUT5_2, &params);
  300. axi_clkgen_calc_clk_params(d, 0, &params);
  301. axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_DIV,
  302. (params.edge << 13) | (params.nocount << 12) |
  303. (params.high << 6) | params.low, 0x3fff);
  304. axi_clkgen_calc_clk_params(m >> 3, m & 0x7, &params);
  305. axi_clkgen_set_div(axi_clkgen, MMCM_REG_CLK_FB1, MMCM_REG_CLK_FB2,
  306. MMCM_REG_CLKOUT6_2, &params);
  307. axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK1, lock & 0x3ff, 0x3ff);
  308. axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK2,
  309. (((lock >> 16) & 0x1f) << 10) | 0x1, 0x7fff);
  310. axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK3,
  311. (((lock >> 24) & 0x1f) << 10) | 0x3e9, 0x7fff);
  312. axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER1, filter >> 16, 0x9900);
  313. axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER2, filter, 0x9900);
  314. return 0;
  315. }
  316. static long axi_clkgen_round_rate(struct clk_hw *hw, unsigned long rate,
  317. unsigned long *parent_rate)
  318. {
  319. struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(hw);
  320. const struct axi_clkgen_limits *limits = &axi_clkgen->limits;
  321. unsigned int d, m, dout;
  322. unsigned long long tmp;
  323. axi_clkgen_calc_params(limits, *parent_rate, rate, &d, &m, &dout);
  324. if (d == 0 || dout == 0 || m == 0)
  325. return -EINVAL;
  326. tmp = (unsigned long long)*parent_rate * m;
  327. tmp = DIV_ROUND_CLOSEST_ULL(tmp, dout * d);
  328. return min_t(unsigned long long, tmp, LONG_MAX);
  329. }
  330. static unsigned int axi_clkgen_get_div(struct axi_clkgen *axi_clkgen,
  331. unsigned int reg1, unsigned int reg2)
  332. {
  333. unsigned int val1, val2;
  334. unsigned int div;
  335. axi_clkgen_mmcm_read(axi_clkgen, reg2, &val2);
  336. if (val2 & MMCM_CLKOUT_NOCOUNT)
  337. return 8;
  338. axi_clkgen_mmcm_read(axi_clkgen, reg1, &val1);
  339. div = (val1 & 0x3f) + ((val1 >> 6) & 0x3f);
  340. div <<= 3;
  341. if (val2 & MMCM_CLK_DIV_DIVIDE) {
  342. if ((val2 & BIT(7)) && (val2 & 0x7000) != 0x1000)
  343. div += 8;
  344. else
  345. div += 16;
  346. div += (val2 >> 12) & 0x7;
  347. }
  348. return div;
  349. }
  350. static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw,
  351. unsigned long parent_rate)
  352. {
  353. struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
  354. unsigned int d, m, dout;
  355. unsigned long long tmp;
  356. unsigned int val;
  357. dout = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLKOUT0_1,
  358. MMCM_REG_CLKOUT0_2);
  359. m = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLK_FB1,
  360. MMCM_REG_CLK_FB2);
  361. axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_DIV, &val);
  362. if (val & MMCM_CLK_DIV_NOCOUNT)
  363. d = 1;
  364. else
  365. d = (val & 0x3f) + ((val >> 6) & 0x3f);
  366. if (d == 0 || dout == 0)
  367. return 0;
  368. tmp = (unsigned long long)parent_rate * m;
  369. tmp = DIV_ROUND_CLOSEST_ULL(tmp, dout * d);
  370. return min_t(unsigned long long, tmp, ULONG_MAX);
  371. }
  372. static int axi_clkgen_enable(struct clk_hw *clk_hw)
  373. {
  374. struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
  375. axi_clkgen_mmcm_enable(axi_clkgen, true);
  376. return 0;
  377. }
  378. static void axi_clkgen_disable(struct clk_hw *clk_hw)
  379. {
  380. struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
  381. axi_clkgen_mmcm_enable(axi_clkgen, false);
  382. }
  383. static int axi_clkgen_set_parent(struct clk_hw *clk_hw, u8 index)
  384. {
  385. struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
  386. axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_CLKSEL, index);
  387. return 0;
  388. }
  389. static u8 axi_clkgen_get_parent(struct clk_hw *clk_hw)
  390. {
  391. struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
  392. unsigned int parent;
  393. axi_clkgen_read(axi_clkgen, AXI_CLKGEN_V2_REG_CLKSEL, &parent);
  394. return parent;
  395. }
  396. static const struct clk_ops axi_clkgen_ops = {
  397. .recalc_rate = axi_clkgen_recalc_rate,
  398. .round_rate = axi_clkgen_round_rate,
  399. .set_rate = axi_clkgen_set_rate,
  400. .enable = axi_clkgen_enable,
  401. .disable = axi_clkgen_disable,
  402. .set_parent = axi_clkgen_set_parent,
  403. .get_parent = axi_clkgen_get_parent,
  404. };
  405. static int axi_clkgen_probe(struct platform_device *pdev)
  406. {
  407. const struct axi_clkgen_limits *dflt_limits;
  408. struct axi_clkgen *axi_clkgen;
  409. struct clk_init_data init;
  410. const char *parent_names[2];
  411. const char *clk_name;
  412. unsigned int i;
  413. int ret;
  414. dflt_limits = device_get_match_data(&pdev->dev);
  415. if (!dflt_limits)
  416. return -ENODEV;
  417. axi_clkgen = devm_kzalloc(&pdev->dev, sizeof(*axi_clkgen), GFP_KERNEL);
  418. if (!axi_clkgen)
  419. return -ENOMEM;
  420. axi_clkgen->base = devm_platform_ioremap_resource(pdev, 0);
  421. if (IS_ERR(axi_clkgen->base))
  422. return PTR_ERR(axi_clkgen->base);
  423. init.num_parents = of_clk_get_parent_count(pdev->dev.of_node);
  424. if (init.num_parents < 1 || init.num_parents > 2)
  425. return -EINVAL;
  426. for (i = 0; i < init.num_parents; i++) {
  427. parent_names[i] = of_clk_get_parent_name(pdev->dev.of_node, i);
  428. if (!parent_names[i])
  429. return -EINVAL;
  430. }
  431. memcpy(&axi_clkgen->limits, dflt_limits, sizeof(axi_clkgen->limits));
  432. clk_name = pdev->dev.of_node->name;
  433. of_property_read_string(pdev->dev.of_node, "clock-output-names",
  434. &clk_name);
  435. init.name = clk_name;
  436. init.ops = &axi_clkgen_ops;
  437. init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
  438. init.parent_names = parent_names;
  439. axi_clkgen_mmcm_enable(axi_clkgen, false);
  440. axi_clkgen->clk_hw.init = &init;
  441. ret = devm_clk_hw_register(&pdev->dev, &axi_clkgen->clk_hw);
  442. if (ret)
  443. return ret;
  444. return of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_simple_get,
  445. &axi_clkgen->clk_hw);
  446. }
  447. static int axi_clkgen_remove(struct platform_device *pdev)
  448. {
  449. of_clk_del_provider(pdev->dev.of_node);
  450. return 0;
  451. }
  452. static const struct of_device_id axi_clkgen_ids[] = {
  453. {
  454. .compatible = "adi,zynqmp-axi-clkgen-2.00.a",
  455. .data = &axi_clkgen_zynqmp_default_limits,
  456. },
  457. {
  458. .compatible = "adi,axi-clkgen-2.00.a",
  459. .data = &axi_clkgen_zynq_default_limits,
  460. },
  461. { }
  462. };
  463. MODULE_DEVICE_TABLE(of, axi_clkgen_ids);
  464. static struct platform_driver axi_clkgen_driver = {
  465. .driver = {
  466. .name = "adi-axi-clkgen",
  467. .of_match_table = axi_clkgen_ids,
  468. },
  469. .probe = axi_clkgen_probe,
  470. .remove = axi_clkgen_remove,
  471. };
  472. module_platform_driver(axi_clkgen_driver);
  473. MODULE_LICENSE("GPL v2");
  474. MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
  475. MODULE_DESCRIPTION("Driver for the Analog Devices' AXI clkgen pcore clock generator");