Kconfig 2.1 KB

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  1. # SPDX-License-Identifier: GPL-2.0-only
  2. config CLK_BAIKAL_T1
  3. bool "Baikal-T1 Clocks Control Unit interface"
  4. depends on (MIPS_BAIKAL_T1 && OF) || COMPILE_TEST
  5. default MIPS_BAIKAL_T1
  6. help
  7. Clocks Control Unit is the core of Baikal-T1 SoC System Controller
  8. responsible for the chip subsystems clocking and resetting. It
  9. consists of multiple global clock domains, which can be reset by
  10. means of the CCU control registers. These domains and devices placed
  11. in them are fed with clocks generated by a hierarchy of PLLs,
  12. configurable and fixed clock dividers. Enable this option to be able
  13. to select Baikal-T1 CCU PLLs and Dividers drivers.
  14. if CLK_BAIKAL_T1
  15. config CLK_BT1_CCU_PLL
  16. bool "Baikal-T1 CCU PLLs support"
  17. select MFD_SYSCON
  18. default MIPS_BAIKAL_T1
  19. help
  20. Enable this to support the PLLs embedded into the Baikal-T1 SoC
  21. System Controller. These are five PLLs placed at the root of the
  22. clocks hierarchy, right after an external reference oscillator
  23. (normally of 25MHz). They are used to generate high frequency
  24. signals, which are either directly wired to the consumers (like
  25. CPUs, DDR, etc.) or passed over the clock dividers to be only
  26. then used as an individual reference clock of a target device.
  27. config CLK_BT1_CCU_DIV
  28. bool "Baikal-T1 CCU Dividers support"
  29. select MFD_SYSCON
  30. default MIPS_BAIKAL_T1
  31. help
  32. Enable this to support the CCU dividers used to distribute clocks
  33. between AXI-bus and system devices coming from CCU PLLs of Baikal-T1
  34. SoC. CCU dividers can be either configurable or with fixed divider,
  35. either gateable or ungateable. Some of the CCU dividers can be as well
  36. used to reset the domains they're supplying clock to.
  37. config CLK_BT1_CCU_RST
  38. bool "Baikal-T1 CCU Resets support"
  39. select RESET_CONTROLLER
  40. select MFD_SYSCON
  41. default MIPS_BAIKAL_T1
  42. help
  43. Enable this to support the CCU reset blocks responsible for the
  44. AXI-bus and some subsystems reset. These are mainly the
  45. self-deasserted reset controls but there are several lines which
  46. can be directly asserted/de-asserted (PCIe and DDR sub-domains).
  47. endif