wrpll-cln28hpc.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018-2019 SiFive, Inc.
  4. * Wesley Terpstra
  5. * Paul Walmsley
  6. *
  7. * This library supports configuration parsing and reprogramming of
  8. * the CLN28HPC variant of the Analog Bits Wide Range PLL. The
  9. * intention is for this library to be reusable for any device that
  10. * integrates this PLL; thus the register structure and programming
  11. * details are expected to be provided by a separate IP block driver.
  12. *
  13. * The bulk of this code is primarily useful for clock configurations
  14. * that must operate at arbitrary rates, as opposed to clock configurations
  15. * that are restricted by software or manufacturer guidance to a small,
  16. * pre-determined set of performance points.
  17. *
  18. * References:
  19. * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
  20. * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
  21. * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
  22. */
  23. #include <linux/bug.h>
  24. #include <linux/err.h>
  25. #include <linux/limits.h>
  26. #include <linux/log2.h>
  27. #include <linux/math64.h>
  28. #include <linux/math.h>
  29. #include <linux/minmax.h>
  30. #include <linux/clk/analogbits-wrpll-cln28hpc.h>
  31. /* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */
  32. #define MIN_INPUT_FREQ 7000000
  33. /* MAX_INPUT_FREQ: maximum input clock frequency, in Hz (Fref_max) */
  34. #define MAX_INPUT_FREQ 600000000
  35. /* MIN_POST_DIVIDE_REF_FREQ: minimum post-divider reference frequency, in Hz */
  36. #define MIN_POST_DIVR_FREQ 7000000
  37. /* MAX_POST_DIVIDE_REF_FREQ: maximum post-divider reference frequency, in Hz */
  38. #define MAX_POST_DIVR_FREQ 200000000
  39. /* MIN_VCO_FREQ: minimum VCO frequency, in Hz (Fvco_min) */
  40. #define MIN_VCO_FREQ 2400000000UL
  41. /* MAX_VCO_FREQ: maximum VCO frequency, in Hz (Fvco_max) */
  42. #define MAX_VCO_FREQ 4800000000ULL
  43. /* MAX_DIVQ_DIVISOR: maximum output divisor. Selected by DIVQ = 6 */
  44. #define MAX_DIVQ_DIVISOR 64
  45. /* MAX_DIVR_DIVISOR: maximum reference divisor. Selected by DIVR = 63 */
  46. #define MAX_DIVR_DIVISOR 64
  47. /* MAX_LOCK_US: maximum PLL lock time, in microseconds (tLOCK_max) */
  48. #define MAX_LOCK_US 70
  49. /*
  50. * ROUND_SHIFT: number of bits to shift to avoid precision loss in the rounding
  51. * algorithm
  52. */
  53. #define ROUND_SHIFT 20
  54. /*
  55. * Private functions
  56. */
  57. /**
  58. * __wrpll_calc_filter_range() - determine PLL loop filter bandwidth
  59. * @post_divr_freq: input clock rate after the R divider
  60. *
  61. * Select the value to be presented to the PLL RANGE input signals, based
  62. * on the input clock frequency after the post-R-divider @post_divr_freq.
  63. * This code follows the recommendations in the PLL datasheet for filter
  64. * range selection.
  65. *
  66. * Return: The RANGE value to be presented to the PLL configuration inputs,
  67. * or a negative return code upon error.
  68. */
  69. static int __wrpll_calc_filter_range(unsigned long post_divr_freq)
  70. {
  71. if (post_divr_freq < MIN_POST_DIVR_FREQ ||
  72. post_divr_freq > MAX_POST_DIVR_FREQ) {
  73. WARN(1, "%s: post-divider reference freq out of range: %lu",
  74. __func__, post_divr_freq);
  75. return -ERANGE;
  76. }
  77. switch (post_divr_freq) {
  78. case 0 ... 10999999:
  79. return 1;
  80. case 11000000 ... 17999999:
  81. return 2;
  82. case 18000000 ... 29999999:
  83. return 3;
  84. case 30000000 ... 49999999:
  85. return 4;
  86. case 50000000 ... 79999999:
  87. return 5;
  88. case 80000000 ... 129999999:
  89. return 6;
  90. }
  91. return 7;
  92. }
  93. /**
  94. * __wrpll_calc_fbdiv() - return feedback fixed divide value
  95. * @c: ptr to a struct wrpll_cfg record to read from
  96. *
  97. * The internal feedback path includes a fixed by-two divider; the
  98. * external feedback path does not. Return the appropriate divider
  99. * value (2 or 1) depending on whether internal or external feedback
  100. * is enabled. This code doesn't test for invalid configurations
  101. * (e.g. both or neither of WRPLL_FLAGS_*_FEEDBACK are set); it relies
  102. * on the caller to do so.
  103. *
  104. * Context: Any context. Caller must protect the memory pointed to by
  105. * @c from simultaneous modification.
  106. *
  107. * Return: 2 if internal feedback is enabled or 1 if external feedback
  108. * is enabled.
  109. */
  110. static u8 __wrpll_calc_fbdiv(const struct wrpll_cfg *c)
  111. {
  112. return (c->flags & WRPLL_FLAGS_INT_FEEDBACK_MASK) ? 2 : 1;
  113. }
  114. /**
  115. * __wrpll_calc_divq() - determine DIVQ based on target PLL output clock rate
  116. * @target_rate: target PLL output clock rate
  117. * @vco_rate: pointer to a u64 to store the computed VCO rate into
  118. *
  119. * Determine a reasonable value for the PLL Q post-divider, based on the
  120. * target output rate @target_rate for the PLL. Along with returning the
  121. * computed Q divider value as the return value, this function stores the
  122. * desired target VCO rate into the variable pointed to by @vco_rate.
  123. *
  124. * Context: Any context. Caller must protect the memory pointed to by
  125. * @vco_rate from simultaneous access or modification.
  126. *
  127. * Return: a positive integer DIVQ value to be programmed into the hardware
  128. * upon success, or 0 upon error (since 0 is an invalid DIVQ value)
  129. */
  130. static u8 __wrpll_calc_divq(u32 target_rate, u64 *vco_rate)
  131. {
  132. u64 s;
  133. u8 divq = 0;
  134. if (!vco_rate) {
  135. WARN_ON(1);
  136. goto wcd_out;
  137. }
  138. s = div_u64(MAX_VCO_FREQ, target_rate);
  139. if (s <= 1) {
  140. divq = 1;
  141. *vco_rate = MAX_VCO_FREQ;
  142. } else if (s > MAX_DIVQ_DIVISOR) {
  143. divq = ilog2(MAX_DIVQ_DIVISOR);
  144. *vco_rate = MIN_VCO_FREQ;
  145. } else {
  146. divq = ilog2(s);
  147. *vco_rate = (u64)target_rate << divq;
  148. }
  149. wcd_out:
  150. return divq;
  151. }
  152. /**
  153. * __wrpll_update_parent_rate() - update PLL data when parent rate changes
  154. * @c: ptr to a struct wrpll_cfg record to write PLL data to
  155. * @parent_rate: PLL input refclk rate (pre-R-divider)
  156. *
  157. * Pre-compute some data used by the PLL configuration algorithm when
  158. * the PLL's reference clock rate changes. The intention is to avoid
  159. * computation when the parent rate remains constant - expected to be
  160. * the common case.
  161. *
  162. * Returns: 0 upon success or -ERANGE if the reference clock rate is
  163. * out of range.
  164. */
  165. static int __wrpll_update_parent_rate(struct wrpll_cfg *c,
  166. unsigned long parent_rate)
  167. {
  168. u8 max_r_for_parent;
  169. if (parent_rate > MAX_INPUT_FREQ || parent_rate < MIN_POST_DIVR_FREQ)
  170. return -ERANGE;
  171. c->parent_rate = parent_rate;
  172. max_r_for_parent = div_u64(parent_rate, MIN_POST_DIVR_FREQ);
  173. c->max_r = min_t(u8, MAX_DIVR_DIVISOR, max_r_for_parent);
  174. c->init_r = DIV_ROUND_UP_ULL(parent_rate, MAX_POST_DIVR_FREQ);
  175. return 0;
  176. }
  177. /**
  178. * wrpll_configure_for_rate() - compute PLL configuration for a target rate
  179. * @c: ptr to a struct wrpll_cfg record to write into
  180. * @target_rate: target PLL output clock rate (post-Q-divider)
  181. * @parent_rate: PLL input refclk rate (pre-R-divider)
  182. *
  183. * Compute the appropriate PLL signal configuration values and store
  184. * in PLL context @c. PLL reprogramming is not glitchless, so the
  185. * caller should switch any downstream logic to a different clock
  186. * source or clock-gate it before presenting these values to the PLL
  187. * configuration signals.
  188. *
  189. * The caller must pass this function a pre-initialized struct
  190. * wrpll_cfg record: either initialized to zero (with the
  191. * exception of the .name and .flags fields) or read from the PLL.
  192. *
  193. * Context: Any context. Caller must protect the memory pointed to by @c
  194. * from simultaneous access or modification.
  195. *
  196. * Return: 0 upon success; anything else upon failure.
  197. */
  198. int wrpll_configure_for_rate(struct wrpll_cfg *c, u32 target_rate,
  199. unsigned long parent_rate)
  200. {
  201. unsigned long ratio;
  202. u64 target_vco_rate, delta, best_delta, f_pre_div, vco, vco_pre;
  203. u32 best_f, f, post_divr_freq;
  204. u8 fbdiv, divq, best_r, r;
  205. int range;
  206. if (c->flags == 0) {
  207. WARN(1, "%s called with uninitialized PLL config", __func__);
  208. return -EINVAL;
  209. }
  210. /* Initialize rounding data if it hasn't been initialized already */
  211. if (parent_rate != c->parent_rate) {
  212. if (__wrpll_update_parent_rate(c, parent_rate)) {
  213. pr_err("%s: PLL input rate is out of range\n",
  214. __func__);
  215. return -ERANGE;
  216. }
  217. }
  218. c->flags &= ~WRPLL_FLAGS_RESET_MASK;
  219. /* Put the PLL into bypass if the user requests the parent clock rate */
  220. if (target_rate == parent_rate) {
  221. c->flags |= WRPLL_FLAGS_BYPASS_MASK;
  222. return 0;
  223. }
  224. c->flags &= ~WRPLL_FLAGS_BYPASS_MASK;
  225. /* Calculate the Q shift and target VCO rate */
  226. divq = __wrpll_calc_divq(target_rate, &target_vco_rate);
  227. if (!divq)
  228. return -1;
  229. c->divq = divq;
  230. /* Precalculate the pre-Q divider target ratio */
  231. ratio = div64_u64((target_vco_rate << ROUND_SHIFT), parent_rate);
  232. fbdiv = __wrpll_calc_fbdiv(c);
  233. best_r = 0;
  234. best_f = 0;
  235. best_delta = MAX_VCO_FREQ;
  236. /*
  237. * Consider all values for R which land within
  238. * [MIN_POST_DIVR_FREQ, MAX_POST_DIVR_FREQ]; prefer smaller R
  239. */
  240. for (r = c->init_r; r <= c->max_r; ++r) {
  241. f_pre_div = ratio * r;
  242. f = (f_pre_div + (1 << ROUND_SHIFT)) >> ROUND_SHIFT;
  243. f >>= (fbdiv - 1);
  244. post_divr_freq = div_u64(parent_rate, r);
  245. vco_pre = fbdiv * post_divr_freq;
  246. vco = vco_pre * f;
  247. /* Ensure rounding didn't take us out of range */
  248. if (vco > target_vco_rate) {
  249. --f;
  250. vco = vco_pre * f;
  251. } else if (vco < MIN_VCO_FREQ) {
  252. ++f;
  253. vco = vco_pre * f;
  254. }
  255. delta = abs(target_rate - vco);
  256. if (delta < best_delta) {
  257. best_delta = delta;
  258. best_r = r;
  259. best_f = f;
  260. }
  261. }
  262. c->divr = best_r - 1;
  263. c->divf = best_f - 1;
  264. post_divr_freq = div_u64(parent_rate, best_r);
  265. /* Pick the best PLL jitter filter */
  266. range = __wrpll_calc_filter_range(post_divr_freq);
  267. if (range < 0)
  268. return range;
  269. c->range = range;
  270. return 0;
  271. }
  272. /**
  273. * wrpll_calc_output_rate() - calculate the PLL's target output rate
  274. * @c: ptr to a struct wrpll_cfg record to read from
  275. * @parent_rate: PLL refclk rate
  276. *
  277. * Given a pointer to the PLL's current input configuration @c and the
  278. * PLL's input reference clock rate @parent_rate (before the R
  279. * pre-divider), calculate the PLL's output clock rate (after the Q
  280. * post-divider).
  281. *
  282. * Context: Any context. Caller must protect the memory pointed to by @c
  283. * from simultaneous modification.
  284. *
  285. * Return: the PLL's output clock rate, in Hz. The return value from
  286. * this function is intended to be convenient to pass directly
  287. * to the Linux clock framework; thus there is no explicit
  288. * error return value.
  289. */
  290. unsigned long wrpll_calc_output_rate(const struct wrpll_cfg *c,
  291. unsigned long parent_rate)
  292. {
  293. u8 fbdiv;
  294. u64 n;
  295. if (c->flags & WRPLL_FLAGS_EXT_FEEDBACK_MASK) {
  296. WARN(1, "external feedback mode not yet supported");
  297. return ULONG_MAX;
  298. }
  299. fbdiv = __wrpll_calc_fbdiv(c);
  300. n = parent_rate * fbdiv * (c->divf + 1);
  301. n = div_u64(n, c->divr + 1);
  302. n >>= c->divq;
  303. return n;
  304. }
  305. /**
  306. * wrpll_calc_max_lock_us() - return the time for the PLL to lock
  307. * @c: ptr to a struct wrpll_cfg record to read from
  308. *
  309. * Return the minimum amount of time (in microseconds) that the caller
  310. * must wait after reprogramming the PLL to ensure that it is locked
  311. * to the input frequency and stable. This is likely to depend on the DIVR
  312. * value; this is under discussion with the manufacturer.
  313. *
  314. * Return: the minimum amount of time the caller must wait for the PLL
  315. * to lock (in microseconds)
  316. */
  317. unsigned int wrpll_calc_max_lock_us(const struct wrpll_cfg *c)
  318. {
  319. return MAX_LOCK_US;
  320. }