omap-rng.c 14 KB

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  1. /*
  2. * omap-rng.c - RNG driver for TI OMAP CPU family
  3. *
  4. * Author: Deepak Saxena <[email protected]>
  5. *
  6. * Copyright 2005 (c) MontaVista Software, Inc.
  7. *
  8. * Mostly based on original driver:
  9. *
  10. * Copyright (C) 2005 Nokia Corporation
  11. * Author: Juha Yrjölä <[email protected]>
  12. *
  13. * This file is licensed under the terms of the GNU General Public
  14. * License version 2. This program is licensed "as is" without any
  15. * warranty of any kind, whether express or implied.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/init.h>
  19. #include <linux/random.h>
  20. #include <linux/err.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/hw_random.h>
  23. #include <linux/delay.h>
  24. #include <linux/kernel.h>
  25. #include <linux/slab.h>
  26. #include <linux/pm_runtime.h>
  27. #include <linux/of.h>
  28. #include <linux/of_device.h>
  29. #include <linux/of_address.h>
  30. #include <linux/interrupt.h>
  31. #include <linux/clk.h>
  32. #include <linux/io.h>
  33. #define RNG_REG_STATUS_RDY (1 << 0)
  34. #define RNG_REG_INTACK_RDY_MASK (1 << 0)
  35. #define RNG_REG_INTACK_SHUTDOWN_OFLO_MASK (1 << 1)
  36. #define RNG_SHUTDOWN_OFLO_MASK (1 << 1)
  37. #define RNG_CONTROL_STARTUP_CYCLES_SHIFT 16
  38. #define RNG_CONTROL_STARTUP_CYCLES_MASK (0xffff << 16)
  39. #define RNG_CONTROL_ENABLE_TRNG_SHIFT 10
  40. #define RNG_CONTROL_ENABLE_TRNG_MASK (1 << 10)
  41. #define RNG_CONFIG_MAX_REFIL_CYCLES_SHIFT 16
  42. #define RNG_CONFIG_MAX_REFIL_CYCLES_MASK (0xffff << 16)
  43. #define RNG_CONFIG_MIN_REFIL_CYCLES_SHIFT 0
  44. #define RNG_CONFIG_MIN_REFIL_CYCLES_MASK (0xff << 0)
  45. #define RNG_CONTROL_STARTUP_CYCLES 0xff
  46. #define RNG_CONFIG_MIN_REFIL_CYCLES 0x21
  47. #define RNG_CONFIG_MAX_REFIL_CYCLES 0x22
  48. #define RNG_ALARMCNT_ALARM_TH_SHIFT 0x0
  49. #define RNG_ALARMCNT_ALARM_TH_MASK (0xff << 0)
  50. #define RNG_ALARMCNT_SHUTDOWN_TH_SHIFT 16
  51. #define RNG_ALARMCNT_SHUTDOWN_TH_MASK (0x1f << 16)
  52. #define RNG_ALARM_THRESHOLD 0xff
  53. #define RNG_SHUTDOWN_THRESHOLD 0x4
  54. #define RNG_REG_FROENABLE_MASK 0xffffff
  55. #define RNG_REG_FRODETUNE_MASK 0xffffff
  56. #define OMAP2_RNG_OUTPUT_SIZE 0x4
  57. #define OMAP4_RNG_OUTPUT_SIZE 0x8
  58. #define EIP76_RNG_OUTPUT_SIZE 0x10
  59. /*
  60. * EIP76 RNG takes approx. 700us to produce 16 bytes of output data
  61. * as per testing results. And to account for the lack of udelay()'s
  62. * reliability, we keep the timeout as 1000us.
  63. */
  64. #define RNG_DATA_FILL_TIMEOUT 100
  65. enum {
  66. RNG_OUTPUT_0_REG = 0,
  67. RNG_OUTPUT_1_REG,
  68. RNG_OUTPUT_2_REG,
  69. RNG_OUTPUT_3_REG,
  70. RNG_STATUS_REG,
  71. RNG_INTMASK_REG,
  72. RNG_INTACK_REG,
  73. RNG_CONTROL_REG,
  74. RNG_CONFIG_REG,
  75. RNG_ALARMCNT_REG,
  76. RNG_FROENABLE_REG,
  77. RNG_FRODETUNE_REG,
  78. RNG_ALARMMASK_REG,
  79. RNG_ALARMSTOP_REG,
  80. RNG_REV_REG,
  81. RNG_SYSCONFIG_REG,
  82. };
  83. static const u16 reg_map_omap2[] = {
  84. [RNG_OUTPUT_0_REG] = 0x0,
  85. [RNG_STATUS_REG] = 0x4,
  86. [RNG_CONFIG_REG] = 0x28,
  87. [RNG_REV_REG] = 0x3c,
  88. [RNG_SYSCONFIG_REG] = 0x40,
  89. };
  90. static const u16 reg_map_omap4[] = {
  91. [RNG_OUTPUT_0_REG] = 0x0,
  92. [RNG_OUTPUT_1_REG] = 0x4,
  93. [RNG_STATUS_REG] = 0x8,
  94. [RNG_INTMASK_REG] = 0xc,
  95. [RNG_INTACK_REG] = 0x10,
  96. [RNG_CONTROL_REG] = 0x14,
  97. [RNG_CONFIG_REG] = 0x18,
  98. [RNG_ALARMCNT_REG] = 0x1c,
  99. [RNG_FROENABLE_REG] = 0x20,
  100. [RNG_FRODETUNE_REG] = 0x24,
  101. [RNG_ALARMMASK_REG] = 0x28,
  102. [RNG_ALARMSTOP_REG] = 0x2c,
  103. [RNG_REV_REG] = 0x1FE0,
  104. [RNG_SYSCONFIG_REG] = 0x1FE4,
  105. };
  106. static const u16 reg_map_eip76[] = {
  107. [RNG_OUTPUT_0_REG] = 0x0,
  108. [RNG_OUTPUT_1_REG] = 0x4,
  109. [RNG_OUTPUT_2_REG] = 0x8,
  110. [RNG_OUTPUT_3_REG] = 0xc,
  111. [RNG_STATUS_REG] = 0x10,
  112. [RNG_INTACK_REG] = 0x10,
  113. [RNG_CONTROL_REG] = 0x14,
  114. [RNG_CONFIG_REG] = 0x18,
  115. [RNG_ALARMCNT_REG] = 0x1c,
  116. [RNG_FROENABLE_REG] = 0x20,
  117. [RNG_FRODETUNE_REG] = 0x24,
  118. [RNG_ALARMMASK_REG] = 0x28,
  119. [RNG_ALARMSTOP_REG] = 0x2c,
  120. [RNG_REV_REG] = 0x7c,
  121. };
  122. struct omap_rng_dev;
  123. /**
  124. * struct omap_rng_pdata - RNG IP block-specific data
  125. * @regs: Pointer to the register offsets structure.
  126. * @data_size: No. of bytes in RNG output.
  127. * @data_present: Callback to determine if data is available.
  128. * @init: Callback for IP specific initialization sequence.
  129. * @cleanup: Callback for IP specific cleanup sequence.
  130. */
  131. struct omap_rng_pdata {
  132. u16 *regs;
  133. u32 data_size;
  134. u32 (*data_present)(struct omap_rng_dev *priv);
  135. int (*init)(struct omap_rng_dev *priv);
  136. void (*cleanup)(struct omap_rng_dev *priv);
  137. };
  138. struct omap_rng_dev {
  139. void __iomem *base;
  140. struct device *dev;
  141. const struct omap_rng_pdata *pdata;
  142. struct hwrng rng;
  143. struct clk *clk;
  144. struct clk *clk_reg;
  145. };
  146. static inline u32 omap_rng_read(struct omap_rng_dev *priv, u16 reg)
  147. {
  148. return __raw_readl(priv->base + priv->pdata->regs[reg]);
  149. }
  150. static inline void omap_rng_write(struct omap_rng_dev *priv, u16 reg,
  151. u32 val)
  152. {
  153. __raw_writel(val, priv->base + priv->pdata->regs[reg]);
  154. }
  155. static int omap_rng_do_read(struct hwrng *rng, void *data, size_t max,
  156. bool wait)
  157. {
  158. struct omap_rng_dev *priv;
  159. int i, present;
  160. priv = (struct omap_rng_dev *)rng->priv;
  161. if (max < priv->pdata->data_size)
  162. return 0;
  163. for (i = 0; i < RNG_DATA_FILL_TIMEOUT; i++) {
  164. present = priv->pdata->data_present(priv);
  165. if (present || !wait)
  166. break;
  167. udelay(10);
  168. }
  169. if (!present)
  170. return 0;
  171. memcpy_fromio(data, priv->base + priv->pdata->regs[RNG_OUTPUT_0_REG],
  172. priv->pdata->data_size);
  173. if (priv->pdata->regs[RNG_INTACK_REG])
  174. omap_rng_write(priv, RNG_INTACK_REG, RNG_REG_INTACK_RDY_MASK);
  175. return priv->pdata->data_size;
  176. }
  177. static int omap_rng_init(struct hwrng *rng)
  178. {
  179. struct omap_rng_dev *priv;
  180. priv = (struct omap_rng_dev *)rng->priv;
  181. return priv->pdata->init(priv);
  182. }
  183. static void omap_rng_cleanup(struct hwrng *rng)
  184. {
  185. struct omap_rng_dev *priv;
  186. priv = (struct omap_rng_dev *)rng->priv;
  187. priv->pdata->cleanup(priv);
  188. }
  189. static inline u32 omap2_rng_data_present(struct omap_rng_dev *priv)
  190. {
  191. return omap_rng_read(priv, RNG_STATUS_REG) ? 0 : 1;
  192. }
  193. static int omap2_rng_init(struct omap_rng_dev *priv)
  194. {
  195. omap_rng_write(priv, RNG_SYSCONFIG_REG, 0x1);
  196. return 0;
  197. }
  198. static void omap2_rng_cleanup(struct omap_rng_dev *priv)
  199. {
  200. omap_rng_write(priv, RNG_SYSCONFIG_REG, 0x0);
  201. }
  202. static struct omap_rng_pdata omap2_rng_pdata = {
  203. .regs = (u16 *)reg_map_omap2,
  204. .data_size = OMAP2_RNG_OUTPUT_SIZE,
  205. .data_present = omap2_rng_data_present,
  206. .init = omap2_rng_init,
  207. .cleanup = omap2_rng_cleanup,
  208. };
  209. static inline u32 omap4_rng_data_present(struct omap_rng_dev *priv)
  210. {
  211. return omap_rng_read(priv, RNG_STATUS_REG) & RNG_REG_STATUS_RDY;
  212. }
  213. static int eip76_rng_init(struct omap_rng_dev *priv)
  214. {
  215. u32 val;
  216. /* Return if RNG is already running. */
  217. if (omap_rng_read(priv, RNG_CONTROL_REG) & RNG_CONTROL_ENABLE_TRNG_MASK)
  218. return 0;
  219. /* Number of 512 bit blocks of raw Noise Source output data that must
  220. * be processed by either the Conditioning Function or the
  221. * SP 800-90 DRBG ‘BC_DF’ functionality to yield a ‘full entropy’
  222. * output value.
  223. */
  224. val = 0x5 << RNG_CONFIG_MIN_REFIL_CYCLES_SHIFT;
  225. /* Number of FRO samples that are XOR-ed together into one bit to be
  226. * shifted into the main shift register
  227. */
  228. val |= RNG_CONFIG_MAX_REFIL_CYCLES << RNG_CONFIG_MAX_REFIL_CYCLES_SHIFT;
  229. omap_rng_write(priv, RNG_CONFIG_REG, val);
  230. /* Enable all available FROs */
  231. omap_rng_write(priv, RNG_FRODETUNE_REG, 0x0);
  232. omap_rng_write(priv, RNG_FROENABLE_REG, RNG_REG_FROENABLE_MASK);
  233. /* Enable TRNG */
  234. val = RNG_CONTROL_ENABLE_TRNG_MASK;
  235. omap_rng_write(priv, RNG_CONTROL_REG, val);
  236. return 0;
  237. }
  238. static int omap4_rng_init(struct omap_rng_dev *priv)
  239. {
  240. u32 val;
  241. /* Return if RNG is already running. */
  242. if (omap_rng_read(priv, RNG_CONTROL_REG) & RNG_CONTROL_ENABLE_TRNG_MASK)
  243. return 0;
  244. val = RNG_CONFIG_MIN_REFIL_CYCLES << RNG_CONFIG_MIN_REFIL_CYCLES_SHIFT;
  245. val |= RNG_CONFIG_MAX_REFIL_CYCLES << RNG_CONFIG_MAX_REFIL_CYCLES_SHIFT;
  246. omap_rng_write(priv, RNG_CONFIG_REG, val);
  247. omap_rng_write(priv, RNG_FRODETUNE_REG, 0x0);
  248. omap_rng_write(priv, RNG_FROENABLE_REG, RNG_REG_FROENABLE_MASK);
  249. val = RNG_ALARM_THRESHOLD << RNG_ALARMCNT_ALARM_TH_SHIFT;
  250. val |= RNG_SHUTDOWN_THRESHOLD << RNG_ALARMCNT_SHUTDOWN_TH_SHIFT;
  251. omap_rng_write(priv, RNG_ALARMCNT_REG, val);
  252. val = RNG_CONTROL_STARTUP_CYCLES << RNG_CONTROL_STARTUP_CYCLES_SHIFT;
  253. val |= RNG_CONTROL_ENABLE_TRNG_MASK;
  254. omap_rng_write(priv, RNG_CONTROL_REG, val);
  255. return 0;
  256. }
  257. static void omap4_rng_cleanup(struct omap_rng_dev *priv)
  258. {
  259. int val;
  260. val = omap_rng_read(priv, RNG_CONTROL_REG);
  261. val &= ~RNG_CONTROL_ENABLE_TRNG_MASK;
  262. omap_rng_write(priv, RNG_CONTROL_REG, val);
  263. }
  264. static irqreturn_t omap4_rng_irq(int irq, void *dev_id)
  265. {
  266. struct omap_rng_dev *priv = dev_id;
  267. u32 fro_detune, fro_enable;
  268. /*
  269. * Interrupt raised by a fro shutdown threshold, do the following:
  270. * 1. Clear the alarm events.
  271. * 2. De tune the FROs which are shutdown.
  272. * 3. Re enable the shutdown FROs.
  273. */
  274. omap_rng_write(priv, RNG_ALARMMASK_REG, 0x0);
  275. omap_rng_write(priv, RNG_ALARMSTOP_REG, 0x0);
  276. fro_enable = omap_rng_read(priv, RNG_FROENABLE_REG);
  277. fro_detune = ~fro_enable & RNG_REG_FRODETUNE_MASK;
  278. fro_detune = fro_detune | omap_rng_read(priv, RNG_FRODETUNE_REG);
  279. fro_enable = RNG_REG_FROENABLE_MASK;
  280. omap_rng_write(priv, RNG_FRODETUNE_REG, fro_detune);
  281. omap_rng_write(priv, RNG_FROENABLE_REG, fro_enable);
  282. omap_rng_write(priv, RNG_INTACK_REG, RNG_REG_INTACK_SHUTDOWN_OFLO_MASK);
  283. return IRQ_HANDLED;
  284. }
  285. static struct omap_rng_pdata omap4_rng_pdata = {
  286. .regs = (u16 *)reg_map_omap4,
  287. .data_size = OMAP4_RNG_OUTPUT_SIZE,
  288. .data_present = omap4_rng_data_present,
  289. .init = omap4_rng_init,
  290. .cleanup = omap4_rng_cleanup,
  291. };
  292. static struct omap_rng_pdata eip76_rng_pdata = {
  293. .regs = (u16 *)reg_map_eip76,
  294. .data_size = EIP76_RNG_OUTPUT_SIZE,
  295. .data_present = omap4_rng_data_present,
  296. .init = eip76_rng_init,
  297. .cleanup = omap4_rng_cleanup,
  298. };
  299. static const struct of_device_id omap_rng_of_match[] __maybe_unused = {
  300. {
  301. .compatible = "ti,omap2-rng",
  302. .data = &omap2_rng_pdata,
  303. },
  304. {
  305. .compatible = "ti,omap4-rng",
  306. .data = &omap4_rng_pdata,
  307. },
  308. {
  309. .compatible = "inside-secure,safexcel-eip76",
  310. .data = &eip76_rng_pdata,
  311. },
  312. {},
  313. };
  314. MODULE_DEVICE_TABLE(of, omap_rng_of_match);
  315. static int of_get_omap_rng_device_details(struct omap_rng_dev *priv,
  316. struct platform_device *pdev)
  317. {
  318. struct device *dev = &pdev->dev;
  319. int irq, err;
  320. priv->pdata = of_device_get_match_data(dev);
  321. if (!priv->pdata)
  322. return -ENODEV;
  323. if (of_device_is_compatible(dev->of_node, "ti,omap4-rng") ||
  324. of_device_is_compatible(dev->of_node, "inside-secure,safexcel-eip76")) {
  325. irq = platform_get_irq(pdev, 0);
  326. if (irq < 0)
  327. return irq;
  328. err = devm_request_irq(dev, irq, omap4_rng_irq,
  329. IRQF_TRIGGER_NONE, dev_name(dev), priv);
  330. if (err) {
  331. dev_err(dev, "unable to request irq %d, err = %d\n",
  332. irq, err);
  333. return err;
  334. }
  335. /*
  336. * On OMAP4, enabling the shutdown_oflo interrupt is
  337. * done in the interrupt mask register. There is no
  338. * such register on EIP76, and it's enabled by the
  339. * same bit in the control register
  340. */
  341. if (priv->pdata->regs[RNG_INTMASK_REG])
  342. omap_rng_write(priv, RNG_INTMASK_REG,
  343. RNG_SHUTDOWN_OFLO_MASK);
  344. else
  345. omap_rng_write(priv, RNG_CONTROL_REG,
  346. RNG_SHUTDOWN_OFLO_MASK);
  347. }
  348. return 0;
  349. }
  350. static int get_omap_rng_device_details(struct omap_rng_dev *omap_rng)
  351. {
  352. /* Only OMAP2/3 can be non-DT */
  353. omap_rng->pdata = &omap2_rng_pdata;
  354. return 0;
  355. }
  356. static int omap_rng_probe(struct platform_device *pdev)
  357. {
  358. struct omap_rng_dev *priv;
  359. struct device *dev = &pdev->dev;
  360. int ret;
  361. priv = devm_kzalloc(dev, sizeof(struct omap_rng_dev), GFP_KERNEL);
  362. if (!priv)
  363. return -ENOMEM;
  364. priv->rng.read = omap_rng_do_read;
  365. priv->rng.init = omap_rng_init;
  366. priv->rng.cleanup = omap_rng_cleanup;
  367. priv->rng.quality = 900;
  368. priv->rng.priv = (unsigned long)priv;
  369. platform_set_drvdata(pdev, priv);
  370. priv->dev = dev;
  371. priv->base = devm_platform_ioremap_resource(pdev, 0);
  372. if (IS_ERR(priv->base)) {
  373. ret = PTR_ERR(priv->base);
  374. goto err_ioremap;
  375. }
  376. priv->rng.name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
  377. if (!priv->rng.name) {
  378. ret = -ENOMEM;
  379. goto err_ioremap;
  380. }
  381. pm_runtime_enable(&pdev->dev);
  382. ret = pm_runtime_resume_and_get(&pdev->dev);
  383. if (ret < 0) {
  384. dev_err(&pdev->dev, "Failed to runtime_get device: %d\n", ret);
  385. goto err_ioremap;
  386. }
  387. priv->clk = devm_clk_get(&pdev->dev, NULL);
  388. if (PTR_ERR(priv->clk) == -EPROBE_DEFER)
  389. return -EPROBE_DEFER;
  390. if (!IS_ERR(priv->clk)) {
  391. ret = clk_prepare_enable(priv->clk);
  392. if (ret) {
  393. dev_err(&pdev->dev,
  394. "Unable to enable the clk: %d\n", ret);
  395. goto err_register;
  396. }
  397. }
  398. priv->clk_reg = devm_clk_get(&pdev->dev, "reg");
  399. if (PTR_ERR(priv->clk_reg) == -EPROBE_DEFER)
  400. return -EPROBE_DEFER;
  401. if (!IS_ERR(priv->clk_reg)) {
  402. ret = clk_prepare_enable(priv->clk_reg);
  403. if (ret) {
  404. dev_err(&pdev->dev,
  405. "Unable to enable the register clk: %d\n",
  406. ret);
  407. goto err_register;
  408. }
  409. }
  410. ret = (dev->of_node) ? of_get_omap_rng_device_details(priv, pdev) :
  411. get_omap_rng_device_details(priv);
  412. if (ret)
  413. goto err_register;
  414. ret = devm_hwrng_register(&pdev->dev, &priv->rng);
  415. if (ret)
  416. goto err_register;
  417. dev_info(&pdev->dev, "Random Number Generator ver. %02x\n",
  418. omap_rng_read(priv, RNG_REV_REG));
  419. return 0;
  420. err_register:
  421. priv->base = NULL;
  422. pm_runtime_put_sync(&pdev->dev);
  423. pm_runtime_disable(&pdev->dev);
  424. clk_disable_unprepare(priv->clk_reg);
  425. clk_disable_unprepare(priv->clk);
  426. err_ioremap:
  427. dev_err(dev, "initialization failed.\n");
  428. return ret;
  429. }
  430. static int omap_rng_remove(struct platform_device *pdev)
  431. {
  432. struct omap_rng_dev *priv = platform_get_drvdata(pdev);
  433. priv->pdata->cleanup(priv);
  434. pm_runtime_put_sync(&pdev->dev);
  435. pm_runtime_disable(&pdev->dev);
  436. clk_disable_unprepare(priv->clk);
  437. clk_disable_unprepare(priv->clk_reg);
  438. return 0;
  439. }
  440. static int __maybe_unused omap_rng_suspend(struct device *dev)
  441. {
  442. struct omap_rng_dev *priv = dev_get_drvdata(dev);
  443. priv->pdata->cleanup(priv);
  444. pm_runtime_put_sync(dev);
  445. return 0;
  446. }
  447. static int __maybe_unused omap_rng_resume(struct device *dev)
  448. {
  449. struct omap_rng_dev *priv = dev_get_drvdata(dev);
  450. int ret;
  451. ret = pm_runtime_resume_and_get(dev);
  452. if (ret < 0) {
  453. dev_err(dev, "Failed to runtime_get device: %d\n", ret);
  454. return ret;
  455. }
  456. priv->pdata->init(priv);
  457. return 0;
  458. }
  459. static SIMPLE_DEV_PM_OPS(omap_rng_pm, omap_rng_suspend, omap_rng_resume);
  460. static struct platform_driver omap_rng_driver = {
  461. .driver = {
  462. .name = "omap_rng",
  463. .pm = &omap_rng_pm,
  464. .of_match_table = of_match_ptr(omap_rng_of_match),
  465. },
  466. .probe = omap_rng_probe,
  467. .remove = omap_rng_remove,
  468. };
  469. module_platform_driver(omap_rng_driver);
  470. MODULE_ALIAS("platform:omap_rng");
  471. MODULE_AUTHOR("Deepak Saxena (and others)");
  472. MODULE_LICENSE("GPL");