mpfs-rng.c 2.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Microchip PolarFire SoC (MPFS) hardware random driver
  4. *
  5. * Copyright (c) 2020-2022 Microchip Corporation. All rights reserved.
  6. *
  7. * Author: Conor Dooley <[email protected]>
  8. */
  9. #include <linux/module.h>
  10. #include <linux/hw_random.h>
  11. #include <linux/platform_device.h>
  12. #include <soc/microchip/mpfs.h>
  13. #define CMD_OPCODE 0x21
  14. #define CMD_DATA_SIZE 0U
  15. #define CMD_DATA NULL
  16. #define MBOX_OFFSET 0U
  17. #define RESP_OFFSET 0U
  18. #define RNG_RESP_BYTES 32U
  19. struct mpfs_rng {
  20. struct mpfs_sys_controller *sys_controller;
  21. struct hwrng rng;
  22. };
  23. static int mpfs_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
  24. {
  25. struct mpfs_rng *rng_priv = container_of(rng, struct mpfs_rng, rng);
  26. u32 response_msg[RNG_RESP_BYTES / sizeof(u32)];
  27. unsigned int count = 0, copy_size_bytes;
  28. int ret;
  29. struct mpfs_mss_response response = {
  30. .resp_status = 0U,
  31. .resp_msg = (u32 *)response_msg,
  32. .resp_size = RNG_RESP_BYTES
  33. };
  34. struct mpfs_mss_msg msg = {
  35. .cmd_opcode = CMD_OPCODE,
  36. .cmd_data_size = CMD_DATA_SIZE,
  37. .response = &response,
  38. .cmd_data = CMD_DATA,
  39. .mbox_offset = MBOX_OFFSET,
  40. .resp_offset = RESP_OFFSET
  41. };
  42. while (count < max) {
  43. ret = mpfs_blocking_transaction(rng_priv->sys_controller, &msg);
  44. if (ret)
  45. return ret;
  46. copy_size_bytes = max - count > RNG_RESP_BYTES ? RNG_RESP_BYTES : max - count;
  47. memcpy(buf + count, response_msg, copy_size_bytes);
  48. count += copy_size_bytes;
  49. if (!wait)
  50. break;
  51. }
  52. return count;
  53. }
  54. static int mpfs_rng_probe(struct platform_device *pdev)
  55. {
  56. struct device *dev = &pdev->dev;
  57. struct mpfs_rng *rng_priv;
  58. int ret;
  59. rng_priv = devm_kzalloc(dev, sizeof(*rng_priv), GFP_KERNEL);
  60. if (!rng_priv)
  61. return -ENOMEM;
  62. rng_priv->sys_controller = mpfs_sys_controller_get(&pdev->dev);
  63. if (IS_ERR(rng_priv->sys_controller))
  64. return dev_err_probe(dev, PTR_ERR(rng_priv->sys_controller),
  65. "Failed to register system controller hwrng sub device\n");
  66. rng_priv->rng.read = mpfs_rng_read;
  67. rng_priv->rng.name = pdev->name;
  68. rng_priv->rng.quality = 1024;
  69. platform_set_drvdata(pdev, rng_priv);
  70. ret = devm_hwrng_register(&pdev->dev, &rng_priv->rng);
  71. if (ret)
  72. return dev_err_probe(&pdev->dev, ret, "Failed to register MPFS hwrng\n");
  73. dev_info(&pdev->dev, "Registered MPFS hwrng\n");
  74. return 0;
  75. }
  76. static struct platform_driver mpfs_rng_driver = {
  77. .driver = {
  78. .name = "mpfs-rng",
  79. },
  80. .probe = mpfs_rng_probe,
  81. };
  82. module_platform_driver(mpfs_rng_driver);
  83. MODULE_LICENSE("GPL");
  84. MODULE_AUTHOR("Conor Dooley <[email protected]>");
  85. MODULE_DESCRIPTION("PolarFire SoC (MPFS) hardware random driver");