iproc-rng200.c 6.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2015 Broadcom Corporation
  4. *
  5. */
  6. /*
  7. * DESCRIPTION: The Broadcom iProc RNG200 Driver
  8. */
  9. #include <linux/hw_random.h>
  10. #include <linux/init.h>
  11. #include <linux/io.h>
  12. #include <linux/kernel.h>
  13. #include <linux/module.h>
  14. #include <linux/of_address.h>
  15. #include <linux/of_platform.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/delay.h>
  18. /* Registers */
  19. #define RNG_CTRL_OFFSET 0x00
  20. #define RNG_CTRL_RNG_RBGEN_MASK 0x00001FFF
  21. #define RNG_CTRL_RNG_RBGEN_ENABLE 0x00000001
  22. #define RNG_SOFT_RESET_OFFSET 0x04
  23. #define RNG_SOFT_RESET 0x00000001
  24. #define RBG_SOFT_RESET_OFFSET 0x08
  25. #define RBG_SOFT_RESET 0x00000001
  26. #define RNG_INT_STATUS_OFFSET 0x18
  27. #define RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK 0x80000000
  28. #define RNG_INT_STATUS_STARTUP_TRANSITIONS_MET_IRQ_MASK 0x00020000
  29. #define RNG_INT_STATUS_NIST_FAIL_IRQ_MASK 0x00000020
  30. #define RNG_INT_STATUS_TOTAL_BITS_COUNT_IRQ_MASK 0x00000001
  31. #define RNG_FIFO_DATA_OFFSET 0x20
  32. #define RNG_FIFO_COUNT_OFFSET 0x24
  33. #define RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK 0x000000FF
  34. struct iproc_rng200_dev {
  35. struct hwrng rng;
  36. void __iomem *base;
  37. };
  38. #define to_rng_priv(rng) container_of(rng, struct iproc_rng200_dev, rng)
  39. static void iproc_rng200_enable_set(void __iomem *rng_base, bool enable)
  40. {
  41. u32 val;
  42. val = ioread32(rng_base + RNG_CTRL_OFFSET);
  43. val &= ~RNG_CTRL_RNG_RBGEN_MASK;
  44. if (enable)
  45. val |= RNG_CTRL_RNG_RBGEN_ENABLE;
  46. iowrite32(val, rng_base + RNG_CTRL_OFFSET);
  47. }
  48. static void iproc_rng200_restart(void __iomem *rng_base)
  49. {
  50. uint32_t val;
  51. iproc_rng200_enable_set(rng_base, false);
  52. /* Clear all interrupt status */
  53. iowrite32(0xFFFFFFFFUL, rng_base + RNG_INT_STATUS_OFFSET);
  54. /* Reset RNG and RBG */
  55. val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET);
  56. val |= RBG_SOFT_RESET;
  57. iowrite32(val, rng_base + RBG_SOFT_RESET_OFFSET);
  58. val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET);
  59. val |= RNG_SOFT_RESET;
  60. iowrite32(val, rng_base + RNG_SOFT_RESET_OFFSET);
  61. val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET);
  62. val &= ~RNG_SOFT_RESET;
  63. iowrite32(val, rng_base + RNG_SOFT_RESET_OFFSET);
  64. val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET);
  65. val &= ~RBG_SOFT_RESET;
  66. iowrite32(val, rng_base + RBG_SOFT_RESET_OFFSET);
  67. iproc_rng200_enable_set(rng_base, true);
  68. }
  69. static int iproc_rng200_read(struct hwrng *rng, void *buf, size_t max,
  70. bool wait)
  71. {
  72. struct iproc_rng200_dev *priv = to_rng_priv(rng);
  73. uint32_t num_remaining = max;
  74. uint32_t status;
  75. #define MAX_RESETS_PER_READ 1
  76. uint32_t num_resets = 0;
  77. #define MAX_IDLE_TIME (1 * HZ)
  78. unsigned long idle_endtime = jiffies + MAX_IDLE_TIME;
  79. while ((num_remaining > 0) && time_before(jiffies, idle_endtime)) {
  80. /* Is RNG sane? If not, reset it. */
  81. status = ioread32(priv->base + RNG_INT_STATUS_OFFSET);
  82. if ((status & (RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK |
  83. RNG_INT_STATUS_NIST_FAIL_IRQ_MASK)) != 0) {
  84. if (num_resets >= MAX_RESETS_PER_READ)
  85. return max - num_remaining;
  86. iproc_rng200_restart(priv->base);
  87. num_resets++;
  88. }
  89. /* Are there any random numbers available? */
  90. if ((ioread32(priv->base + RNG_FIFO_COUNT_OFFSET) &
  91. RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK) > 0) {
  92. if (num_remaining >= sizeof(uint32_t)) {
  93. /* Buffer has room to store entire word */
  94. *(uint32_t *)buf = ioread32(priv->base +
  95. RNG_FIFO_DATA_OFFSET);
  96. buf += sizeof(uint32_t);
  97. num_remaining -= sizeof(uint32_t);
  98. } else {
  99. /* Buffer can only store partial word */
  100. uint32_t rnd_number = ioread32(priv->base +
  101. RNG_FIFO_DATA_OFFSET);
  102. memcpy(buf, &rnd_number, num_remaining);
  103. buf += num_remaining;
  104. num_remaining = 0;
  105. }
  106. /* Reset the IDLE timeout */
  107. idle_endtime = jiffies + MAX_IDLE_TIME;
  108. } else {
  109. if (!wait)
  110. /* Cannot wait, return immediately */
  111. return max - num_remaining;
  112. /* Can wait, give others chance to run */
  113. usleep_range(min(num_remaining * 10, 500U), 500);
  114. }
  115. }
  116. return max - num_remaining;
  117. }
  118. static int iproc_rng200_init(struct hwrng *rng)
  119. {
  120. struct iproc_rng200_dev *priv = to_rng_priv(rng);
  121. iproc_rng200_enable_set(priv->base, true);
  122. return 0;
  123. }
  124. static void iproc_rng200_cleanup(struct hwrng *rng)
  125. {
  126. struct iproc_rng200_dev *priv = to_rng_priv(rng);
  127. iproc_rng200_enable_set(priv->base, false);
  128. }
  129. static int iproc_rng200_probe(struct platform_device *pdev)
  130. {
  131. struct iproc_rng200_dev *priv;
  132. struct device *dev = &pdev->dev;
  133. int ret;
  134. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  135. if (!priv)
  136. return -ENOMEM;
  137. /* Map peripheral */
  138. priv->base = devm_platform_ioremap_resource(pdev, 0);
  139. if (IS_ERR(priv->base)) {
  140. dev_err(dev, "failed to remap rng regs\n");
  141. return PTR_ERR(priv->base);
  142. }
  143. dev_set_drvdata(dev, priv);
  144. priv->rng.name = "iproc-rng200";
  145. priv->rng.read = iproc_rng200_read;
  146. priv->rng.init = iproc_rng200_init;
  147. priv->rng.cleanup = iproc_rng200_cleanup;
  148. /* Register driver */
  149. ret = devm_hwrng_register(dev, &priv->rng);
  150. if (ret) {
  151. dev_err(dev, "hwrng registration failed\n");
  152. return ret;
  153. }
  154. dev_info(dev, "hwrng registered\n");
  155. return 0;
  156. }
  157. static int __maybe_unused iproc_rng200_suspend(struct device *dev)
  158. {
  159. struct iproc_rng200_dev *priv = dev_get_drvdata(dev);
  160. iproc_rng200_cleanup(&priv->rng);
  161. return 0;
  162. }
  163. static int __maybe_unused iproc_rng200_resume(struct device *dev)
  164. {
  165. struct iproc_rng200_dev *priv = dev_get_drvdata(dev);
  166. iproc_rng200_init(&priv->rng);
  167. return 0;
  168. }
  169. static const struct dev_pm_ops iproc_rng200_pm_ops = {
  170. SET_SYSTEM_SLEEP_PM_OPS(iproc_rng200_suspend, iproc_rng200_resume)
  171. };
  172. static const struct of_device_id iproc_rng200_of_match[] = {
  173. { .compatible = "brcm,bcm2711-rng200", },
  174. { .compatible = "brcm,bcm7211-rng200", },
  175. { .compatible = "brcm,bcm7278-rng200", },
  176. { .compatible = "brcm,iproc-rng200", },
  177. {},
  178. };
  179. MODULE_DEVICE_TABLE(of, iproc_rng200_of_match);
  180. static struct platform_driver iproc_rng200_driver = {
  181. .driver = {
  182. .name = "iproc-rng200",
  183. .of_match_table = iproc_rng200_of_match,
  184. .pm = &iproc_rng200_pm_ops,
  185. },
  186. .probe = iproc_rng200_probe,
  187. };
  188. module_platform_driver(iproc_rng200_driver);
  189. MODULE_AUTHOR("Broadcom");
  190. MODULE_DESCRIPTION("iProc RNG200 Random Number Generator driver");
  191. MODULE_LICENSE("GPL v2");