generic-chip.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Library implementing the most common irq chip callback functions
  4. *
  5. * Copyright (C) 2011, Thomas Gleixner
  6. */
  7. #include <linux/io.h>
  8. #include <linux/irq.h>
  9. #include <linux/slab.h>
  10. #include <linux/export.h>
  11. #include <linux/irqdomain.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/kernel_stat.h>
  14. #include <linux/syscore_ops.h>
  15. #include "internals.h"
  16. static LIST_HEAD(gc_list);
  17. static DEFINE_RAW_SPINLOCK(gc_lock);
  18. /**
  19. * irq_gc_noop - NOOP function
  20. * @d: irq_data
  21. */
  22. void irq_gc_noop(struct irq_data *d)
  23. {
  24. }
  25. EXPORT_SYMBOL_GPL(irq_gc_noop);
  26. /**
  27. * irq_gc_mask_disable_reg - Mask chip via disable register
  28. * @d: irq_data
  29. *
  30. * Chip has separate enable/disable registers instead of a single mask
  31. * register.
  32. */
  33. void irq_gc_mask_disable_reg(struct irq_data *d)
  34. {
  35. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  36. struct irq_chip_type *ct = irq_data_get_chip_type(d);
  37. u32 mask = d->mask;
  38. irq_gc_lock(gc);
  39. irq_reg_writel(gc, mask, ct->regs.disable);
  40. *ct->mask_cache &= ~mask;
  41. irq_gc_unlock(gc);
  42. }
  43. EXPORT_SYMBOL_GPL(irq_gc_mask_disable_reg);
  44. /**
  45. * irq_gc_mask_set_bit - Mask chip via setting bit in mask register
  46. * @d: irq_data
  47. *
  48. * Chip has a single mask register. Values of this register are cached
  49. * and protected by gc->lock
  50. */
  51. void irq_gc_mask_set_bit(struct irq_data *d)
  52. {
  53. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  54. struct irq_chip_type *ct = irq_data_get_chip_type(d);
  55. u32 mask = d->mask;
  56. irq_gc_lock(gc);
  57. *ct->mask_cache |= mask;
  58. irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
  59. irq_gc_unlock(gc);
  60. }
  61. EXPORT_SYMBOL_GPL(irq_gc_mask_set_bit);
  62. /**
  63. * irq_gc_mask_clr_bit - Mask chip via clearing bit in mask register
  64. * @d: irq_data
  65. *
  66. * Chip has a single mask register. Values of this register are cached
  67. * and protected by gc->lock
  68. */
  69. void irq_gc_mask_clr_bit(struct irq_data *d)
  70. {
  71. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  72. struct irq_chip_type *ct = irq_data_get_chip_type(d);
  73. u32 mask = d->mask;
  74. irq_gc_lock(gc);
  75. *ct->mask_cache &= ~mask;
  76. irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
  77. irq_gc_unlock(gc);
  78. }
  79. EXPORT_SYMBOL_GPL(irq_gc_mask_clr_bit);
  80. /**
  81. * irq_gc_unmask_enable_reg - Unmask chip via enable register
  82. * @d: irq_data
  83. *
  84. * Chip has separate enable/disable registers instead of a single mask
  85. * register.
  86. */
  87. void irq_gc_unmask_enable_reg(struct irq_data *d)
  88. {
  89. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  90. struct irq_chip_type *ct = irq_data_get_chip_type(d);
  91. u32 mask = d->mask;
  92. irq_gc_lock(gc);
  93. irq_reg_writel(gc, mask, ct->regs.enable);
  94. *ct->mask_cache |= mask;
  95. irq_gc_unlock(gc);
  96. }
  97. EXPORT_SYMBOL_GPL(irq_gc_unmask_enable_reg);
  98. /**
  99. * irq_gc_ack_set_bit - Ack pending interrupt via setting bit
  100. * @d: irq_data
  101. */
  102. void irq_gc_ack_set_bit(struct irq_data *d)
  103. {
  104. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  105. struct irq_chip_type *ct = irq_data_get_chip_type(d);
  106. u32 mask = d->mask;
  107. irq_gc_lock(gc);
  108. irq_reg_writel(gc, mask, ct->regs.ack);
  109. irq_gc_unlock(gc);
  110. }
  111. EXPORT_SYMBOL_GPL(irq_gc_ack_set_bit);
  112. /**
  113. * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
  114. * @d: irq_data
  115. */
  116. void irq_gc_ack_clr_bit(struct irq_data *d)
  117. {
  118. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  119. struct irq_chip_type *ct = irq_data_get_chip_type(d);
  120. u32 mask = ~d->mask;
  121. irq_gc_lock(gc);
  122. irq_reg_writel(gc, mask, ct->regs.ack);
  123. irq_gc_unlock(gc);
  124. }
  125. /**
  126. * irq_gc_mask_disable_and_ack_set - Mask and ack pending interrupt
  127. * @d: irq_data
  128. *
  129. * This generic implementation of the irq_mask_ack method is for chips
  130. * with separate enable/disable registers instead of a single mask
  131. * register and where a pending interrupt is acknowledged by setting a
  132. * bit.
  133. *
  134. * Note: This is the only permutation currently used. Similar generic
  135. * functions should be added here if other permutations are required.
  136. */
  137. void irq_gc_mask_disable_and_ack_set(struct irq_data *d)
  138. {
  139. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  140. struct irq_chip_type *ct = irq_data_get_chip_type(d);
  141. u32 mask = d->mask;
  142. irq_gc_lock(gc);
  143. irq_reg_writel(gc, mask, ct->regs.disable);
  144. *ct->mask_cache &= ~mask;
  145. irq_reg_writel(gc, mask, ct->regs.ack);
  146. irq_gc_unlock(gc);
  147. }
  148. /**
  149. * irq_gc_eoi - EOI interrupt
  150. * @d: irq_data
  151. */
  152. void irq_gc_eoi(struct irq_data *d)
  153. {
  154. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  155. struct irq_chip_type *ct = irq_data_get_chip_type(d);
  156. u32 mask = d->mask;
  157. irq_gc_lock(gc);
  158. irq_reg_writel(gc, mask, ct->regs.eoi);
  159. irq_gc_unlock(gc);
  160. }
  161. /**
  162. * irq_gc_set_wake - Set/clr wake bit for an interrupt
  163. * @d: irq_data
  164. * @on: Indicates whether the wake bit should be set or cleared
  165. *
  166. * For chips where the wake from suspend functionality is not
  167. * configured in a separate register and the wakeup active state is
  168. * just stored in a bitmask.
  169. */
  170. int irq_gc_set_wake(struct irq_data *d, unsigned int on)
  171. {
  172. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  173. u32 mask = d->mask;
  174. if (!(mask & gc->wake_enabled))
  175. return -EINVAL;
  176. irq_gc_lock(gc);
  177. if (on)
  178. gc->wake_active |= mask;
  179. else
  180. gc->wake_active &= ~mask;
  181. irq_gc_unlock(gc);
  182. return 0;
  183. }
  184. EXPORT_SYMBOL_GPL(irq_gc_set_wake);
  185. static u32 irq_readl_be(void __iomem *addr)
  186. {
  187. return ioread32be(addr);
  188. }
  189. static void irq_writel_be(u32 val, void __iomem *addr)
  190. {
  191. iowrite32be(val, addr);
  192. }
  193. void irq_init_generic_chip(struct irq_chip_generic *gc, const char *name,
  194. int num_ct, unsigned int irq_base,
  195. void __iomem *reg_base, irq_flow_handler_t handler)
  196. {
  197. raw_spin_lock_init(&gc->lock);
  198. gc->num_ct = num_ct;
  199. gc->irq_base = irq_base;
  200. gc->reg_base = reg_base;
  201. gc->chip_types->chip.name = name;
  202. gc->chip_types->handler = handler;
  203. }
  204. /**
  205. * irq_alloc_generic_chip - Allocate a generic chip and initialize it
  206. * @name: Name of the irq chip
  207. * @num_ct: Number of irq_chip_type instances associated with this
  208. * @irq_base: Interrupt base nr for this chip
  209. * @reg_base: Register base address (virtual)
  210. * @handler: Default flow handler associated with this chip
  211. *
  212. * Returns an initialized irq_chip_generic structure. The chip defaults
  213. * to the primary (index 0) irq_chip_type and @handler
  214. */
  215. struct irq_chip_generic *
  216. irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base,
  217. void __iomem *reg_base, irq_flow_handler_t handler)
  218. {
  219. struct irq_chip_generic *gc;
  220. gc = kzalloc(struct_size(gc, chip_types, num_ct), GFP_KERNEL);
  221. if (gc) {
  222. irq_init_generic_chip(gc, name, num_ct, irq_base, reg_base,
  223. handler);
  224. }
  225. return gc;
  226. }
  227. EXPORT_SYMBOL_GPL(irq_alloc_generic_chip);
  228. static void
  229. irq_gc_init_mask_cache(struct irq_chip_generic *gc, enum irq_gc_flags flags)
  230. {
  231. struct irq_chip_type *ct = gc->chip_types;
  232. u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask;
  233. int i;
  234. for (i = 0; i < gc->num_ct; i++) {
  235. if (flags & IRQ_GC_MASK_CACHE_PER_TYPE) {
  236. mskptr = &ct[i].mask_cache_priv;
  237. mskreg = ct[i].regs.mask;
  238. }
  239. ct[i].mask_cache = mskptr;
  240. if (flags & IRQ_GC_INIT_MASK_CACHE)
  241. *mskptr = irq_reg_readl(gc, mskreg);
  242. }
  243. }
  244. /**
  245. * __irq_alloc_domain_generic_chips - Allocate generic chips for an irq domain
  246. * @d: irq domain for which to allocate chips
  247. * @irqs_per_chip: Number of interrupts each chip handles (max 32)
  248. * @num_ct: Number of irq_chip_type instances associated with this
  249. * @name: Name of the irq chip
  250. * @handler: Default flow handler associated with these chips
  251. * @clr: IRQ_* bits to clear in the mapping function
  252. * @set: IRQ_* bits to set in the mapping function
  253. * @gcflags: Generic chip specific setup flags
  254. */
  255. int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
  256. int num_ct, const char *name,
  257. irq_flow_handler_t handler,
  258. unsigned int clr, unsigned int set,
  259. enum irq_gc_flags gcflags)
  260. {
  261. struct irq_domain_chip_generic *dgc;
  262. struct irq_chip_generic *gc;
  263. unsigned long flags;
  264. int numchips, i;
  265. size_t dgc_sz;
  266. size_t gc_sz;
  267. size_t sz;
  268. void *tmp;
  269. if (d->gc)
  270. return -EBUSY;
  271. numchips = DIV_ROUND_UP(d->revmap_size, irqs_per_chip);
  272. if (!numchips)
  273. return -EINVAL;
  274. /* Allocate a pointer, generic chip and chiptypes for each chip */
  275. gc_sz = struct_size(gc, chip_types, num_ct);
  276. dgc_sz = struct_size(dgc, gc, numchips);
  277. sz = dgc_sz + numchips * gc_sz;
  278. tmp = dgc = kzalloc(sz, GFP_KERNEL);
  279. if (!dgc)
  280. return -ENOMEM;
  281. dgc->irqs_per_chip = irqs_per_chip;
  282. dgc->num_chips = numchips;
  283. dgc->irq_flags_to_set = set;
  284. dgc->irq_flags_to_clear = clr;
  285. dgc->gc_flags = gcflags;
  286. d->gc = dgc;
  287. /* Calc pointer to the first generic chip */
  288. tmp += dgc_sz;
  289. for (i = 0; i < numchips; i++) {
  290. /* Store the pointer to the generic chip */
  291. dgc->gc[i] = gc = tmp;
  292. irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip,
  293. NULL, handler);
  294. gc->domain = d;
  295. if (gcflags & IRQ_GC_BE_IO) {
  296. gc->reg_readl = &irq_readl_be;
  297. gc->reg_writel = &irq_writel_be;
  298. }
  299. raw_spin_lock_irqsave(&gc_lock, flags);
  300. list_add_tail(&gc->list, &gc_list);
  301. raw_spin_unlock_irqrestore(&gc_lock, flags);
  302. /* Calc pointer to the next generic chip */
  303. tmp += gc_sz;
  304. }
  305. return 0;
  306. }
  307. EXPORT_SYMBOL_GPL(__irq_alloc_domain_generic_chips);
  308. static struct irq_chip_generic *
  309. __irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
  310. {
  311. struct irq_domain_chip_generic *dgc = d->gc;
  312. int idx;
  313. if (!dgc)
  314. return ERR_PTR(-ENODEV);
  315. idx = hw_irq / dgc->irqs_per_chip;
  316. if (idx >= dgc->num_chips)
  317. return ERR_PTR(-EINVAL);
  318. return dgc->gc[idx];
  319. }
  320. /**
  321. * irq_get_domain_generic_chip - Get a pointer to the generic chip of a hw_irq
  322. * @d: irq domain pointer
  323. * @hw_irq: Hardware interrupt number
  324. */
  325. struct irq_chip_generic *
  326. irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
  327. {
  328. struct irq_chip_generic *gc = __irq_get_domain_generic_chip(d, hw_irq);
  329. return !IS_ERR(gc) ? gc : NULL;
  330. }
  331. EXPORT_SYMBOL_GPL(irq_get_domain_generic_chip);
  332. /*
  333. * Separate lockdep classes for interrupt chip which can nest irq_desc
  334. * lock and request mutex.
  335. */
  336. static struct lock_class_key irq_nested_lock_class;
  337. static struct lock_class_key irq_nested_request_class;
  338. /*
  339. * irq_map_generic_chip - Map a generic chip for an irq domain
  340. */
  341. int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
  342. irq_hw_number_t hw_irq)
  343. {
  344. struct irq_data *data = irq_domain_get_irq_data(d, virq);
  345. struct irq_domain_chip_generic *dgc = d->gc;
  346. struct irq_chip_generic *gc;
  347. struct irq_chip_type *ct;
  348. struct irq_chip *chip;
  349. unsigned long flags;
  350. int idx;
  351. gc = __irq_get_domain_generic_chip(d, hw_irq);
  352. if (IS_ERR(gc))
  353. return PTR_ERR(gc);
  354. idx = hw_irq % dgc->irqs_per_chip;
  355. if (test_bit(idx, &gc->unused))
  356. return -ENOTSUPP;
  357. if (test_bit(idx, &gc->installed))
  358. return -EBUSY;
  359. ct = gc->chip_types;
  360. chip = &ct->chip;
  361. /* We only init the cache for the first mapping of a generic chip */
  362. if (!gc->installed) {
  363. raw_spin_lock_irqsave(&gc->lock, flags);
  364. irq_gc_init_mask_cache(gc, dgc->gc_flags);
  365. raw_spin_unlock_irqrestore(&gc->lock, flags);
  366. }
  367. /* Mark the interrupt as installed */
  368. set_bit(idx, &gc->installed);
  369. if (dgc->gc_flags & IRQ_GC_INIT_NESTED_LOCK)
  370. irq_set_lockdep_class(virq, &irq_nested_lock_class,
  371. &irq_nested_request_class);
  372. if (chip->irq_calc_mask)
  373. chip->irq_calc_mask(data);
  374. else
  375. data->mask = 1 << idx;
  376. irq_domain_set_info(d, virq, hw_irq, chip, gc, ct->handler, NULL, NULL);
  377. irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set);
  378. return 0;
  379. }
  380. void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq)
  381. {
  382. struct irq_data *data = irq_domain_get_irq_data(d, virq);
  383. struct irq_domain_chip_generic *dgc = d->gc;
  384. unsigned int hw_irq = data->hwirq;
  385. struct irq_chip_generic *gc;
  386. int irq_idx;
  387. gc = irq_get_domain_generic_chip(d, hw_irq);
  388. if (!gc)
  389. return;
  390. irq_idx = hw_irq % dgc->irqs_per_chip;
  391. clear_bit(irq_idx, &gc->installed);
  392. irq_domain_set_info(d, virq, hw_irq, &no_irq_chip, NULL, NULL, NULL,
  393. NULL);
  394. }
  395. const struct irq_domain_ops irq_generic_chip_ops = {
  396. .map = irq_map_generic_chip,
  397. .unmap = irq_unmap_generic_chip,
  398. .xlate = irq_domain_xlate_onetwocell,
  399. };
  400. EXPORT_SYMBOL_GPL(irq_generic_chip_ops);
  401. /**
  402. * irq_setup_generic_chip - Setup a range of interrupts with a generic chip
  403. * @gc: Generic irq chip holding all data
  404. * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
  405. * @flags: Flags for initialization
  406. * @clr: IRQ_* bits to clear
  407. * @set: IRQ_* bits to set
  408. *
  409. * Set up max. 32 interrupts starting from gc->irq_base. Note, this
  410. * initializes all interrupts to the primary irq_chip_type and its
  411. * associated handler.
  412. */
  413. void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
  414. enum irq_gc_flags flags, unsigned int clr,
  415. unsigned int set)
  416. {
  417. struct irq_chip_type *ct = gc->chip_types;
  418. struct irq_chip *chip = &ct->chip;
  419. unsigned int i;
  420. raw_spin_lock(&gc_lock);
  421. list_add_tail(&gc->list, &gc_list);
  422. raw_spin_unlock(&gc_lock);
  423. irq_gc_init_mask_cache(gc, flags);
  424. for (i = gc->irq_base; msk; msk >>= 1, i++) {
  425. if (!(msk & 0x01))
  426. continue;
  427. if (flags & IRQ_GC_INIT_NESTED_LOCK)
  428. irq_set_lockdep_class(i, &irq_nested_lock_class,
  429. &irq_nested_request_class);
  430. if (!(flags & IRQ_GC_NO_MASK)) {
  431. struct irq_data *d = irq_get_irq_data(i);
  432. if (chip->irq_calc_mask)
  433. chip->irq_calc_mask(d);
  434. else
  435. d->mask = 1 << (i - gc->irq_base);
  436. }
  437. irq_set_chip_and_handler(i, chip, ct->handler);
  438. irq_set_chip_data(i, gc);
  439. irq_modify_status(i, clr, set);
  440. }
  441. gc->irq_cnt = i - gc->irq_base;
  442. }
  443. EXPORT_SYMBOL_GPL(irq_setup_generic_chip);
  444. /**
  445. * irq_setup_alt_chip - Switch to alternative chip
  446. * @d: irq_data for this interrupt
  447. * @type: Flow type to be initialized
  448. *
  449. * Only to be called from chip->irq_set_type() callbacks.
  450. */
  451. int irq_setup_alt_chip(struct irq_data *d, unsigned int type)
  452. {
  453. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  454. struct irq_chip_type *ct = gc->chip_types;
  455. unsigned int i;
  456. for (i = 0; i < gc->num_ct; i++, ct++) {
  457. if (ct->type & type) {
  458. d->chip = &ct->chip;
  459. irq_data_to_desc(d)->handle_irq = ct->handler;
  460. return 0;
  461. }
  462. }
  463. return -EINVAL;
  464. }
  465. EXPORT_SYMBOL_GPL(irq_setup_alt_chip);
  466. /**
  467. * irq_remove_generic_chip - Remove a chip
  468. * @gc: Generic irq chip holding all data
  469. * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
  470. * @clr: IRQ_* bits to clear
  471. * @set: IRQ_* bits to set
  472. *
  473. * Remove up to 32 interrupts starting from gc->irq_base.
  474. */
  475. void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
  476. unsigned int clr, unsigned int set)
  477. {
  478. unsigned int i, virq;
  479. raw_spin_lock(&gc_lock);
  480. list_del(&gc->list);
  481. raw_spin_unlock(&gc_lock);
  482. for (i = 0; msk; msk >>= 1, i++) {
  483. if (!(msk & 0x01))
  484. continue;
  485. /*
  486. * Interrupt domain based chips store the base hardware
  487. * interrupt number in gc::irq_base. Otherwise gc::irq_base
  488. * contains the base Linux interrupt number.
  489. */
  490. if (gc->domain) {
  491. virq = irq_find_mapping(gc->domain, gc->irq_base + i);
  492. if (!virq)
  493. continue;
  494. } else {
  495. virq = gc->irq_base + i;
  496. }
  497. /* Remove handler first. That will mask the irq line */
  498. irq_set_handler(virq, NULL);
  499. irq_set_chip(virq, &no_irq_chip);
  500. irq_set_chip_data(virq, NULL);
  501. irq_modify_status(virq, clr, set);
  502. }
  503. }
  504. EXPORT_SYMBOL_GPL(irq_remove_generic_chip);
  505. static struct irq_data *irq_gc_get_irq_data(struct irq_chip_generic *gc)
  506. {
  507. unsigned int virq;
  508. if (!gc->domain)
  509. return irq_get_irq_data(gc->irq_base);
  510. /*
  511. * We don't know which of the irqs has been actually
  512. * installed. Use the first one.
  513. */
  514. if (!gc->installed)
  515. return NULL;
  516. virq = irq_find_mapping(gc->domain, gc->irq_base + __ffs(gc->installed));
  517. return virq ? irq_get_irq_data(virq) : NULL;
  518. }
  519. #ifdef CONFIG_PM
  520. static int irq_gc_suspend(void)
  521. {
  522. struct irq_chip_generic *gc;
  523. list_for_each_entry(gc, &gc_list, list) {
  524. struct irq_chip_type *ct = gc->chip_types;
  525. if (ct->chip.irq_suspend) {
  526. struct irq_data *data = irq_gc_get_irq_data(gc);
  527. if (data)
  528. ct->chip.irq_suspend(data);
  529. }
  530. if (gc->suspend)
  531. gc->suspend(gc);
  532. }
  533. return 0;
  534. }
  535. static void irq_gc_resume(void)
  536. {
  537. struct irq_chip_generic *gc;
  538. list_for_each_entry(gc, &gc_list, list) {
  539. struct irq_chip_type *ct = gc->chip_types;
  540. if (gc->resume)
  541. gc->resume(gc);
  542. if (ct->chip.irq_resume) {
  543. struct irq_data *data = irq_gc_get_irq_data(gc);
  544. if (data)
  545. ct->chip.irq_resume(data);
  546. }
  547. }
  548. }
  549. #else
  550. #define irq_gc_suspend NULL
  551. #define irq_gc_resume NULL
  552. #endif
  553. static void irq_gc_shutdown(void)
  554. {
  555. struct irq_chip_generic *gc;
  556. list_for_each_entry(gc, &gc_list, list) {
  557. struct irq_chip_type *ct = gc->chip_types;
  558. if (ct->chip.irq_pm_shutdown) {
  559. struct irq_data *data = irq_gc_get_irq_data(gc);
  560. if (data)
  561. ct->chip.irq_pm_shutdown(data);
  562. }
  563. }
  564. }
  565. static struct syscore_ops irq_gc_syscore_ops = {
  566. .suspend = irq_gc_suspend,
  567. .resume = irq_gc_resume,
  568. .shutdown = irq_gc_shutdown,
  569. };
  570. static int __init irq_gc_init_ops(void)
  571. {
  572. register_syscore_ops(&irq_gc_syscore_ops);
  573. return 0;
  574. }
  575. device_initcall(irq_gc_init_ops);