acp63_chip_offset_byte.h 26 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * AMD ACP 6.3 Register Documentation
  4. *
  5. * Copyright 2022 Advanced Micro Devices, Inc.
  6. */
  7. #ifndef _acp_ip_OFFSET_HEADER
  8. #define _acp_ip_OFFSET_HEADER
  9. /* Registers from ACP_DMA block */
  10. #define ACP_DMA_CNTL_0 0x0000000
  11. #define ACP_DMA_CNTL_1 0x0000004
  12. #define ACP_DMA_CNTL_2 0x0000008
  13. #define ACP_DMA_CNTL_3 0x000000C
  14. #define ACP_DMA_CNTL_4 0x0000010
  15. #define ACP_DMA_CNTL_5 0x0000014
  16. #define ACP_DMA_CNTL_6 0x0000018
  17. #define ACP_DMA_CNTL_7 0x000001C
  18. #define ACP_DMA_DSCR_STRT_IDX_0 0x0000020
  19. #define ACP_DMA_DSCR_STRT_IDX_1 0x0000024
  20. #define ACP_DMA_DSCR_STRT_IDX_2 0x0000028
  21. #define ACP_DMA_DSCR_STRT_IDX_3 0x000002C
  22. #define ACP_DMA_DSCR_STRT_IDX_4 0x0000030
  23. #define ACP_DMA_DSCR_STRT_IDX_5 0x0000034
  24. #define ACP_DMA_DSCR_STRT_IDX_6 0x0000038
  25. #define ACP_DMA_DSCR_STRT_IDX_7 0x000003C
  26. #define ACP_DMA_DSCR_CNT_0 0x0000040
  27. #define ACP_DMA_DSCR_CNT_1 0x0000044
  28. #define ACP_DMA_DSCR_CNT_2 0x0000048
  29. #define ACP_DMA_DSCR_CNT_3 0x000004C
  30. #define ACP_DMA_DSCR_CNT_4 0x0000050
  31. #define ACP_DMA_DSCR_CNT_5 0x0000054
  32. #define ACP_DMA_DSCR_CNT_6 0x0000058
  33. #define ACP_DMA_DSCR_CNT_7 0x000005C
  34. #define ACP_DMA_PRIO_0 0x0000060
  35. #define ACP_DMA_PRIO_1 0x0000064
  36. #define ACP_DMA_PRIO_2 0x0000068
  37. #define ACP_DMA_PRIO_3 0x000006C
  38. #define ACP_DMA_PRIO_4 0x0000070
  39. #define ACP_DMA_PRIO_5 0x0000074
  40. #define ACP_DMA_PRIO_6 0x0000078
  41. #define ACP_DMA_PRIO_7 0x000007C
  42. #define ACP_DMA_CUR_DSCR_0 0x0000080
  43. #define ACP_DMA_CUR_DSCR_1 0x0000084
  44. #define ACP_DMA_CUR_DSCR_2 0x0000088
  45. #define ACP_DMA_CUR_DSCR_3 0x000008C
  46. #define ACP_DMA_CUR_DSCR_4 0x0000090
  47. #define ACP_DMA_CUR_DSCR_5 0x0000094
  48. #define ACP_DMA_CUR_DSCR_6 0x0000098
  49. #define ACP_DMA_CUR_DSCR_7 0x000009C
  50. #define ACP_DMA_CUR_TRANS_CNT_0 0x00000A0
  51. #define ACP_DMA_CUR_TRANS_CNT_1 0x00000A4
  52. #define ACP_DMA_CUR_TRANS_CNT_2 0x00000A8
  53. #define ACP_DMA_CUR_TRANS_CNT_3 0x00000AC
  54. #define ACP_DMA_CUR_TRANS_CNT_4 0x00000B0
  55. #define ACP_DMA_CUR_TRANS_CNT_5 0x00000B4
  56. #define ACP_DMA_CUR_TRANS_CNT_6 0x00000B8
  57. #define ACP_DMA_CUR_TRANS_CNT_7 0x00000BC
  58. #define ACP_DMA_ERR_STS_0 0x00000C0
  59. #define ACP_DMA_ERR_STS_1 0x00000C4
  60. #define ACP_DMA_ERR_STS_2 0x00000C8
  61. #define ACP_DMA_ERR_STS_3 0x00000CC
  62. #define ACP_DMA_ERR_STS_4 0x00000D0
  63. #define ACP_DMA_ERR_STS_5 0x00000D4
  64. #define ACP_DMA_ERR_STS_6 0x00000D8
  65. #define ACP_DMA_ERR_STS_7 0x00000DC
  66. #define ACP_DMA_DESC_BASE_ADDR 0x00000E0
  67. #define ACP_DMA_DESC_MAX_NUM_DSCR 0x00000E4
  68. #define ACP_DMA_CH_STS 0x00000E8
  69. #define ACP_DMA_CH_GROUP 0x00000EC
  70. #define ACP_DMA_CH_RST_STS 0x00000F0
  71. /* Registers from ACP_AXI2AXIATU block */
  72. #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1 0x0000C00
  73. #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1 0x0000C04
  74. #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2 0x0000C08
  75. #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2 0x0000C0C
  76. #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3 0x0000C10
  77. #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3 0x0000C14
  78. #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4 0x0000C18
  79. #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4 0x0000C1C
  80. #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0x0000C20
  81. #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0x0000C24
  82. #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6 0x0000C28
  83. #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6 0x0000C2C
  84. #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7 0x0000C30
  85. #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7 0x0000C34
  86. #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8 0x0000C38
  87. #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8 0x0000C3C
  88. #define ACPAXI2AXI_ATU_CTRL 0x0000C40
  89. #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_9 0x0000C44
  90. #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_9 0x0000C48
  91. #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_10 0x0000C4C
  92. #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_10 0x0000C50
  93. #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_11 0x0000C54
  94. #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_11 0x0000C58
  95. #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_12 0x0000C5C
  96. #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_12 0x0000C60
  97. #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_13 0x0000C64
  98. #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_13 0x0000C68
  99. #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_14 0x0000C6C
  100. #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_14 0x0000C70
  101. #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_15 0x0000C74
  102. #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_15 0x0000C78
  103. #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_16 0x0000C7C
  104. #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_16 0x0000C80
  105. /* Registers from ACP_CLKRST block */
  106. #define ACP_SOFT_RESET 0x0001000
  107. #define ACP_CONTROL 0x0001004
  108. #define ACP_STATUS 0x0001008
  109. #define ACP_DYNAMIC_CG_MASTER_CONTROL 0x0001010
  110. #define ACP_ZSC_DSP_CTRL 0x0001014
  111. #define ACP_ZSC_STS 0x0001018
  112. #define ACP_PGFSM_CONTROL 0x0001024
  113. #define ACP_PGFSM_STATUS 0x0001028
  114. #define ACP_CLKMUX_SEL 0x000102C
  115. /* Registers from ACP_AON block */
  116. #define ACP_PME_EN 0x0001400
  117. #define ACP_DEVICE_STATE 0x0001404
  118. #define AZ_DEVICE_STATE 0x0001408
  119. #define ACP_PIN_CONFIG 0x0001440
  120. #define ACP_PAD_PULLUP_CTRL 0x0001444
  121. #define ACP_PAD_PULLDOWN_CTRL 0x0001448
  122. #define ACP_PAD_DRIVE_STRENGTH_CTRL 0x000144C
  123. #define ACP_PAD_SCHMEN_CTRL 0x0001450
  124. #define ACP_SW_PAD_KEEPER_EN 0x0001454
  125. #define ACP_SW_WAKE_EN 0x0001458
  126. #define ACP_I2S_WAKE_EN 0x000145C
  127. #define ACP_SW1_WAKE_EN 0x0001460
  128. /* Registers from ACP_P1_MISC block */
  129. #define ACP_EXTERNAL_INTR_ENB 0x0001A00
  130. #define ACP_EXTERNAL_INTR_CNTL 0x0001A04
  131. #define ACP_EXTERNAL_INTR_CNTL1 0x0001A08
  132. #define ACP_EXTERNAL_INTR_STAT 0x0001A0C
  133. #define ACP_EXTERNAL_INTR_STAT1 0x0001A10
  134. #define ACP_ERROR_STATUS 0x0001A4C
  135. #define ACP_P1_SW_I2S_ERROR_REASON 0x0001A50
  136. #define ACP_P1_SW_POS_TRACK_I2S_TX_CTRL 0x0001A6C
  137. #define ACP_P1_SW_I2S_TX_DMA_POS 0x0001A70
  138. #define ACP_P1_SW_POS_TRACK_I2S_RX_CTRL 0x0001A74
  139. #define ACP_P1_SW_I2S_RX_DMA_POS 0x0001A78
  140. #define ACP_P1_DMIC_I2S_GPIO_INTR_CTRL 0x0001A7C
  141. #define ACP_P1_DMIC_I2S_GPIO_INTR_STATUS 0x0001A80
  142. #define ACP_SCRATCH_REG_BASE_ADDR 0x0001A84
  143. #define ACP_P1_SW_POS_TRACK_BT_TX_CTRL 0x0001A88
  144. #define ACP_P1_SW_BT_TX_DMA_POS 0x0001A8C
  145. #define ACP_P1_SW_POS_TRACK_HS_TX_CTRL 0x0001A90
  146. #define ACP_P1_SW_HS_TX_DMA_POS 0x0001A94
  147. #define ACP_P1_SW_POS_TRACK_BT_RX_CTRL 0x0001A98
  148. #define ACP_P1_SW_BT_RX_DMA_POS 0x0001A9C
  149. #define ACP_P1_SW_POS_TRACK_HS_RX_CTRL 0x0001AA0
  150. #define ACP_P1_SW_HS_RX_DMA_POS 0x0001AA4
  151. /* Registers from ACP_AUDIO_BUFFERS block */
  152. #define ACP_I2S_RX_RINGBUFADDR 0x0002000
  153. #define ACP_I2S_RX_RINGBUFSIZE 0x0002004
  154. #define ACP_I2S_RX_LINKPOSITIONCNTR 0x0002008
  155. #define ACP_I2S_RX_FIFOADDR 0x000200C
  156. #define ACP_I2S_RX_FIFOSIZE 0x0002010
  157. #define ACP_I2S_RX_DMA_SIZE 0x0002014
  158. #define ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH 0x0002018
  159. #define ACP_I2S_RX_LINEARPOSITIONCNTR_LOW 0x000201C
  160. #define ACP_I2S_RX_INTR_WATERMARK_SIZE 0x0002020
  161. #define ACP_I2S_TX_RINGBUFADDR 0x0002024
  162. #define ACP_I2S_TX_RINGBUFSIZE 0x0002028
  163. #define ACP_I2S_TX_LINKPOSITIONCNTR 0x000202C
  164. #define ACP_I2S_TX_FIFOADDR 0x0002030
  165. #define ACP_I2S_TX_FIFOSIZE 0x0002034
  166. #define ACP_I2S_TX_DMA_SIZE 0x0002038
  167. #define ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH 0x000203C
  168. #define ACP_I2S_TX_LINEARPOSITIONCNTR_LOW 0x0002040
  169. #define ACP_I2S_TX_INTR_WATERMARK_SIZE 0x0002044
  170. #define ACP_BT_RX_RINGBUFADDR 0x0002048
  171. #define ACP_BT_RX_RINGBUFSIZE 0x000204C
  172. #define ACP_BT_RX_LINKPOSITIONCNTR 0x0002050
  173. #define ACP_BT_RX_FIFOADDR 0x0002054
  174. #define ACP_BT_RX_FIFOSIZE 0x0002058
  175. #define ACP_BT_RX_DMA_SIZE 0x000205C
  176. #define ACP_BT_RX_LINEARPOSITIONCNTR_HIGH 0x0002060
  177. #define ACP_BT_RX_LINEARPOSITIONCNTR_LOW 0x0002064
  178. #define ACP_BT_RX_INTR_WATERMARK_SIZE 0x0002068
  179. #define ACP_BT_TX_RINGBUFADDR 0x000206C
  180. #define ACP_BT_TX_RINGBUFSIZE 0x0002070
  181. #define ACP_BT_TX_LINKPOSITIONCNTR 0x0002074
  182. #define ACP_BT_TX_FIFOADDR 0x0002078
  183. #define ACP_BT_TX_FIFOSIZE 0x000207C
  184. #define ACP_BT_TX_DMA_SIZE 0x0002080
  185. #define ACP_BT_TX_LINEARPOSITIONCNTR_HIGH 0x0002084
  186. #define ACP_BT_TX_LINEARPOSITIONCNTR_LOW 0x0002088
  187. #define ACP_BT_TX_INTR_WATERMARK_SIZE 0x000208C
  188. #define ACP_HS_RX_RINGBUFADDR 0x0002090
  189. #define ACP_HS_RX_RINGBUFSIZE 0x0002094
  190. #define ACP_HS_RX_LINKPOSITIONCNTR 0x0002098
  191. #define ACP_HS_RX_FIFOADDR 0x000209C
  192. #define ACP_HS_RX_FIFOSIZE 0x00020A0
  193. #define ACP_HS_RX_DMA_SIZE 0x00020A4
  194. #define ACP_HS_RX_LINEARPOSITIONCNTR_HIGH 0x00020A8
  195. #define ACP_HS_RX_LINEARPOSITIONCNTR_LOW 0x00020AC
  196. #define ACP_HS_RX_INTR_WATERMARK_SIZE 0x00020B0
  197. #define ACP_HS_TX_RINGBUFADDR 0x00020B4
  198. #define ACP_HS_TX_RINGBUFSIZE 0x00020B8
  199. #define ACP_HS_TX_LINKPOSITIONCNTR 0x00020BC
  200. #define ACP_HS_TX_FIFOADDR 0x00020C0
  201. #define ACP_HS_TX_FIFOSIZE 0x00020C4
  202. #define ACP_HS_TX_DMA_SIZE 0x00020C8
  203. #define ACP_HS_TX_LINEARPOSITIONCNTR_HIGH 0x00020CC
  204. #define ACP_HS_TX_LINEARPOSITIONCNTR_LOW 0x00020D0
  205. #define ACP_HS_TX_INTR_WATERMARK_SIZE 0x00020D4
  206. /* Registers from ACP_I2S_TDM block */
  207. #define ACP_I2STDM_IER 0x0002400
  208. #define ACP_I2STDM_IRER 0x0002404
  209. #define ACP_I2STDM_RXFRMT 0x0002408
  210. #define ACP_I2STDM_ITER 0x000240C
  211. #define ACP_I2STDM_TXFRMT 0x0002410
  212. #define ACP_I2STDM0_MSTRCLKGEN 0x0002414
  213. #define ACP_I2STDM1_MSTRCLKGEN 0x0002418
  214. #define ACP_I2STDM2_MSTRCLKGEN 0x000241C
  215. #define ACP_I2STDM_REFCLKGEN 0x0002420
  216. /* Registers from ACP_BT_TDM block */
  217. #define ACP_BTTDM_IER 0x0002800
  218. #define ACP_BTTDM_IRER 0x0002804
  219. #define ACP_BTTDM_RXFRMT 0x0002808
  220. #define ACP_BTTDM_ITER 0x000280C
  221. #define ACP_BTTDM_TXFRMT 0x0002810
  222. #define ACP_HSTDM_IER 0x0002814
  223. #define ACP_HSTDM_IRER 0x0002818
  224. #define ACP_HSTDM_RXFRMT 0x000281C
  225. #define ACP_HSTDM_ITER 0x0002820
  226. #define ACP_HSTDM_TXFRMT 0x0002824
  227. /* Registers from ACP_WOV block */
  228. #define ACP_WOV_PDM_ENABLE 0x0002C04
  229. #define ACP_WOV_PDM_DMA_ENABLE 0x0002C08
  230. #define ACP_WOV_RX_RINGBUFADDR 0x0002C0C
  231. #define ACP_WOV_RX_RINGBUFSIZE 0x0002C10
  232. #define ACP_WOV_RX_LINKPOSITIONCNTR 0x0002C14
  233. #define ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH 0x0002C18
  234. #define ACP_WOV_RX_LINEARPOSITIONCNTR_LOW 0x0002C1C
  235. #define ACP_WOV_RX_INTR_WATERMARK_SIZE 0x0002C20
  236. #define ACP_WOV_PDM_FIFO_FLUSH 0x0002C24
  237. #define ACP_WOV_PDM_NO_OF_CHANNELS 0x0002C28
  238. #define ACP_WOV_PDM_DECIMATION_FACTOR 0x0002C2C
  239. #define ACP_WOV_PDM_VAD_CTRL 0x0002C30
  240. #define ACP_WOV_WAKE 0x0002C54
  241. #define ACP_WOV_BUFFER_STATUS 0x0002C58
  242. #define ACP_WOV_MISC_CTRL 0x0002C5C
  243. #define ACP_WOV_CLK_CTRL 0x0002C60
  244. #define ACP_PDM_VAD_DYNAMIC_CLK_GATING_EN 0x0002C64
  245. #define ACP_WOV_ERROR_STATUS_REGISTER 0x0002C68
  246. #define ACP_PDM_CLKDIV 0x0002C6C
  247. /* Registers from ACP_P1_AUDIO_BUFFERS block */
  248. #define ACP_P1_I2S_RX_RINGBUFADDR 0x0003A00
  249. #define ACP_P1_I2S_RX_RINGBUFSIZE 0x0003A04
  250. #define ACP_P1_I2S_RX_LINKPOSITIONCNTR 0x0003A08
  251. #define ACP_P1_I2S_RX_FIFOADDR 0x0003A0C
  252. #define ACP_P1_I2S_RX_FIFOSIZE 0x0003A10
  253. #define ACP_P1_I2S_RX_DMA_SIZE 0x0003A14
  254. #define ACP_P1_I2S_RX_LINEARPOSITIONCNTR_HIGH 0x0003A18
  255. #define ACP_P1_I2S_RX_LINEARPOSITIONCNTR_LOW 0x0003A1C
  256. #define ACP_P1_I2S_RX_INTR_WATERMARK_SIZE 0x0003A20
  257. #define ACP_P1_I2S_TX_RINGBUFADDR 0x0003A24
  258. #define ACP_P1_I2S_TX_RINGBUFSIZE 0x0003A28
  259. #define ACP_P1_I2S_TX_LINKPOSITIONCNTR 0x0003A2C
  260. #define ACP_P1_I2S_TX_FIFOADDR 0x0003A30
  261. #define ACP_P1_I2S_TX_FIFOSIZE 0x0003A34
  262. #define ACP_P1_I2S_TX_DMA_SIZE 0x0003A38
  263. #define ACP_P1_I2S_TX_LINEARPOSITIONCNTR_HIGH 0x0003A3C
  264. #define ACP_P1_I2S_TX_LINEARPOSITIONCNTR_LOW 0x0003A40
  265. #define ACP_P1_I2S_TX_INTR_WATERMARK_SIZE 0x0003A44
  266. #define ACP_P1_BT_RX_RINGBUFADDR 0x0003A48
  267. #define ACP_P1_BT_RX_RINGBUFSIZE 0x0003A4C
  268. #define ACP_P1_BT_RX_LINKPOSITIONCNTR 0x0003A50
  269. #define ACP_P1_BT_RX_FIFOADDR 0x0003A54
  270. #define ACP_P1_BT_RX_FIFOSIZE 0x0003A58
  271. #define ACP_P1_BT_RX_DMA_SIZE 0x0003A5C
  272. #define ACP_P1_BT_RX_LINEARPOSITIONCNTR_HIGH 0x0003A60
  273. #define ACP_P1_BT_RX_LINEARPOSITIONCNTR_LOW 0x0003A64
  274. #define ACP_P1_BT_RX_INTR_WATERMARK_SIZE 0x0003A68
  275. #define ACP_P1_BT_TX_RINGBUFADDR 0x0003A6C
  276. #define ACP_P1_BT_TX_RINGBUFSIZE 0x0003A70
  277. #define ACP_P1_BT_TX_LINKPOSITIONCNTR 0x0003A74
  278. #define ACP_P1_BT_TX_FIFOADDR 0x0003A78
  279. #define ACP_P1_BT_TX_FIFOSIZE 0x0003A7C
  280. #define ACP_P1_BT_TX_DMA_SIZE 0x0003A80
  281. #define ACP_P1_BT_TX_LINEARPOSITIONCNTR_HIGH 0x0003A84
  282. #define ACP_P1_BT_TX_LINEARPOSITIONCNTR_LOW 0x0003A88
  283. #define ACP_P1_BT_TX_INTR_WATERMARK_SIZE 0x0003A8C
  284. #define ACP_P1_HS_RX_RINGBUFADDR 0x0003A90
  285. #define ACP_P1_HS_RX_RINGBUFSIZE 0x0003A94
  286. #define ACP_P1_HS_RX_LINKPOSITIONCNTR 0x0003A98
  287. #define ACP_P1_HS_RX_FIFOADDR 0x0003A9C
  288. #define ACP_P1_HS_RX_FIFOSIZE 0x0003AA0
  289. #define ACP_P1_HS_RX_DMA_SIZE 0x0003AA4
  290. #define ACP_P1_HS_RX_LINEARPOSITIONCNTR_HIGH 0x0003AA8
  291. #define ACP_P1_HS_RX_LINEARPOSITIONCNTR_LOW 0x0003AAC
  292. #define ACP_P1_HS_RX_INTR_WATERMARK_SIZE 0x0003AB0
  293. #define ACP_P1_HS_TX_RINGBUFADDR 0x0003AB4
  294. #define ACP_P1_HS_TX_RINGBUFSIZE 0x0003AB8
  295. #define ACP_P1_HS_TX_LINKPOSITIONCNTR 0x0003ABC
  296. #define ACP_P1_HS_TX_FIFOADDR 0x0003AC0
  297. #define ACP_P1_HS_TX_FIFOSIZE 0x0003AC4
  298. #define ACP_P1_HS_TX_DMA_SIZE 0x0003AC8
  299. #define ACP_P1_HS_TX_LINEARPOSITIONCNTR_HIGH 0x0003ACC
  300. #define ACP_P1_HS_TX_LINEARPOSITIONCNTR_LOW 0x0003AD0
  301. #define ACP_P1_HS_TX_INTR_WATERMARK_SIZE 0x0003AD4
  302. /* Registers from ACP_SCRATCH block */
  303. #define ACP_SCRATCH_REG_0 0x0010000
  304. #define ACP_SCRATCH_REG_1 0x0010004
  305. #define ACP_SCRATCH_REG_2 0x0010008
  306. #define ACP_SCRATCH_REG_3 0x001000C
  307. #define ACP_SCRATCH_REG_4 0x0010010
  308. #define ACP_SCRATCH_REG_5 0x0010014
  309. #define ACP_SCRATCH_REG_6 0x0010018
  310. #define ACP_SCRATCH_REG_7 0x001001C
  311. #define ACP_SCRATCH_REG_8 0x0010020
  312. #define ACP_SCRATCH_REG_9 0x0010024
  313. #define ACP_SCRATCH_REG_10 0x0010028
  314. #define ACP_SCRATCH_REG_11 0x001002C
  315. #define ACP_SCRATCH_REG_12 0x0010030
  316. #define ACP_SCRATCH_REG_13 0x0010034
  317. #define ACP_SCRATCH_REG_14 0x0010038
  318. #define ACP_SCRATCH_REG_15 0x001003C
  319. #define ACP_SCRATCH_REG_16 0x0010040
  320. #define ACP_SCRATCH_REG_17 0x0010044
  321. #define ACP_SCRATCH_REG_18 0x0010048
  322. #define ACP_SCRATCH_REG_19 0x001004C
  323. #define ACP_SCRATCH_REG_20 0x0010050
  324. #define ACP_SCRATCH_REG_21 0x0010054
  325. #define ACP_SCRATCH_REG_22 0x0010058
  326. #define ACP_SCRATCH_REG_23 0x001005C
  327. #define ACP_SCRATCH_REG_24 0x0010060
  328. #define ACP_SCRATCH_REG_25 0x0010064
  329. #define ACP_SCRATCH_REG_26 0x0010068
  330. #define ACP_SCRATCH_REG_27 0x001006C
  331. #define ACP_SCRATCH_REG_28 0x0010070
  332. #define ACP_SCRATCH_REG_29 0x0010074
  333. #define ACP_SCRATCH_REG_30 0x0010078
  334. #define ACP_SCRATCH_REG_31 0x001007C
  335. #define ACP_SCRATCH_REG_32 0x0010080
  336. #define ACP_SCRATCH_REG_33 0x0010084
  337. #define ACP_SCRATCH_REG_34 0x0010088
  338. #define ACP_SCRATCH_REG_35 0x001008C
  339. #define ACP_SCRATCH_REG_36 0x0010090
  340. #define ACP_SCRATCH_REG_37 0x0010094
  341. #define ACP_SCRATCH_REG_38 0x0010098
  342. #define ACP_SCRATCH_REG_39 0x001009C
  343. #define ACP_SCRATCH_REG_40 0x00100A0
  344. #define ACP_SCRATCH_REG_41 0x00100A4
  345. #define ACP_SCRATCH_REG_42 0x00100A8
  346. #define ACP_SCRATCH_REG_43 0x00100AC
  347. #define ACP_SCRATCH_REG_44 0x00100B0
  348. #define ACP_SCRATCH_REG_45 0x00100B4
  349. #define ACP_SCRATCH_REG_46 0x00100B8
  350. #define ACP_SCRATCH_REG_47 0x00100BC
  351. #define ACP_SCRATCH_REG_48 0x00100C0
  352. #define ACP_SCRATCH_REG_49 0x00100C4
  353. #define ACP_SCRATCH_REG_50 0x00100C8
  354. #define ACP_SCRATCH_REG_51 0x00100CC
  355. #define ACP_SCRATCH_REG_52 0x00100D0
  356. #define ACP_SCRATCH_REG_53 0x00100D4
  357. #define ACP_SCRATCH_REG_54 0x00100D8
  358. #define ACP_SCRATCH_REG_55 0x00100DC
  359. #define ACP_SCRATCH_REG_56 0x00100E0
  360. #define ACP_SCRATCH_REG_57 0x00100E4
  361. #define ACP_SCRATCH_REG_58 0x00100E8
  362. #define ACP_SCRATCH_REG_59 0x00100EC
  363. #define ACP_SCRATCH_REG_60 0x00100F0
  364. #define ACP_SCRATCH_REG_61 0x00100F4
  365. #define ACP_SCRATCH_REG_62 0x00100F8
  366. #define ACP_SCRATCH_REG_63 0x00100FC
  367. #define ACP_SCRATCH_REG_64 0x0010100
  368. #define ACP_SCRATCH_REG_65 0x0010104
  369. #define ACP_SCRATCH_REG_66 0x0010108
  370. #define ACP_SCRATCH_REG_67 0x001010C
  371. #define ACP_SCRATCH_REG_68 0x0010110
  372. #define ACP_SCRATCH_REG_69 0x0010114
  373. #define ACP_SCRATCH_REG_70 0x0010118
  374. #define ACP_SCRATCH_REG_71 0x001011C
  375. #define ACP_SCRATCH_REG_72 0x0010120
  376. #define ACP_SCRATCH_REG_73 0x0010124
  377. #define ACP_SCRATCH_REG_74 0x0010128
  378. #define ACP_SCRATCH_REG_75 0x001012C
  379. #define ACP_SCRATCH_REG_76 0x0010130
  380. #define ACP_SCRATCH_REG_77 0x0010134
  381. #define ACP_SCRATCH_REG_78 0x0010138
  382. #define ACP_SCRATCH_REG_79 0x001013C
  383. #define ACP_SCRATCH_REG_80 0x0010140
  384. #define ACP_SCRATCH_REG_81 0x0010144
  385. #define ACP_SCRATCH_REG_82 0x0010148
  386. #define ACP_SCRATCH_REG_83 0x001014C
  387. #define ACP_SCRATCH_REG_84 0x0010150
  388. #define ACP_SCRATCH_REG_85 0x0010154
  389. #define ACP_SCRATCH_REG_86 0x0010158
  390. #define ACP_SCRATCH_REG_87 0x001015C
  391. #define ACP_SCRATCH_REG_88 0x0010160
  392. #define ACP_SCRATCH_REG_89 0x0010164
  393. #define ACP_SCRATCH_REG_90 0x0010168
  394. #define ACP_SCRATCH_REG_91 0x001016C
  395. #define ACP_SCRATCH_REG_92 0x0010170
  396. #define ACP_SCRATCH_REG_93 0x0010174
  397. #define ACP_SCRATCH_REG_94 0x0010178
  398. #define ACP_SCRATCH_REG_95 0x001017C
  399. #define ACP_SCRATCH_REG_96 0x0010180
  400. #define ACP_SCRATCH_REG_97 0x0010184
  401. #define ACP_SCRATCH_REG_98 0x0010188
  402. #define ACP_SCRATCH_REG_99 0x001018C
  403. #define ACP_SCRATCH_REG_100 0x0010190
  404. #define ACP_SCRATCH_REG_101 0x0010194
  405. #define ACP_SCRATCH_REG_102 0x0010198
  406. #define ACP_SCRATCH_REG_103 0x001019C
  407. #define ACP_SCRATCH_REG_104 0x00101A0
  408. #define ACP_SCRATCH_REG_105 0x00101A4
  409. #define ACP_SCRATCH_REG_106 0x00101A8
  410. #define ACP_SCRATCH_REG_107 0x00101AC
  411. #define ACP_SCRATCH_REG_108 0x00101B0
  412. #define ACP_SCRATCH_REG_109 0x00101B4
  413. #define ACP_SCRATCH_REG_110 0x00101B8
  414. #define ACP_SCRATCH_REG_111 0x00101BC
  415. #define ACP_SCRATCH_REG_112 0x00101C0
  416. #define ACP_SCRATCH_REG_113 0x00101C4
  417. #define ACP_SCRATCH_REG_114 0x00101C8
  418. #define ACP_SCRATCH_REG_115 0x00101CC
  419. #define ACP_SCRATCH_REG_116 0x00101D0
  420. #define ACP_SCRATCH_REG_117 0x00101D4
  421. #define ACP_SCRATCH_REG_118 0x00101D8
  422. #define ACP_SCRATCH_REG_119 0x00101DC
  423. #define ACP_SCRATCH_REG_120 0x00101E0
  424. #define ACP_SCRATCH_REG_121 0x00101E4
  425. #define ACP_SCRATCH_REG_122 0x00101E8
  426. #define ACP_SCRATCH_REG_123 0x00101EC
  427. #define ACP_SCRATCH_REG_124 0x00101F0
  428. #define ACP_SCRATCH_REG_125 0x00101F4
  429. #define ACP_SCRATCH_REG_126 0x00101F8
  430. #define ACP_SCRATCH_REG_127 0x00101FC
  431. #define ACP_SCRATCH_REG_128 0x0010200
  432. #endif