sungem_phy.h 4.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #ifndef __SUNGEM_PHY_H__
  3. #define __SUNGEM_PHY_H__
  4. #include <linux/types.h>
  5. struct mii_phy;
  6. /* Operations supported by any kind of PHY */
  7. struct mii_phy_ops
  8. {
  9. int (*init)(struct mii_phy *phy);
  10. int (*suspend)(struct mii_phy *phy);
  11. int (*setup_aneg)(struct mii_phy *phy, u32 advertise);
  12. int (*setup_forced)(struct mii_phy *phy, int speed, int fd);
  13. int (*poll_link)(struct mii_phy *phy);
  14. int (*read_link)(struct mii_phy *phy);
  15. int (*enable_fiber)(struct mii_phy *phy, int autoneg);
  16. };
  17. /* Structure used to statically define an mii/gii based PHY */
  18. struct mii_phy_def
  19. {
  20. u32 phy_id; /* Concatenated ID1 << 16 | ID2 */
  21. u32 phy_id_mask; /* Significant bits */
  22. u32 features; /* Ethtool SUPPORTED_* defines */
  23. int magic_aneg; /* Autoneg does all speed test for us */
  24. const char* name;
  25. const struct mii_phy_ops* ops;
  26. };
  27. enum {
  28. BCM54XX_COPPER,
  29. BCM54XX_FIBER,
  30. BCM54XX_GBIC,
  31. BCM54XX_SGMII,
  32. BCM54XX_UNKNOWN,
  33. };
  34. /* An instance of a PHY, partially borrowed from mii_if_info */
  35. struct mii_phy
  36. {
  37. struct mii_phy_def* def;
  38. u32 advertising;
  39. int mii_id;
  40. /* 1: autoneg enabled, 0: disabled */
  41. int autoneg;
  42. /* forced speed & duplex (no autoneg)
  43. * partner speed & duplex & pause (autoneg)
  44. */
  45. int speed;
  46. int duplex;
  47. int pause;
  48. /* Provided by host chip */
  49. struct net_device *dev;
  50. int (*mdio_read) (struct net_device *dev, int mii_id, int reg);
  51. void (*mdio_write) (struct net_device *dev, int mii_id, int reg, int val);
  52. void *platform_data;
  53. };
  54. /* Pass in a struct mii_phy with dev, mdio_read and mdio_write
  55. * filled, the remaining fields will be filled on return
  56. */
  57. extern int sungem_phy_probe(struct mii_phy *phy, int mii_id);
  58. /* MII definitions missing from mii.h */
  59. #define BMCR_SPD2 0x0040 /* Gigabit enable (bcm54xx) */
  60. #define LPA_PAUSE 0x0400
  61. /* More PHY registers (model specific) */
  62. /* MII BCM5201 MULTIPHY interrupt register */
  63. #define MII_BCM5201_INTERRUPT 0x1A
  64. #define MII_BCM5201_INTERRUPT_INTENABLE 0x4000
  65. #define MII_BCM5201_AUXMODE2 0x1B
  66. #define MII_BCM5201_AUXMODE2_LOWPOWER 0x0008
  67. #define MII_BCM5201_MULTIPHY 0x1E
  68. /* MII BCM5201 MULTIPHY register bits */
  69. #define MII_BCM5201_MULTIPHY_SERIALMODE 0x0002
  70. #define MII_BCM5201_MULTIPHY_SUPERISOLATE 0x0008
  71. /* MII BCM5221 Additional registers */
  72. #define MII_BCM5221_TEST 0x1f
  73. #define MII_BCM5221_TEST_ENABLE_SHADOWS 0x0080
  74. #define MII_BCM5221_SHDOW_AUX_STAT2 0x1b
  75. #define MII_BCM5221_SHDOW_AUX_STAT2_APD 0x0020
  76. #define MII_BCM5221_SHDOW_AUX_MODE4 0x1a
  77. #define MII_BCM5221_SHDOW_AUX_MODE4_IDDQMODE 0x0001
  78. #define MII_BCM5221_SHDOW_AUX_MODE4_CLKLOPWR 0x0004
  79. /* MII BCM5241 Additional registers */
  80. #define MII_BCM5241_SHDOW_AUX_MODE4_STANDBYPWR 0x0008
  81. /* MII BCM5400 1000-BASET Control register */
  82. #define MII_BCM5400_GB_CONTROL 0x09
  83. #define MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP 0x0200
  84. /* MII BCM5400 AUXCONTROL register */
  85. #define MII_BCM5400_AUXCONTROL 0x18
  86. #define MII_BCM5400_AUXCONTROL_PWR10BASET 0x0004
  87. /* MII BCM5400 AUXSTATUS register */
  88. #define MII_BCM5400_AUXSTATUS 0x19
  89. #define MII_BCM5400_AUXSTATUS_LINKMODE_MASK 0x0700
  90. #define MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT 8
  91. /* 1000BT control (Marvell & BCM54xx at least) */
  92. #define MII_1000BASETCONTROL 0x09
  93. #define MII_1000BASETCONTROL_FULLDUPLEXCAP 0x0200
  94. #define MII_1000BASETCONTROL_HALFDUPLEXCAP 0x0100
  95. /* Marvell 88E1011 PHY control */
  96. #define MII_M1011_PHY_SPEC_CONTROL 0x10
  97. #define MII_M1011_PHY_SPEC_CONTROL_MANUAL_MDIX 0x20
  98. #define MII_M1011_PHY_SPEC_CONTROL_AUTO_MDIX 0x40
  99. /* Marvell 88E1011 PHY status */
  100. #define MII_M1011_PHY_SPEC_STATUS 0x11
  101. #define MII_M1011_PHY_SPEC_STATUS_1000 0x8000
  102. #define MII_M1011_PHY_SPEC_STATUS_100 0x4000
  103. #define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000
  104. #define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000
  105. #define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800
  106. #define MII_M1011_PHY_SPEC_STATUS_TX_PAUSE 0x0008
  107. #define MII_M1011_PHY_SPEC_STATUS_RX_PAUSE 0x0004
  108. #endif /* __SUNGEM_PHY_H__ */