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- /* SPDX-License-Identifier: GPL-2.0-only */
- /*
- * Copyright (c) 2015 MediaTek Inc.
- */
- #ifndef __MTK_MMSYS_H
- #define __MTK_MMSYS_H
- enum mtk_ddp_comp_id;
- struct device;
- enum mtk_ddp_comp_id {
- DDP_COMPONENT_AAL0,
- DDP_COMPONENT_AAL1,
- DDP_COMPONENT_BLS,
- DDP_COMPONENT_CCORR,
- DDP_COMPONENT_COLOR0,
- DDP_COMPONENT_COLOR1,
- DDP_COMPONENT_DITHER,
- DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
- DDP_COMPONENT_DITHER1,
- DDP_COMPONENT_DP_INTF0,
- DDP_COMPONENT_DP_INTF1,
- DDP_COMPONENT_DPI0,
- DDP_COMPONENT_DPI1,
- DDP_COMPONENT_DSC0,
- DDP_COMPONENT_DSC1,
- DDP_COMPONENT_DSI0,
- DDP_COMPONENT_DSI1,
- DDP_COMPONENT_DSI2,
- DDP_COMPONENT_DSI3,
- DDP_COMPONENT_GAMMA,
- DDP_COMPONENT_MERGE0,
- DDP_COMPONENT_MERGE1,
- DDP_COMPONENT_MERGE2,
- DDP_COMPONENT_MERGE3,
- DDP_COMPONENT_MERGE4,
- DDP_COMPONENT_MERGE5,
- DDP_COMPONENT_OD0,
- DDP_COMPONENT_OD1,
- DDP_COMPONENT_OVL0,
- DDP_COMPONENT_OVL_2L0,
- DDP_COMPONENT_OVL_2L1,
- DDP_COMPONENT_OVL_2L2,
- DDP_COMPONENT_OVL1,
- DDP_COMPONENT_POSTMASK0,
- DDP_COMPONENT_PWM0,
- DDP_COMPONENT_PWM1,
- DDP_COMPONENT_PWM2,
- DDP_COMPONENT_RDMA0,
- DDP_COMPONENT_RDMA1,
- DDP_COMPONENT_RDMA2,
- DDP_COMPONENT_RDMA4,
- DDP_COMPONENT_UFOE,
- DDP_COMPONENT_WDMA0,
- DDP_COMPONENT_WDMA1,
- DDP_COMPONENT_ID_MAX,
- };
- void mtk_mmsys_ddp_connect(struct device *dev,
- enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next);
- void mtk_mmsys_ddp_disconnect(struct device *dev,
- enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next);
- void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val);
- #endif /* __MTK_MMSYS_H */
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