sh_dma.h 3.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112
  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Header for the new SH dmaengine driver
  4. *
  5. * Copyright (C) 2010 Guennadi Liakhovetski <[email protected]>
  6. */
  7. #ifndef SH_DMA_H
  8. #define SH_DMA_H
  9. #include <linux/dmaengine.h>
  10. #include <linux/list.h>
  11. #include <linux/shdma-base.h>
  12. #include <linux/types.h>
  13. struct device;
  14. /* Used by slave DMA clients to request DMA to/from a specific peripheral */
  15. struct sh_dmae_slave {
  16. struct shdma_slave shdma_slave; /* Set by the platform */
  17. };
  18. /*
  19. * Supplied by platforms to specify, how a DMA channel has to be configured for
  20. * a certain peripheral
  21. */
  22. struct sh_dmae_slave_config {
  23. int slave_id;
  24. dma_addr_t addr;
  25. u32 chcr;
  26. char mid_rid;
  27. };
  28. /**
  29. * struct sh_dmae_channel - DMAC channel platform data
  30. * @offset: register offset within the main IOMEM resource
  31. * @dmars: channel DMARS register offset
  32. * @chclr_offset: channel CHCLR register offset
  33. * @dmars_bit: channel DMARS field offset within the register
  34. * @chclr_bit: bit position, to be set to reset the channel
  35. */
  36. struct sh_dmae_channel {
  37. unsigned int offset;
  38. unsigned int dmars;
  39. unsigned int chclr_offset;
  40. unsigned char dmars_bit;
  41. unsigned char chclr_bit;
  42. };
  43. /**
  44. * struct sh_dmae_pdata - DMAC platform data
  45. * @slave: array of slaves
  46. * @slave_num: number of slaves in the above array
  47. * @channel: array of DMA channels
  48. * @channel_num: number of channels in the above array
  49. * @ts_low_shift: shift of the low part of the TS field
  50. * @ts_low_mask: low TS field mask
  51. * @ts_high_shift: additional shift of the high part of the TS field
  52. * @ts_high_mask: high TS field mask
  53. * @ts_shift: array of Transfer Size shifts, indexed by TS value
  54. * @ts_shift_num: number of shifts in the above array
  55. * @dmaor_init: DMAOR initialisation value
  56. * @chcr_offset: CHCR address offset
  57. * @chcr_ie_bit: CHCR Interrupt Enable bit
  58. * @dmaor_is_32bit: DMAOR is a 32-bit register
  59. * @needs_tend_set: the TEND register has to be set
  60. * @no_dmars: DMAC has no DMARS registers
  61. * @chclr_present: DMAC has one or several CHCLR registers
  62. * @chclr_bitwise: channel CHCLR registers are bitwise
  63. * @slave_only: DMAC cannot be used for MEMCPY
  64. */
  65. struct sh_dmae_pdata {
  66. const struct sh_dmae_slave_config *slave;
  67. int slave_num;
  68. const struct sh_dmae_channel *channel;
  69. int channel_num;
  70. unsigned int ts_low_shift;
  71. unsigned int ts_low_mask;
  72. unsigned int ts_high_shift;
  73. unsigned int ts_high_mask;
  74. const unsigned int *ts_shift;
  75. int ts_shift_num;
  76. u16 dmaor_init;
  77. unsigned int chcr_offset;
  78. u32 chcr_ie_bit;
  79. unsigned int dmaor_is_32bit:1;
  80. unsigned int needs_tend_set:1;
  81. unsigned int no_dmars:1;
  82. unsigned int chclr_present:1;
  83. unsigned int chclr_bitwise:1;
  84. unsigned int slave_only:1;
  85. };
  86. /* DMAOR definitions */
  87. #define DMAOR_AE 0x00000004 /* Address Error Flag */
  88. #define DMAOR_NMIF 0x00000002
  89. #define DMAOR_DME 0x00000001 /* DMA Master Enable */
  90. /* Definitions for the SuperH DMAC */
  91. #define DM_INC 0x00004000 /* Destination addresses are incremented */
  92. #define DM_DEC 0x00008000 /* Destination addresses are decremented */
  93. #define DM_FIX 0x0000c000 /* Destination address is fixed */
  94. #define SM_INC 0x00001000 /* Source addresses are incremented */
  95. #define SM_DEC 0x00002000 /* Source addresses are decremented */
  96. #define SM_FIX 0x00003000 /* Source address is fixed */
  97. #define RS_AUTO 0x00000400 /* Auto Request */
  98. #define RS_ERS 0x00000800 /* DMA extended resource selector */
  99. #define CHCR_DE 0x00000001 /* DMA Enable */
  100. #define CHCR_TE 0x00000002 /* Transfer End Flag */
  101. #define CHCR_IE 0x00000004 /* Interrupt Enable */
  102. #endif