phy-lvds.h 945 B

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright 2020,2022 NXP
  4. */
  5. #ifndef __PHY_LVDS_H_
  6. #define __PHY_LVDS_H_
  7. /**
  8. * struct phy_configure_opts_lvds - LVDS configuration set
  9. * @bits_per_lane_and_dclk_cycle: Number of bits per lane per differential
  10. * clock cycle.
  11. * @differential_clk_rate: Clock rate, in Hertz, of the LVDS
  12. * differential clock.
  13. * @lanes: Number of active, consecutive,
  14. * data lanes, starting from lane 0,
  15. * used for the transmissions.
  16. * @is_slave: Boolean, true if the phy is a slave
  17. * which works together with a master
  18. * phy to support dual link transmission,
  19. * otherwise a regular phy or a master phy.
  20. *
  21. * This structure is used to represent the configuration state of a LVDS phy.
  22. */
  23. struct phy_configure_opts_lvds {
  24. unsigned int bits_per_lane_and_dclk_cycle;
  25. unsigned long differential_clk_rate;
  26. unsigned int lanes;
  27. bool is_slave;
  28. };
  29. #endif /* __PHY_LVDS_H_ */