nvme.h 44 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Definitions for the NVM Express interface
  4. * Copyright (c) 2011-2014, Intel Corporation.
  5. */
  6. #ifndef _LINUX_NVME_H
  7. #define _LINUX_NVME_H
  8. #include <linux/bits.h>
  9. #include <linux/types.h>
  10. #include <linux/uuid.h>
  11. /* NQN names in commands fields specified one size */
  12. #define NVMF_NQN_FIELD_LEN 256
  13. /* However the max length of a qualified name is another size */
  14. #define NVMF_NQN_SIZE 223
  15. #define NVMF_TRSVCID_SIZE 32
  16. #define NVMF_TRADDR_SIZE 256
  17. #define NVMF_TSAS_SIZE 256
  18. #define NVMF_AUTH_HASH_LEN 64
  19. #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
  20. #define NVME_RDMA_IP_PORT 4420
  21. #define NVME_NSID_ALL 0xffffffff
  22. enum nvme_subsys_type {
  23. /* Referral to another discovery type target subsystem */
  24. NVME_NQN_DISC = 1,
  25. /* NVME type target subsystem */
  26. NVME_NQN_NVME = 2,
  27. /* Current discovery type target subsystem */
  28. NVME_NQN_CURR = 3,
  29. };
  30. enum nvme_ctrl_type {
  31. NVME_CTRL_IO = 1, /* I/O controller */
  32. NVME_CTRL_DISC = 2, /* Discovery controller */
  33. NVME_CTRL_ADMIN = 3, /* Administrative controller */
  34. };
  35. enum nvme_dctype {
  36. NVME_DCTYPE_NOT_REPORTED = 0,
  37. NVME_DCTYPE_DDC = 1, /* Direct Discovery Controller */
  38. NVME_DCTYPE_CDC = 2, /* Central Discovery Controller */
  39. };
  40. /* Address Family codes for Discovery Log Page entry ADRFAM field */
  41. enum {
  42. NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
  43. NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
  44. NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
  45. NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
  46. NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
  47. NVMF_ADDR_FAMILY_LOOP = 254, /* Reserved for host usage */
  48. NVMF_ADDR_FAMILY_MAX,
  49. };
  50. /* Transport Type codes for Discovery Log Page entry TRTYPE field */
  51. enum {
  52. NVMF_TRTYPE_RDMA = 1, /* RDMA */
  53. NVMF_TRTYPE_FC = 2, /* Fibre Channel */
  54. NVMF_TRTYPE_TCP = 3, /* TCP/IP */
  55. NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
  56. NVMF_TRTYPE_MAX,
  57. };
  58. /* Transport Requirements codes for Discovery Log Page entry TREQ field */
  59. enum {
  60. NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
  61. NVMF_TREQ_REQUIRED = 1, /* Required */
  62. NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
  63. #define NVME_TREQ_SECURE_CHANNEL_MASK \
  64. (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
  65. NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */
  66. };
  67. /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
  68. * RDMA_QPTYPE field
  69. */
  70. enum {
  71. NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */
  72. NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */
  73. };
  74. /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
  75. * RDMA_QPTYPE field
  76. */
  77. enum {
  78. NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */
  79. NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */
  80. NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */
  81. NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */
  82. NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */
  83. };
  84. /* RDMA Connection Management Service Type codes for Discovery Log Page
  85. * entry TSAS RDMA_CMS field
  86. */
  87. enum {
  88. NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */
  89. };
  90. #define NVME_AQ_DEPTH 32
  91. #define NVME_NR_AEN_COMMANDS 1
  92. #define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
  93. /*
  94. * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
  95. * NVM-Express 1.2 specification, section 4.1.2.
  96. */
  97. #define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1)
  98. enum {
  99. NVME_REG_CAP = 0x0000, /* Controller Capabilities */
  100. NVME_REG_VS = 0x0008, /* Version */
  101. NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
  102. NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
  103. NVME_REG_CC = 0x0014, /* Controller Configuration */
  104. NVME_REG_CSTS = 0x001c, /* Controller Status */
  105. NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
  106. NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
  107. NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
  108. NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
  109. NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
  110. NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
  111. NVME_REG_BPINFO = 0x0040, /* Boot Partition Information */
  112. NVME_REG_BPRSEL = 0x0044, /* Boot Partition Read Select */
  113. NVME_REG_BPMBL = 0x0048, /* Boot Partition Memory Buffer
  114. * Location
  115. */
  116. NVME_REG_CMBMSC = 0x0050, /* Controller Memory Buffer Memory
  117. * Space Control
  118. */
  119. NVME_REG_CRTO = 0x0068, /* Controller Ready Timeouts */
  120. NVME_REG_PMRCAP = 0x0e00, /* Persistent Memory Capabilities */
  121. NVME_REG_PMRCTL = 0x0e04, /* Persistent Memory Region Control */
  122. NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */
  123. NVME_REG_PMREBS = 0x0e0c, /* Persistent Memory Region Elasticity
  124. * Buffer Size
  125. */
  126. NVME_REG_PMRSWTP = 0x0e10, /* Persistent Memory Region Sustained
  127. * Write Throughput
  128. */
  129. NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
  130. };
  131. #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
  132. #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
  133. #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
  134. #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
  135. #define NVME_CAP_CSS(cap) (((cap) >> 37) & 0xff)
  136. #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
  137. #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
  138. #define NVME_CAP_CMBS(cap) (((cap) >> 57) & 0x1)
  139. #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
  140. #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
  141. #define NVME_CRTO_CRIMT(crto) ((crto) >> 16)
  142. #define NVME_CRTO_CRWMT(crto) ((crto) & 0xffff)
  143. enum {
  144. NVME_CMBSZ_SQS = 1 << 0,
  145. NVME_CMBSZ_CQS = 1 << 1,
  146. NVME_CMBSZ_LISTS = 1 << 2,
  147. NVME_CMBSZ_RDS = 1 << 3,
  148. NVME_CMBSZ_WDS = 1 << 4,
  149. NVME_CMBSZ_SZ_SHIFT = 12,
  150. NVME_CMBSZ_SZ_MASK = 0xfffff,
  151. NVME_CMBSZ_SZU_SHIFT = 8,
  152. NVME_CMBSZ_SZU_MASK = 0xf,
  153. };
  154. /*
  155. * Submission and Completion Queue Entry Sizes for the NVM command set.
  156. * (In bytes and specified as a power of two (2^n)).
  157. */
  158. #define NVME_ADM_SQES 6
  159. #define NVME_NVM_IOSQES 6
  160. #define NVME_NVM_IOCQES 4
  161. enum {
  162. NVME_CC_ENABLE = 1 << 0,
  163. NVME_CC_EN_SHIFT = 0,
  164. NVME_CC_CSS_SHIFT = 4,
  165. NVME_CC_MPS_SHIFT = 7,
  166. NVME_CC_AMS_SHIFT = 11,
  167. NVME_CC_SHN_SHIFT = 14,
  168. NVME_CC_IOSQES_SHIFT = 16,
  169. NVME_CC_IOCQES_SHIFT = 20,
  170. NVME_CC_CSS_NVM = 0 << NVME_CC_CSS_SHIFT,
  171. NVME_CC_CSS_CSI = 6 << NVME_CC_CSS_SHIFT,
  172. NVME_CC_CSS_MASK = 7 << NVME_CC_CSS_SHIFT,
  173. NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT,
  174. NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT,
  175. NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT,
  176. NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT,
  177. NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT,
  178. NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT,
  179. NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT,
  180. NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
  181. NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
  182. NVME_CC_CRIME = 1 << 24,
  183. };
  184. enum {
  185. NVME_CSTS_RDY = 1 << 0,
  186. NVME_CSTS_CFS = 1 << 1,
  187. NVME_CSTS_NSSRO = 1 << 4,
  188. NVME_CSTS_PP = 1 << 5,
  189. NVME_CSTS_SHST_NORMAL = 0 << 2,
  190. NVME_CSTS_SHST_OCCUR = 1 << 2,
  191. NVME_CSTS_SHST_CMPLT = 2 << 2,
  192. NVME_CSTS_SHST_MASK = 3 << 2,
  193. };
  194. enum {
  195. NVME_CMBMSC_CRE = 1 << 0,
  196. NVME_CMBMSC_CMSE = 1 << 1,
  197. };
  198. enum {
  199. NVME_CAP_CSS_NVM = 1 << 0,
  200. NVME_CAP_CSS_CSI = 1 << 6,
  201. };
  202. enum {
  203. NVME_CAP_CRMS_CRWMS = 1ULL << 59,
  204. NVME_CAP_CRMS_CRIMS = 1ULL << 60,
  205. };
  206. struct nvme_id_power_state {
  207. __le16 max_power; /* centiwatts */
  208. __u8 rsvd2;
  209. __u8 flags;
  210. __le32 entry_lat; /* microseconds */
  211. __le32 exit_lat; /* microseconds */
  212. __u8 read_tput;
  213. __u8 read_lat;
  214. __u8 write_tput;
  215. __u8 write_lat;
  216. __le16 idle_power;
  217. __u8 idle_scale;
  218. __u8 rsvd19;
  219. __le16 active_power;
  220. __u8 active_work_scale;
  221. __u8 rsvd23[9];
  222. };
  223. enum {
  224. NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
  225. NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
  226. };
  227. enum nvme_ctrl_attr {
  228. NVME_CTRL_ATTR_HID_128_BIT = (1 << 0),
  229. NVME_CTRL_ATTR_TBKAS = (1 << 6),
  230. NVME_CTRL_ATTR_ELBAS = (1 << 15),
  231. };
  232. struct nvme_id_ctrl {
  233. __le16 vid;
  234. __le16 ssvid;
  235. char sn[20];
  236. char mn[40];
  237. char fr[8];
  238. __u8 rab;
  239. __u8 ieee[3];
  240. __u8 cmic;
  241. __u8 mdts;
  242. __le16 cntlid;
  243. __le32 ver;
  244. __le32 rtd3r;
  245. __le32 rtd3e;
  246. __le32 oaes;
  247. __le32 ctratt;
  248. __u8 rsvd100[11];
  249. __u8 cntrltype;
  250. __u8 fguid[16];
  251. __le16 crdt1;
  252. __le16 crdt2;
  253. __le16 crdt3;
  254. __u8 rsvd134[122];
  255. __le16 oacs;
  256. __u8 acl;
  257. __u8 aerl;
  258. __u8 frmw;
  259. __u8 lpa;
  260. __u8 elpe;
  261. __u8 npss;
  262. __u8 avscc;
  263. __u8 apsta;
  264. __le16 wctemp;
  265. __le16 cctemp;
  266. __le16 mtfa;
  267. __le32 hmpre;
  268. __le32 hmmin;
  269. __u8 tnvmcap[16];
  270. __u8 unvmcap[16];
  271. __le32 rpmbs;
  272. __le16 edstt;
  273. __u8 dsto;
  274. __u8 fwug;
  275. __le16 kas;
  276. __le16 hctma;
  277. __le16 mntmt;
  278. __le16 mxtmt;
  279. __le32 sanicap;
  280. __le32 hmminds;
  281. __le16 hmmaxd;
  282. __u8 rsvd338[4];
  283. __u8 anatt;
  284. __u8 anacap;
  285. __le32 anagrpmax;
  286. __le32 nanagrpid;
  287. __u8 rsvd352[160];
  288. __u8 sqes;
  289. __u8 cqes;
  290. __le16 maxcmd;
  291. __le32 nn;
  292. __le16 oncs;
  293. __le16 fuses;
  294. __u8 fna;
  295. __u8 vwc;
  296. __le16 awun;
  297. __le16 awupf;
  298. __u8 nvscc;
  299. __u8 nwpc;
  300. __le16 acwu;
  301. __u8 rsvd534[2];
  302. __le32 sgls;
  303. __le32 mnan;
  304. __u8 rsvd544[224];
  305. char subnqn[256];
  306. __u8 rsvd1024[768];
  307. __le32 ioccsz;
  308. __le32 iorcsz;
  309. __le16 icdoff;
  310. __u8 ctrattr;
  311. __u8 msdbd;
  312. __u8 rsvd1804[2];
  313. __u8 dctype;
  314. __u8 rsvd1807[241];
  315. struct nvme_id_power_state psd[32];
  316. __u8 vs[1024];
  317. };
  318. enum {
  319. NVME_CTRL_CMIC_MULTI_PORT = 1 << 0,
  320. NVME_CTRL_CMIC_MULTI_CTRL = 1 << 1,
  321. NVME_CTRL_CMIC_ANA = 1 << 3,
  322. NVME_CTRL_ONCS_COMPARE = 1 << 0,
  323. NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
  324. NVME_CTRL_ONCS_DSM = 1 << 2,
  325. NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
  326. NVME_CTRL_ONCS_RESERVATIONS = 1 << 5,
  327. NVME_CTRL_ONCS_TIMESTAMP = 1 << 6,
  328. NVME_CTRL_VWC_PRESENT = 1 << 0,
  329. NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
  330. NVME_CTRL_OACS_NS_MNGT_SUPP = 1 << 3,
  331. NVME_CTRL_OACS_DIRECTIVES = 1 << 5,
  332. NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8,
  333. NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1,
  334. NVME_CTRL_CTRATT_128_ID = 1 << 0,
  335. NVME_CTRL_CTRATT_NON_OP_PSP = 1 << 1,
  336. NVME_CTRL_CTRATT_NVM_SETS = 1 << 2,
  337. NVME_CTRL_CTRATT_READ_RECV_LVLS = 1 << 3,
  338. NVME_CTRL_CTRATT_ENDURANCE_GROUPS = 1 << 4,
  339. NVME_CTRL_CTRATT_PREDICTABLE_LAT = 1 << 5,
  340. NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY = 1 << 7,
  341. NVME_CTRL_CTRATT_UUID_LIST = 1 << 9,
  342. };
  343. struct nvme_lbaf {
  344. __le16 ms;
  345. __u8 ds;
  346. __u8 rp;
  347. };
  348. struct nvme_id_ns {
  349. __le64 nsze;
  350. __le64 ncap;
  351. __le64 nuse;
  352. __u8 nsfeat;
  353. __u8 nlbaf;
  354. __u8 flbas;
  355. __u8 mc;
  356. __u8 dpc;
  357. __u8 dps;
  358. __u8 nmic;
  359. __u8 rescap;
  360. __u8 fpi;
  361. __u8 dlfeat;
  362. __le16 nawun;
  363. __le16 nawupf;
  364. __le16 nacwu;
  365. __le16 nabsn;
  366. __le16 nabo;
  367. __le16 nabspf;
  368. __le16 noiob;
  369. __u8 nvmcap[16];
  370. __le16 npwg;
  371. __le16 npwa;
  372. __le16 npdg;
  373. __le16 npda;
  374. __le16 nows;
  375. __u8 rsvd74[18];
  376. __le32 anagrpid;
  377. __u8 rsvd96[3];
  378. __u8 nsattr;
  379. __le16 nvmsetid;
  380. __le16 endgid;
  381. __u8 nguid[16];
  382. __u8 eui64[8];
  383. struct nvme_lbaf lbaf[64];
  384. __u8 vs[3712];
  385. };
  386. /* I/O Command Set Independent Identify Namespace Data Structure */
  387. struct nvme_id_ns_cs_indep {
  388. __u8 nsfeat;
  389. __u8 nmic;
  390. __u8 rescap;
  391. __u8 fpi;
  392. __le32 anagrpid;
  393. __u8 nsattr;
  394. __u8 rsvd9;
  395. __le16 nvmsetid;
  396. __le16 endgid;
  397. __u8 nstat;
  398. __u8 rsvd15[4081];
  399. };
  400. struct nvme_zns_lbafe {
  401. __le64 zsze;
  402. __u8 zdes;
  403. __u8 rsvd9[7];
  404. };
  405. struct nvme_id_ns_zns {
  406. __le16 zoc;
  407. __le16 ozcs;
  408. __le32 mar;
  409. __le32 mor;
  410. __le32 rrl;
  411. __le32 frl;
  412. __u8 rsvd20[2796];
  413. struct nvme_zns_lbafe lbafe[64];
  414. __u8 vs[256];
  415. };
  416. struct nvme_id_ctrl_zns {
  417. __u8 zasl;
  418. __u8 rsvd1[4095];
  419. };
  420. struct nvme_id_ns_nvm {
  421. __le64 lbstm;
  422. __u8 pic;
  423. __u8 rsvd9[3];
  424. __le32 elbaf[64];
  425. __u8 rsvd268[3828];
  426. };
  427. enum {
  428. NVME_ID_NS_NVM_STS_MASK = 0x7f,
  429. NVME_ID_NS_NVM_GUARD_SHIFT = 7,
  430. NVME_ID_NS_NVM_GUARD_MASK = 0x3,
  431. };
  432. static inline __u8 nvme_elbaf_sts(__u32 elbaf)
  433. {
  434. return elbaf & NVME_ID_NS_NVM_STS_MASK;
  435. }
  436. static inline __u8 nvme_elbaf_guard_type(__u32 elbaf)
  437. {
  438. return (elbaf >> NVME_ID_NS_NVM_GUARD_SHIFT) & NVME_ID_NS_NVM_GUARD_MASK;
  439. }
  440. struct nvme_id_ctrl_nvm {
  441. __u8 vsl;
  442. __u8 wzsl;
  443. __u8 wusl;
  444. __u8 dmrl;
  445. __le32 dmrsl;
  446. __le64 dmsl;
  447. __u8 rsvd16[4080];
  448. };
  449. enum {
  450. NVME_ID_CNS_NS = 0x00,
  451. NVME_ID_CNS_CTRL = 0x01,
  452. NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
  453. NVME_ID_CNS_NS_DESC_LIST = 0x03,
  454. NVME_ID_CNS_CS_NS = 0x05,
  455. NVME_ID_CNS_CS_CTRL = 0x06,
  456. NVME_ID_CNS_NS_CS_INDEP = 0x08,
  457. NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
  458. NVME_ID_CNS_NS_PRESENT = 0x11,
  459. NVME_ID_CNS_CTRL_NS_LIST = 0x12,
  460. NVME_ID_CNS_CTRL_LIST = 0x13,
  461. NVME_ID_CNS_SCNDRY_CTRL_LIST = 0x15,
  462. NVME_ID_CNS_NS_GRANULARITY = 0x16,
  463. NVME_ID_CNS_UUID_LIST = 0x17,
  464. };
  465. enum {
  466. NVME_CSI_NVM = 0,
  467. NVME_CSI_ZNS = 2,
  468. };
  469. enum {
  470. NVME_DIR_IDENTIFY = 0x00,
  471. NVME_DIR_STREAMS = 0x01,
  472. NVME_DIR_SND_ID_OP_ENABLE = 0x01,
  473. NVME_DIR_SND_ST_OP_REL_ID = 0x01,
  474. NVME_DIR_SND_ST_OP_REL_RSC = 0x02,
  475. NVME_DIR_RCV_ID_OP_PARAM = 0x01,
  476. NVME_DIR_RCV_ST_OP_PARAM = 0x01,
  477. NVME_DIR_RCV_ST_OP_STATUS = 0x02,
  478. NVME_DIR_RCV_ST_OP_RESOURCE = 0x03,
  479. NVME_DIR_ENDIR = 0x01,
  480. };
  481. enum {
  482. NVME_NS_FEAT_THIN = 1 << 0,
  483. NVME_NS_FEAT_ATOMICS = 1 << 1,
  484. NVME_NS_FEAT_IO_OPT = 1 << 4,
  485. NVME_NS_ATTR_RO = 1 << 0,
  486. NVME_NS_FLBAS_LBA_MASK = 0xf,
  487. NVME_NS_FLBAS_LBA_UMASK = 0x60,
  488. NVME_NS_FLBAS_LBA_SHIFT = 1,
  489. NVME_NS_FLBAS_META_EXT = 0x10,
  490. NVME_NS_NMIC_SHARED = 1 << 0,
  491. NVME_LBAF_RP_BEST = 0,
  492. NVME_LBAF_RP_BETTER = 1,
  493. NVME_LBAF_RP_GOOD = 2,
  494. NVME_LBAF_RP_DEGRADED = 3,
  495. NVME_NS_DPC_PI_LAST = 1 << 4,
  496. NVME_NS_DPC_PI_FIRST = 1 << 3,
  497. NVME_NS_DPC_PI_TYPE3 = 1 << 2,
  498. NVME_NS_DPC_PI_TYPE2 = 1 << 1,
  499. NVME_NS_DPC_PI_TYPE1 = 1 << 0,
  500. NVME_NS_DPS_PI_FIRST = 1 << 3,
  501. NVME_NS_DPS_PI_MASK = 0x7,
  502. NVME_NS_DPS_PI_TYPE1 = 1,
  503. NVME_NS_DPS_PI_TYPE2 = 2,
  504. NVME_NS_DPS_PI_TYPE3 = 3,
  505. };
  506. enum {
  507. NVME_NSTAT_NRDY = 1 << 0,
  508. };
  509. enum {
  510. NVME_NVM_NS_16B_GUARD = 0,
  511. NVME_NVM_NS_32B_GUARD = 1,
  512. NVME_NVM_NS_64B_GUARD = 2,
  513. };
  514. static inline __u8 nvme_lbaf_index(__u8 flbas)
  515. {
  516. return (flbas & NVME_NS_FLBAS_LBA_MASK) |
  517. ((flbas & NVME_NS_FLBAS_LBA_UMASK) >> NVME_NS_FLBAS_LBA_SHIFT);
  518. }
  519. /* Identify Namespace Metadata Capabilities (MC): */
  520. enum {
  521. NVME_MC_EXTENDED_LBA = (1 << 0),
  522. NVME_MC_METADATA_PTR = (1 << 1),
  523. };
  524. struct nvme_ns_id_desc {
  525. __u8 nidt;
  526. __u8 nidl;
  527. __le16 reserved;
  528. };
  529. #define NVME_NIDT_EUI64_LEN 8
  530. #define NVME_NIDT_NGUID_LEN 16
  531. #define NVME_NIDT_UUID_LEN 16
  532. #define NVME_NIDT_CSI_LEN 1
  533. enum {
  534. NVME_NIDT_EUI64 = 0x01,
  535. NVME_NIDT_NGUID = 0x02,
  536. NVME_NIDT_UUID = 0x03,
  537. NVME_NIDT_CSI = 0x04,
  538. };
  539. struct nvme_smart_log {
  540. __u8 critical_warning;
  541. __u8 temperature[2];
  542. __u8 avail_spare;
  543. __u8 spare_thresh;
  544. __u8 percent_used;
  545. __u8 endu_grp_crit_warn_sumry;
  546. __u8 rsvd7[25];
  547. __u8 data_units_read[16];
  548. __u8 data_units_written[16];
  549. __u8 host_reads[16];
  550. __u8 host_writes[16];
  551. __u8 ctrl_busy_time[16];
  552. __u8 power_cycles[16];
  553. __u8 power_on_hours[16];
  554. __u8 unsafe_shutdowns[16];
  555. __u8 media_errors[16];
  556. __u8 num_err_log_entries[16];
  557. __le32 warning_temp_time;
  558. __le32 critical_comp_time;
  559. __le16 temp_sensor[8];
  560. __le32 thm_temp1_trans_count;
  561. __le32 thm_temp2_trans_count;
  562. __le32 thm_temp1_total_time;
  563. __le32 thm_temp2_total_time;
  564. __u8 rsvd232[280];
  565. };
  566. struct nvme_fw_slot_info_log {
  567. __u8 afi;
  568. __u8 rsvd1[7];
  569. __le64 frs[7];
  570. __u8 rsvd64[448];
  571. };
  572. enum {
  573. NVME_CMD_EFFECTS_CSUPP = 1 << 0,
  574. NVME_CMD_EFFECTS_LBCC = 1 << 1,
  575. NVME_CMD_EFFECTS_NCC = 1 << 2,
  576. NVME_CMD_EFFECTS_NIC = 1 << 3,
  577. NVME_CMD_EFFECTS_CCC = 1 << 4,
  578. NVME_CMD_EFFECTS_CSE_MASK = GENMASK(18, 16),
  579. NVME_CMD_EFFECTS_UUID_SEL = 1 << 19,
  580. };
  581. struct nvme_effects_log {
  582. __le32 acs[256];
  583. __le32 iocs[256];
  584. __u8 resv[2048];
  585. };
  586. enum nvme_ana_state {
  587. NVME_ANA_OPTIMIZED = 0x01,
  588. NVME_ANA_NONOPTIMIZED = 0x02,
  589. NVME_ANA_INACCESSIBLE = 0x03,
  590. NVME_ANA_PERSISTENT_LOSS = 0x04,
  591. NVME_ANA_CHANGE = 0x0f,
  592. };
  593. struct nvme_ana_group_desc {
  594. __le32 grpid;
  595. __le32 nnsids;
  596. __le64 chgcnt;
  597. __u8 state;
  598. __u8 rsvd17[15];
  599. __le32 nsids[];
  600. };
  601. /* flag for the log specific field of the ANA log */
  602. #define NVME_ANA_LOG_RGO (1 << 0)
  603. struct nvme_ana_rsp_hdr {
  604. __le64 chgcnt;
  605. __le16 ngrps;
  606. __le16 rsvd10[3];
  607. };
  608. struct nvme_zone_descriptor {
  609. __u8 zt;
  610. __u8 zs;
  611. __u8 za;
  612. __u8 rsvd3[5];
  613. __le64 zcap;
  614. __le64 zslba;
  615. __le64 wp;
  616. __u8 rsvd32[32];
  617. };
  618. enum {
  619. NVME_ZONE_TYPE_SEQWRITE_REQ = 0x2,
  620. };
  621. struct nvme_zone_report {
  622. __le64 nr_zones;
  623. __u8 resv8[56];
  624. struct nvme_zone_descriptor entries[];
  625. };
  626. enum {
  627. NVME_SMART_CRIT_SPARE = 1 << 0,
  628. NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
  629. NVME_SMART_CRIT_RELIABILITY = 1 << 2,
  630. NVME_SMART_CRIT_MEDIA = 1 << 3,
  631. NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
  632. };
  633. enum {
  634. NVME_AER_ERROR = 0,
  635. NVME_AER_SMART = 1,
  636. NVME_AER_NOTICE = 2,
  637. NVME_AER_CSS = 6,
  638. NVME_AER_VS = 7,
  639. };
  640. enum {
  641. NVME_AER_ERROR_PERSIST_INT_ERR = 0x03,
  642. };
  643. enum {
  644. NVME_AER_NOTICE_NS_CHANGED = 0x00,
  645. NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
  646. NVME_AER_NOTICE_ANA = 0x03,
  647. NVME_AER_NOTICE_DISC_CHANGED = 0xf0,
  648. };
  649. enum {
  650. NVME_AEN_BIT_NS_ATTR = 8,
  651. NVME_AEN_BIT_FW_ACT = 9,
  652. NVME_AEN_BIT_ANA_CHANGE = 11,
  653. NVME_AEN_BIT_DISC_CHANGE = 31,
  654. };
  655. enum {
  656. NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR,
  657. NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT,
  658. NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE,
  659. NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE,
  660. };
  661. struct nvme_lba_range_type {
  662. __u8 type;
  663. __u8 attributes;
  664. __u8 rsvd2[14];
  665. __le64 slba;
  666. __le64 nlb;
  667. __u8 guid[16];
  668. __u8 rsvd48[16];
  669. };
  670. enum {
  671. NVME_LBART_TYPE_FS = 0x01,
  672. NVME_LBART_TYPE_RAID = 0x02,
  673. NVME_LBART_TYPE_CACHE = 0x03,
  674. NVME_LBART_TYPE_SWAP = 0x04,
  675. NVME_LBART_ATTRIB_TEMP = 1 << 0,
  676. NVME_LBART_ATTRIB_HIDE = 1 << 1,
  677. };
  678. struct nvme_reservation_status {
  679. __le32 gen;
  680. __u8 rtype;
  681. __u8 regctl[2];
  682. __u8 resv5[2];
  683. __u8 ptpls;
  684. __u8 resv10[13];
  685. struct {
  686. __le16 cntlid;
  687. __u8 rcsts;
  688. __u8 resv3[5];
  689. __le64 hostid;
  690. __le64 rkey;
  691. } regctl_ds[];
  692. };
  693. enum nvme_async_event_type {
  694. NVME_AER_TYPE_ERROR = 0,
  695. NVME_AER_TYPE_SMART = 1,
  696. NVME_AER_TYPE_NOTICE = 2,
  697. };
  698. /* I/O commands */
  699. enum nvme_opcode {
  700. nvme_cmd_flush = 0x00,
  701. nvme_cmd_write = 0x01,
  702. nvme_cmd_read = 0x02,
  703. nvme_cmd_write_uncor = 0x04,
  704. nvme_cmd_compare = 0x05,
  705. nvme_cmd_write_zeroes = 0x08,
  706. nvme_cmd_dsm = 0x09,
  707. nvme_cmd_verify = 0x0c,
  708. nvme_cmd_resv_register = 0x0d,
  709. nvme_cmd_resv_report = 0x0e,
  710. nvme_cmd_resv_acquire = 0x11,
  711. nvme_cmd_resv_release = 0x15,
  712. nvme_cmd_zone_mgmt_send = 0x79,
  713. nvme_cmd_zone_mgmt_recv = 0x7a,
  714. nvme_cmd_zone_append = 0x7d,
  715. };
  716. #define nvme_opcode_name(opcode) { opcode, #opcode }
  717. #define show_nvm_opcode_name(val) \
  718. __print_symbolic(val, \
  719. nvme_opcode_name(nvme_cmd_flush), \
  720. nvme_opcode_name(nvme_cmd_write), \
  721. nvme_opcode_name(nvme_cmd_read), \
  722. nvme_opcode_name(nvme_cmd_write_uncor), \
  723. nvme_opcode_name(nvme_cmd_compare), \
  724. nvme_opcode_name(nvme_cmd_write_zeroes), \
  725. nvme_opcode_name(nvme_cmd_dsm), \
  726. nvme_opcode_name(nvme_cmd_resv_register), \
  727. nvme_opcode_name(nvme_cmd_resv_report), \
  728. nvme_opcode_name(nvme_cmd_resv_acquire), \
  729. nvme_opcode_name(nvme_cmd_resv_release), \
  730. nvme_opcode_name(nvme_cmd_zone_mgmt_send), \
  731. nvme_opcode_name(nvme_cmd_zone_mgmt_recv), \
  732. nvme_opcode_name(nvme_cmd_zone_append))
  733. /*
  734. * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
  735. *
  736. * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
  737. * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
  738. * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
  739. * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
  740. * request subtype
  741. */
  742. enum {
  743. NVME_SGL_FMT_ADDRESS = 0x00,
  744. NVME_SGL_FMT_OFFSET = 0x01,
  745. NVME_SGL_FMT_TRANSPORT_A = 0x0A,
  746. NVME_SGL_FMT_INVALIDATE = 0x0f,
  747. };
  748. /*
  749. * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
  750. *
  751. * For struct nvme_sgl_desc:
  752. * @NVME_SGL_FMT_DATA_DESC: data block descriptor
  753. * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
  754. * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
  755. *
  756. * For struct nvme_keyed_sgl_desc:
  757. * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
  758. *
  759. * Transport-specific SGL types:
  760. * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor
  761. */
  762. enum {
  763. NVME_SGL_FMT_DATA_DESC = 0x00,
  764. NVME_SGL_FMT_SEG_DESC = 0x02,
  765. NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
  766. NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
  767. NVME_TRANSPORT_SGL_DATA_DESC = 0x05,
  768. };
  769. struct nvme_sgl_desc {
  770. __le64 addr;
  771. __le32 length;
  772. __u8 rsvd[3];
  773. __u8 type;
  774. };
  775. struct nvme_keyed_sgl_desc {
  776. __le64 addr;
  777. __u8 length[3];
  778. __u8 key[4];
  779. __u8 type;
  780. };
  781. union nvme_data_ptr {
  782. struct {
  783. __le64 prp1;
  784. __le64 prp2;
  785. };
  786. struct nvme_sgl_desc sgl;
  787. struct nvme_keyed_sgl_desc ksgl;
  788. };
  789. /*
  790. * Lowest two bits of our flags field (FUSE field in the spec):
  791. *
  792. * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
  793. * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
  794. *
  795. * Highest two bits in our flags field (PSDT field in the spec):
  796. *
  797. * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
  798. * If used, MPTR contains addr of single physical buffer (byte aligned).
  799. * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
  800. * If used, MPTR contains an address of an SGL segment containing
  801. * exactly 1 SGL descriptor (qword aligned).
  802. */
  803. enum {
  804. NVME_CMD_FUSE_FIRST = (1 << 0),
  805. NVME_CMD_FUSE_SECOND = (1 << 1),
  806. NVME_CMD_SGL_METABUF = (1 << 6),
  807. NVME_CMD_SGL_METASEG = (1 << 7),
  808. NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
  809. };
  810. struct nvme_common_command {
  811. __u8 opcode;
  812. __u8 flags;
  813. __u16 command_id;
  814. __le32 nsid;
  815. __le32 cdw2[2];
  816. __le64 metadata;
  817. union nvme_data_ptr dptr;
  818. struct_group(cdws,
  819. __le32 cdw10;
  820. __le32 cdw11;
  821. __le32 cdw12;
  822. __le32 cdw13;
  823. __le32 cdw14;
  824. __le32 cdw15;
  825. );
  826. };
  827. struct nvme_rw_command {
  828. __u8 opcode;
  829. __u8 flags;
  830. __u16 command_id;
  831. __le32 nsid;
  832. __le32 cdw2;
  833. __le32 cdw3;
  834. __le64 metadata;
  835. union nvme_data_ptr dptr;
  836. __le64 slba;
  837. __le16 length;
  838. __le16 control;
  839. __le32 dsmgmt;
  840. __le32 reftag;
  841. __le16 apptag;
  842. __le16 appmask;
  843. };
  844. enum {
  845. NVME_RW_LR = 1 << 15,
  846. NVME_RW_FUA = 1 << 14,
  847. NVME_RW_APPEND_PIREMAP = 1 << 9,
  848. NVME_RW_DSM_FREQ_UNSPEC = 0,
  849. NVME_RW_DSM_FREQ_TYPICAL = 1,
  850. NVME_RW_DSM_FREQ_RARE = 2,
  851. NVME_RW_DSM_FREQ_READS = 3,
  852. NVME_RW_DSM_FREQ_WRITES = 4,
  853. NVME_RW_DSM_FREQ_RW = 5,
  854. NVME_RW_DSM_FREQ_ONCE = 6,
  855. NVME_RW_DSM_FREQ_PREFETCH = 7,
  856. NVME_RW_DSM_FREQ_TEMP = 8,
  857. NVME_RW_DSM_LATENCY_NONE = 0 << 4,
  858. NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
  859. NVME_RW_DSM_LATENCY_NORM = 2 << 4,
  860. NVME_RW_DSM_LATENCY_LOW = 3 << 4,
  861. NVME_RW_DSM_SEQ_REQ = 1 << 6,
  862. NVME_RW_DSM_COMPRESSED = 1 << 7,
  863. NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
  864. NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
  865. NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
  866. NVME_RW_PRINFO_PRACT = 1 << 13,
  867. NVME_RW_DTYPE_STREAMS = 1 << 4,
  868. };
  869. struct nvme_dsm_cmd {
  870. __u8 opcode;
  871. __u8 flags;
  872. __u16 command_id;
  873. __le32 nsid;
  874. __u64 rsvd2[2];
  875. union nvme_data_ptr dptr;
  876. __le32 nr;
  877. __le32 attributes;
  878. __u32 rsvd12[4];
  879. };
  880. enum {
  881. NVME_DSMGMT_IDR = 1 << 0,
  882. NVME_DSMGMT_IDW = 1 << 1,
  883. NVME_DSMGMT_AD = 1 << 2,
  884. };
  885. #define NVME_DSM_MAX_RANGES 256
  886. struct nvme_dsm_range {
  887. __le32 cattr;
  888. __le32 nlb;
  889. __le64 slba;
  890. };
  891. struct nvme_write_zeroes_cmd {
  892. __u8 opcode;
  893. __u8 flags;
  894. __u16 command_id;
  895. __le32 nsid;
  896. __u64 rsvd2;
  897. __le64 metadata;
  898. union nvme_data_ptr dptr;
  899. __le64 slba;
  900. __le16 length;
  901. __le16 control;
  902. __le32 dsmgmt;
  903. __le32 reftag;
  904. __le16 apptag;
  905. __le16 appmask;
  906. };
  907. enum nvme_zone_mgmt_action {
  908. NVME_ZONE_CLOSE = 0x1,
  909. NVME_ZONE_FINISH = 0x2,
  910. NVME_ZONE_OPEN = 0x3,
  911. NVME_ZONE_RESET = 0x4,
  912. NVME_ZONE_OFFLINE = 0x5,
  913. NVME_ZONE_SET_DESC_EXT = 0x10,
  914. };
  915. struct nvme_zone_mgmt_send_cmd {
  916. __u8 opcode;
  917. __u8 flags;
  918. __u16 command_id;
  919. __le32 nsid;
  920. __le32 cdw2[2];
  921. __le64 metadata;
  922. union nvme_data_ptr dptr;
  923. __le64 slba;
  924. __le32 cdw12;
  925. __u8 zsa;
  926. __u8 select_all;
  927. __u8 rsvd13[2];
  928. __le32 cdw14[2];
  929. };
  930. struct nvme_zone_mgmt_recv_cmd {
  931. __u8 opcode;
  932. __u8 flags;
  933. __u16 command_id;
  934. __le32 nsid;
  935. __le64 rsvd2[2];
  936. union nvme_data_ptr dptr;
  937. __le64 slba;
  938. __le32 numd;
  939. __u8 zra;
  940. __u8 zrasf;
  941. __u8 pr;
  942. __u8 rsvd13;
  943. __le32 cdw14[2];
  944. };
  945. enum {
  946. NVME_ZRA_ZONE_REPORT = 0,
  947. NVME_ZRASF_ZONE_REPORT_ALL = 0,
  948. NVME_ZRASF_ZONE_STATE_EMPTY = 0x01,
  949. NVME_ZRASF_ZONE_STATE_IMP_OPEN = 0x02,
  950. NVME_ZRASF_ZONE_STATE_EXP_OPEN = 0x03,
  951. NVME_ZRASF_ZONE_STATE_CLOSED = 0x04,
  952. NVME_ZRASF_ZONE_STATE_READONLY = 0x05,
  953. NVME_ZRASF_ZONE_STATE_FULL = 0x06,
  954. NVME_ZRASF_ZONE_STATE_OFFLINE = 0x07,
  955. NVME_REPORT_ZONE_PARTIAL = 1,
  956. };
  957. /* Features */
  958. enum {
  959. NVME_TEMP_THRESH_MASK = 0xffff,
  960. NVME_TEMP_THRESH_SELECT_SHIFT = 16,
  961. NVME_TEMP_THRESH_TYPE_UNDER = 0x100000,
  962. };
  963. struct nvme_feat_auto_pst {
  964. __le64 entries[32];
  965. };
  966. enum {
  967. NVME_HOST_MEM_ENABLE = (1 << 0),
  968. NVME_HOST_MEM_RETURN = (1 << 1),
  969. };
  970. struct nvme_feat_host_behavior {
  971. __u8 acre;
  972. __u8 etdas;
  973. __u8 lbafee;
  974. __u8 resv1[509];
  975. };
  976. enum {
  977. NVME_ENABLE_ACRE = 1,
  978. NVME_ENABLE_LBAFEE = 1,
  979. };
  980. /* Admin commands */
  981. enum nvme_admin_opcode {
  982. nvme_admin_delete_sq = 0x00,
  983. nvme_admin_create_sq = 0x01,
  984. nvme_admin_get_log_page = 0x02,
  985. nvme_admin_delete_cq = 0x04,
  986. nvme_admin_create_cq = 0x05,
  987. nvme_admin_identify = 0x06,
  988. nvme_admin_abort_cmd = 0x08,
  989. nvme_admin_set_features = 0x09,
  990. nvme_admin_get_features = 0x0a,
  991. nvme_admin_async_event = 0x0c,
  992. nvme_admin_ns_mgmt = 0x0d,
  993. nvme_admin_activate_fw = 0x10,
  994. nvme_admin_download_fw = 0x11,
  995. nvme_admin_dev_self_test = 0x14,
  996. nvme_admin_ns_attach = 0x15,
  997. nvme_admin_keep_alive = 0x18,
  998. nvme_admin_directive_send = 0x19,
  999. nvme_admin_directive_recv = 0x1a,
  1000. nvme_admin_virtual_mgmt = 0x1c,
  1001. nvme_admin_nvme_mi_send = 0x1d,
  1002. nvme_admin_nvme_mi_recv = 0x1e,
  1003. nvme_admin_dbbuf = 0x7C,
  1004. nvme_admin_format_nvm = 0x80,
  1005. nvme_admin_security_send = 0x81,
  1006. nvme_admin_security_recv = 0x82,
  1007. nvme_admin_sanitize_nvm = 0x84,
  1008. nvme_admin_get_lba_status = 0x86,
  1009. nvme_admin_vendor_start = 0xC0,
  1010. };
  1011. #define nvme_admin_opcode_name(opcode) { opcode, #opcode }
  1012. #define show_admin_opcode_name(val) \
  1013. __print_symbolic(val, \
  1014. nvme_admin_opcode_name(nvme_admin_delete_sq), \
  1015. nvme_admin_opcode_name(nvme_admin_create_sq), \
  1016. nvme_admin_opcode_name(nvme_admin_get_log_page), \
  1017. nvme_admin_opcode_name(nvme_admin_delete_cq), \
  1018. nvme_admin_opcode_name(nvme_admin_create_cq), \
  1019. nvme_admin_opcode_name(nvme_admin_identify), \
  1020. nvme_admin_opcode_name(nvme_admin_abort_cmd), \
  1021. nvme_admin_opcode_name(nvme_admin_set_features), \
  1022. nvme_admin_opcode_name(nvme_admin_get_features), \
  1023. nvme_admin_opcode_name(nvme_admin_async_event), \
  1024. nvme_admin_opcode_name(nvme_admin_ns_mgmt), \
  1025. nvme_admin_opcode_name(nvme_admin_activate_fw), \
  1026. nvme_admin_opcode_name(nvme_admin_download_fw), \
  1027. nvme_admin_opcode_name(nvme_admin_ns_attach), \
  1028. nvme_admin_opcode_name(nvme_admin_keep_alive), \
  1029. nvme_admin_opcode_name(nvme_admin_directive_send), \
  1030. nvme_admin_opcode_name(nvme_admin_directive_recv), \
  1031. nvme_admin_opcode_name(nvme_admin_dbbuf), \
  1032. nvme_admin_opcode_name(nvme_admin_format_nvm), \
  1033. nvme_admin_opcode_name(nvme_admin_security_send), \
  1034. nvme_admin_opcode_name(nvme_admin_security_recv), \
  1035. nvme_admin_opcode_name(nvme_admin_sanitize_nvm), \
  1036. nvme_admin_opcode_name(nvme_admin_get_lba_status))
  1037. enum {
  1038. NVME_QUEUE_PHYS_CONTIG = (1 << 0),
  1039. NVME_CQ_IRQ_ENABLED = (1 << 1),
  1040. NVME_SQ_PRIO_URGENT = (0 << 1),
  1041. NVME_SQ_PRIO_HIGH = (1 << 1),
  1042. NVME_SQ_PRIO_MEDIUM = (2 << 1),
  1043. NVME_SQ_PRIO_LOW = (3 << 1),
  1044. NVME_FEAT_ARBITRATION = 0x01,
  1045. NVME_FEAT_POWER_MGMT = 0x02,
  1046. NVME_FEAT_LBA_RANGE = 0x03,
  1047. NVME_FEAT_TEMP_THRESH = 0x04,
  1048. NVME_FEAT_ERR_RECOVERY = 0x05,
  1049. NVME_FEAT_VOLATILE_WC = 0x06,
  1050. NVME_FEAT_NUM_QUEUES = 0x07,
  1051. NVME_FEAT_IRQ_COALESCE = 0x08,
  1052. NVME_FEAT_IRQ_CONFIG = 0x09,
  1053. NVME_FEAT_WRITE_ATOMIC = 0x0a,
  1054. NVME_FEAT_ASYNC_EVENT = 0x0b,
  1055. NVME_FEAT_AUTO_PST = 0x0c,
  1056. NVME_FEAT_HOST_MEM_BUF = 0x0d,
  1057. NVME_FEAT_TIMESTAMP = 0x0e,
  1058. NVME_FEAT_KATO = 0x0f,
  1059. NVME_FEAT_HCTM = 0x10,
  1060. NVME_FEAT_NOPSC = 0x11,
  1061. NVME_FEAT_RRL = 0x12,
  1062. NVME_FEAT_PLM_CONFIG = 0x13,
  1063. NVME_FEAT_PLM_WINDOW = 0x14,
  1064. NVME_FEAT_HOST_BEHAVIOR = 0x16,
  1065. NVME_FEAT_SANITIZE = 0x17,
  1066. NVME_FEAT_SW_PROGRESS = 0x80,
  1067. NVME_FEAT_HOST_ID = 0x81,
  1068. NVME_FEAT_RESV_MASK = 0x82,
  1069. NVME_FEAT_RESV_PERSIST = 0x83,
  1070. NVME_FEAT_WRITE_PROTECT = 0x84,
  1071. NVME_FEAT_VENDOR_START = 0xC0,
  1072. NVME_FEAT_VENDOR_END = 0xFF,
  1073. NVME_LOG_ERROR = 0x01,
  1074. NVME_LOG_SMART = 0x02,
  1075. NVME_LOG_FW_SLOT = 0x03,
  1076. NVME_LOG_CHANGED_NS = 0x04,
  1077. NVME_LOG_CMD_EFFECTS = 0x05,
  1078. NVME_LOG_DEVICE_SELF_TEST = 0x06,
  1079. NVME_LOG_TELEMETRY_HOST = 0x07,
  1080. NVME_LOG_TELEMETRY_CTRL = 0x08,
  1081. NVME_LOG_ENDURANCE_GROUP = 0x09,
  1082. NVME_LOG_ANA = 0x0c,
  1083. NVME_LOG_DISC = 0x70,
  1084. NVME_LOG_RESERVATION = 0x80,
  1085. NVME_FWACT_REPL = (0 << 3),
  1086. NVME_FWACT_REPL_ACTV = (1 << 3),
  1087. NVME_FWACT_ACTV = (2 << 3),
  1088. };
  1089. /* NVMe Namespace Write Protect State */
  1090. enum {
  1091. NVME_NS_NO_WRITE_PROTECT = 0,
  1092. NVME_NS_WRITE_PROTECT,
  1093. NVME_NS_WRITE_PROTECT_POWER_CYCLE,
  1094. NVME_NS_WRITE_PROTECT_PERMANENT,
  1095. };
  1096. #define NVME_MAX_CHANGED_NAMESPACES 1024
  1097. struct nvme_identify {
  1098. __u8 opcode;
  1099. __u8 flags;
  1100. __u16 command_id;
  1101. __le32 nsid;
  1102. __u64 rsvd2[2];
  1103. union nvme_data_ptr dptr;
  1104. __u8 cns;
  1105. __u8 rsvd3;
  1106. __le16 ctrlid;
  1107. __u8 rsvd11[3];
  1108. __u8 csi;
  1109. __u32 rsvd12[4];
  1110. };
  1111. #define NVME_IDENTIFY_DATA_SIZE 4096
  1112. struct nvme_features {
  1113. __u8 opcode;
  1114. __u8 flags;
  1115. __u16 command_id;
  1116. __le32 nsid;
  1117. __u64 rsvd2[2];
  1118. union nvme_data_ptr dptr;
  1119. __le32 fid;
  1120. __le32 dword11;
  1121. __le32 dword12;
  1122. __le32 dword13;
  1123. __le32 dword14;
  1124. __le32 dword15;
  1125. };
  1126. struct nvme_host_mem_buf_desc {
  1127. __le64 addr;
  1128. __le32 size;
  1129. __u32 rsvd;
  1130. };
  1131. struct nvme_create_cq {
  1132. __u8 opcode;
  1133. __u8 flags;
  1134. __u16 command_id;
  1135. __u32 rsvd1[5];
  1136. __le64 prp1;
  1137. __u64 rsvd8;
  1138. __le16 cqid;
  1139. __le16 qsize;
  1140. __le16 cq_flags;
  1141. __le16 irq_vector;
  1142. __u32 rsvd12[4];
  1143. };
  1144. struct nvme_create_sq {
  1145. __u8 opcode;
  1146. __u8 flags;
  1147. __u16 command_id;
  1148. __u32 rsvd1[5];
  1149. __le64 prp1;
  1150. __u64 rsvd8;
  1151. __le16 sqid;
  1152. __le16 qsize;
  1153. __le16 sq_flags;
  1154. __le16 cqid;
  1155. __u32 rsvd12[4];
  1156. };
  1157. struct nvme_delete_queue {
  1158. __u8 opcode;
  1159. __u8 flags;
  1160. __u16 command_id;
  1161. __u32 rsvd1[9];
  1162. __le16 qid;
  1163. __u16 rsvd10;
  1164. __u32 rsvd11[5];
  1165. };
  1166. struct nvme_abort_cmd {
  1167. __u8 opcode;
  1168. __u8 flags;
  1169. __u16 command_id;
  1170. __u32 rsvd1[9];
  1171. __le16 sqid;
  1172. __u16 cid;
  1173. __u32 rsvd11[5];
  1174. };
  1175. struct nvme_download_firmware {
  1176. __u8 opcode;
  1177. __u8 flags;
  1178. __u16 command_id;
  1179. __u32 rsvd1[5];
  1180. union nvme_data_ptr dptr;
  1181. __le32 numd;
  1182. __le32 offset;
  1183. __u32 rsvd12[4];
  1184. };
  1185. struct nvme_format_cmd {
  1186. __u8 opcode;
  1187. __u8 flags;
  1188. __u16 command_id;
  1189. __le32 nsid;
  1190. __u64 rsvd2[4];
  1191. __le32 cdw10;
  1192. __u32 rsvd11[5];
  1193. };
  1194. struct nvme_get_log_page_command {
  1195. __u8 opcode;
  1196. __u8 flags;
  1197. __u16 command_id;
  1198. __le32 nsid;
  1199. __u64 rsvd2[2];
  1200. union nvme_data_ptr dptr;
  1201. __u8 lid;
  1202. __u8 lsp; /* upper 4 bits reserved */
  1203. __le16 numdl;
  1204. __le16 numdu;
  1205. __u16 rsvd11;
  1206. union {
  1207. struct {
  1208. __le32 lpol;
  1209. __le32 lpou;
  1210. };
  1211. __le64 lpo;
  1212. };
  1213. __u8 rsvd14[3];
  1214. __u8 csi;
  1215. __u32 rsvd15;
  1216. };
  1217. struct nvme_directive_cmd {
  1218. __u8 opcode;
  1219. __u8 flags;
  1220. __u16 command_id;
  1221. __le32 nsid;
  1222. __u64 rsvd2[2];
  1223. union nvme_data_ptr dptr;
  1224. __le32 numd;
  1225. __u8 doper;
  1226. __u8 dtype;
  1227. __le16 dspec;
  1228. __u8 endir;
  1229. __u8 tdtype;
  1230. __u16 rsvd15;
  1231. __u32 rsvd16[3];
  1232. };
  1233. /*
  1234. * Fabrics subcommands.
  1235. */
  1236. enum nvmf_fabrics_opcode {
  1237. nvme_fabrics_command = 0x7f,
  1238. };
  1239. enum nvmf_capsule_command {
  1240. nvme_fabrics_type_property_set = 0x00,
  1241. nvme_fabrics_type_connect = 0x01,
  1242. nvme_fabrics_type_property_get = 0x04,
  1243. nvme_fabrics_type_auth_send = 0x05,
  1244. nvme_fabrics_type_auth_receive = 0x06,
  1245. };
  1246. #define nvme_fabrics_type_name(type) { type, #type }
  1247. #define show_fabrics_type_name(type) \
  1248. __print_symbolic(type, \
  1249. nvme_fabrics_type_name(nvme_fabrics_type_property_set), \
  1250. nvme_fabrics_type_name(nvme_fabrics_type_connect), \
  1251. nvme_fabrics_type_name(nvme_fabrics_type_property_get), \
  1252. nvme_fabrics_type_name(nvme_fabrics_type_auth_send), \
  1253. nvme_fabrics_type_name(nvme_fabrics_type_auth_receive))
  1254. /*
  1255. * If not fabrics command, fctype will be ignored.
  1256. */
  1257. #define show_opcode_name(qid, opcode, fctype) \
  1258. ((opcode) == nvme_fabrics_command ? \
  1259. show_fabrics_type_name(fctype) : \
  1260. ((qid) ? \
  1261. show_nvm_opcode_name(opcode) : \
  1262. show_admin_opcode_name(opcode)))
  1263. struct nvmf_common_command {
  1264. __u8 opcode;
  1265. __u8 resv1;
  1266. __u16 command_id;
  1267. __u8 fctype;
  1268. __u8 resv2[35];
  1269. __u8 ts[24];
  1270. };
  1271. /*
  1272. * The legal cntlid range a NVMe Target will provide.
  1273. * Note that cntlid of value 0 is considered illegal in the fabrics world.
  1274. * Devices based on earlier specs did not have the subsystem concept;
  1275. * therefore, those devices had their cntlid value set to 0 as a result.
  1276. */
  1277. #define NVME_CNTLID_MIN 1
  1278. #define NVME_CNTLID_MAX 0xffef
  1279. #define NVME_CNTLID_DYNAMIC 0xffff
  1280. #define MAX_DISC_LOGS 255
  1281. /* Discovery log page entry flags (EFLAGS): */
  1282. enum {
  1283. NVME_DISC_EFLAGS_EPCSD = (1 << 1),
  1284. NVME_DISC_EFLAGS_DUPRETINFO = (1 << 0),
  1285. };
  1286. /* Discovery log page entry */
  1287. struct nvmf_disc_rsp_page_entry {
  1288. __u8 trtype;
  1289. __u8 adrfam;
  1290. __u8 subtype;
  1291. __u8 treq;
  1292. __le16 portid;
  1293. __le16 cntlid;
  1294. __le16 asqsz;
  1295. __le16 eflags;
  1296. __u8 resv10[20];
  1297. char trsvcid[NVMF_TRSVCID_SIZE];
  1298. __u8 resv64[192];
  1299. char subnqn[NVMF_NQN_FIELD_LEN];
  1300. char traddr[NVMF_TRADDR_SIZE];
  1301. union tsas {
  1302. char common[NVMF_TSAS_SIZE];
  1303. struct rdma {
  1304. __u8 qptype;
  1305. __u8 prtype;
  1306. __u8 cms;
  1307. __u8 resv3[5];
  1308. __u16 pkey;
  1309. __u8 resv10[246];
  1310. } rdma;
  1311. } tsas;
  1312. };
  1313. /* Discovery log page header */
  1314. struct nvmf_disc_rsp_page_hdr {
  1315. __le64 genctr;
  1316. __le64 numrec;
  1317. __le16 recfmt;
  1318. __u8 resv14[1006];
  1319. struct nvmf_disc_rsp_page_entry entries[];
  1320. };
  1321. enum {
  1322. NVME_CONNECT_DISABLE_SQFLOW = (1 << 2),
  1323. };
  1324. struct nvmf_connect_command {
  1325. __u8 opcode;
  1326. __u8 resv1;
  1327. __u16 command_id;
  1328. __u8 fctype;
  1329. __u8 resv2[19];
  1330. union nvme_data_ptr dptr;
  1331. __le16 recfmt;
  1332. __le16 qid;
  1333. __le16 sqsize;
  1334. __u8 cattr;
  1335. __u8 resv3;
  1336. __le32 kato;
  1337. __u8 resv4[12];
  1338. };
  1339. enum {
  1340. NVME_CONNECT_AUTHREQ_ASCR = (1U << 18),
  1341. NVME_CONNECT_AUTHREQ_ATR = (1U << 17),
  1342. };
  1343. struct nvmf_connect_data {
  1344. uuid_t hostid;
  1345. __le16 cntlid;
  1346. char resv4[238];
  1347. char subsysnqn[NVMF_NQN_FIELD_LEN];
  1348. char hostnqn[NVMF_NQN_FIELD_LEN];
  1349. char resv5[256];
  1350. };
  1351. struct nvmf_property_set_command {
  1352. __u8 opcode;
  1353. __u8 resv1;
  1354. __u16 command_id;
  1355. __u8 fctype;
  1356. __u8 resv2[35];
  1357. __u8 attrib;
  1358. __u8 resv3[3];
  1359. __le32 offset;
  1360. __le64 value;
  1361. __u8 resv4[8];
  1362. };
  1363. struct nvmf_property_get_command {
  1364. __u8 opcode;
  1365. __u8 resv1;
  1366. __u16 command_id;
  1367. __u8 fctype;
  1368. __u8 resv2[35];
  1369. __u8 attrib;
  1370. __u8 resv3[3];
  1371. __le32 offset;
  1372. __u8 resv4[16];
  1373. };
  1374. struct nvmf_auth_common_command {
  1375. __u8 opcode;
  1376. __u8 resv1;
  1377. __u16 command_id;
  1378. __u8 fctype;
  1379. __u8 resv2[19];
  1380. union nvme_data_ptr dptr;
  1381. __u8 resv3;
  1382. __u8 spsp0;
  1383. __u8 spsp1;
  1384. __u8 secp;
  1385. __le32 al_tl;
  1386. __u8 resv4[16];
  1387. };
  1388. struct nvmf_auth_send_command {
  1389. __u8 opcode;
  1390. __u8 resv1;
  1391. __u16 command_id;
  1392. __u8 fctype;
  1393. __u8 resv2[19];
  1394. union nvme_data_ptr dptr;
  1395. __u8 resv3;
  1396. __u8 spsp0;
  1397. __u8 spsp1;
  1398. __u8 secp;
  1399. __le32 tl;
  1400. __u8 resv4[16];
  1401. };
  1402. struct nvmf_auth_receive_command {
  1403. __u8 opcode;
  1404. __u8 resv1;
  1405. __u16 command_id;
  1406. __u8 fctype;
  1407. __u8 resv2[19];
  1408. union nvme_data_ptr dptr;
  1409. __u8 resv3;
  1410. __u8 spsp0;
  1411. __u8 spsp1;
  1412. __u8 secp;
  1413. __le32 al;
  1414. __u8 resv4[16];
  1415. };
  1416. /* Value for secp */
  1417. enum {
  1418. NVME_AUTH_DHCHAP_PROTOCOL_IDENTIFIER = 0xe9,
  1419. };
  1420. /* Defined value for auth_type */
  1421. enum {
  1422. NVME_AUTH_COMMON_MESSAGES = 0x00,
  1423. NVME_AUTH_DHCHAP_MESSAGES = 0x01,
  1424. };
  1425. /* Defined messages for auth_id */
  1426. enum {
  1427. NVME_AUTH_DHCHAP_MESSAGE_NEGOTIATE = 0x00,
  1428. NVME_AUTH_DHCHAP_MESSAGE_CHALLENGE = 0x01,
  1429. NVME_AUTH_DHCHAP_MESSAGE_REPLY = 0x02,
  1430. NVME_AUTH_DHCHAP_MESSAGE_SUCCESS1 = 0x03,
  1431. NVME_AUTH_DHCHAP_MESSAGE_SUCCESS2 = 0x04,
  1432. NVME_AUTH_DHCHAP_MESSAGE_FAILURE2 = 0xf0,
  1433. NVME_AUTH_DHCHAP_MESSAGE_FAILURE1 = 0xf1,
  1434. };
  1435. struct nvmf_auth_dhchap_protocol_descriptor {
  1436. __u8 authid;
  1437. __u8 rsvd;
  1438. __u8 halen;
  1439. __u8 dhlen;
  1440. __u8 idlist[60];
  1441. };
  1442. enum {
  1443. NVME_AUTH_DHCHAP_AUTH_ID = 0x01,
  1444. };
  1445. /* Defined hash functions for DH-HMAC-CHAP authentication */
  1446. enum {
  1447. NVME_AUTH_HASH_SHA256 = 0x01,
  1448. NVME_AUTH_HASH_SHA384 = 0x02,
  1449. NVME_AUTH_HASH_SHA512 = 0x03,
  1450. NVME_AUTH_HASH_INVALID = 0xff,
  1451. };
  1452. /* Defined Diffie-Hellman group identifiers for DH-HMAC-CHAP authentication */
  1453. enum {
  1454. NVME_AUTH_DHGROUP_NULL = 0x00,
  1455. NVME_AUTH_DHGROUP_2048 = 0x01,
  1456. NVME_AUTH_DHGROUP_3072 = 0x02,
  1457. NVME_AUTH_DHGROUP_4096 = 0x03,
  1458. NVME_AUTH_DHGROUP_6144 = 0x04,
  1459. NVME_AUTH_DHGROUP_8192 = 0x05,
  1460. NVME_AUTH_DHGROUP_INVALID = 0xff,
  1461. };
  1462. union nvmf_auth_protocol {
  1463. struct nvmf_auth_dhchap_protocol_descriptor dhchap;
  1464. };
  1465. struct nvmf_auth_dhchap_negotiate_data {
  1466. __u8 auth_type;
  1467. __u8 auth_id;
  1468. __le16 rsvd;
  1469. __le16 t_id;
  1470. __u8 sc_c;
  1471. __u8 napd;
  1472. union nvmf_auth_protocol auth_protocol[];
  1473. };
  1474. struct nvmf_auth_dhchap_challenge_data {
  1475. __u8 auth_type;
  1476. __u8 auth_id;
  1477. __u16 rsvd1;
  1478. __le16 t_id;
  1479. __u8 hl;
  1480. __u8 rsvd2;
  1481. __u8 hashid;
  1482. __u8 dhgid;
  1483. __le16 dhvlen;
  1484. __le32 seqnum;
  1485. /* 'hl' bytes of challenge value */
  1486. __u8 cval[];
  1487. /* followed by 'dhvlen' bytes of DH value */
  1488. };
  1489. struct nvmf_auth_dhchap_reply_data {
  1490. __u8 auth_type;
  1491. __u8 auth_id;
  1492. __le16 rsvd1;
  1493. __le16 t_id;
  1494. __u8 hl;
  1495. __u8 rsvd2;
  1496. __u8 cvalid;
  1497. __u8 rsvd3;
  1498. __le16 dhvlen;
  1499. __le32 seqnum;
  1500. /* 'hl' bytes of response data */
  1501. __u8 rval[];
  1502. /* followed by 'hl' bytes of Challenge value */
  1503. /* followed by 'dhvlen' bytes of DH value */
  1504. };
  1505. enum {
  1506. NVME_AUTH_DHCHAP_RESPONSE_VALID = (1 << 0),
  1507. };
  1508. struct nvmf_auth_dhchap_success1_data {
  1509. __u8 auth_type;
  1510. __u8 auth_id;
  1511. __le16 rsvd1;
  1512. __le16 t_id;
  1513. __u8 hl;
  1514. __u8 rsvd2;
  1515. __u8 rvalid;
  1516. __u8 rsvd3[7];
  1517. /* 'hl' bytes of response value if 'rvalid' is set */
  1518. __u8 rval[];
  1519. };
  1520. struct nvmf_auth_dhchap_success2_data {
  1521. __u8 auth_type;
  1522. __u8 auth_id;
  1523. __le16 rsvd1;
  1524. __le16 t_id;
  1525. __u8 rsvd2[10];
  1526. };
  1527. struct nvmf_auth_dhchap_failure_data {
  1528. __u8 auth_type;
  1529. __u8 auth_id;
  1530. __le16 rsvd1;
  1531. __le16 t_id;
  1532. __u8 rescode;
  1533. __u8 rescode_exp;
  1534. };
  1535. enum {
  1536. NVME_AUTH_DHCHAP_FAILURE_REASON_FAILED = 0x01,
  1537. };
  1538. enum {
  1539. NVME_AUTH_DHCHAP_FAILURE_FAILED = 0x01,
  1540. NVME_AUTH_DHCHAP_FAILURE_NOT_USABLE = 0x02,
  1541. NVME_AUTH_DHCHAP_FAILURE_CONCAT_MISMATCH = 0x03,
  1542. NVME_AUTH_DHCHAP_FAILURE_HASH_UNUSABLE = 0x04,
  1543. NVME_AUTH_DHCHAP_FAILURE_DHGROUP_UNUSABLE = 0x05,
  1544. NVME_AUTH_DHCHAP_FAILURE_INCORRECT_PAYLOAD = 0x06,
  1545. NVME_AUTH_DHCHAP_FAILURE_INCORRECT_MESSAGE = 0x07,
  1546. };
  1547. struct nvme_dbbuf {
  1548. __u8 opcode;
  1549. __u8 flags;
  1550. __u16 command_id;
  1551. __u32 rsvd1[5];
  1552. __le64 prp1;
  1553. __le64 prp2;
  1554. __u32 rsvd12[6];
  1555. };
  1556. struct streams_directive_params {
  1557. __le16 msl;
  1558. __le16 nssa;
  1559. __le16 nsso;
  1560. __u8 rsvd[10];
  1561. __le32 sws;
  1562. __le16 sgs;
  1563. __le16 nsa;
  1564. __le16 nso;
  1565. __u8 rsvd2[6];
  1566. };
  1567. struct nvme_command {
  1568. union {
  1569. struct nvme_common_command common;
  1570. struct nvme_rw_command rw;
  1571. struct nvme_identify identify;
  1572. struct nvme_features features;
  1573. struct nvme_create_cq create_cq;
  1574. struct nvme_create_sq create_sq;
  1575. struct nvme_delete_queue delete_queue;
  1576. struct nvme_download_firmware dlfw;
  1577. struct nvme_format_cmd format;
  1578. struct nvme_dsm_cmd dsm;
  1579. struct nvme_write_zeroes_cmd write_zeroes;
  1580. struct nvme_zone_mgmt_send_cmd zms;
  1581. struct nvme_zone_mgmt_recv_cmd zmr;
  1582. struct nvme_abort_cmd abort;
  1583. struct nvme_get_log_page_command get_log_page;
  1584. struct nvmf_common_command fabrics;
  1585. struct nvmf_connect_command connect;
  1586. struct nvmf_property_set_command prop_set;
  1587. struct nvmf_property_get_command prop_get;
  1588. struct nvmf_auth_common_command auth_common;
  1589. struct nvmf_auth_send_command auth_send;
  1590. struct nvmf_auth_receive_command auth_receive;
  1591. struct nvme_dbbuf dbbuf;
  1592. struct nvme_directive_cmd directive;
  1593. };
  1594. };
  1595. static inline bool nvme_is_fabrics(struct nvme_command *cmd)
  1596. {
  1597. return cmd->common.opcode == nvme_fabrics_command;
  1598. }
  1599. struct nvme_error_slot {
  1600. __le64 error_count;
  1601. __le16 sqid;
  1602. __le16 cmdid;
  1603. __le16 status_field;
  1604. __le16 param_error_location;
  1605. __le64 lba;
  1606. __le32 nsid;
  1607. __u8 vs;
  1608. __u8 resv[3];
  1609. __le64 cs;
  1610. __u8 resv2[24];
  1611. };
  1612. static inline bool nvme_is_write(struct nvme_command *cmd)
  1613. {
  1614. /*
  1615. * What a mess...
  1616. *
  1617. * Why can't we simply have a Fabrics In and Fabrics out command?
  1618. */
  1619. if (unlikely(nvme_is_fabrics(cmd)))
  1620. return cmd->fabrics.fctype & 1;
  1621. return cmd->common.opcode & 1;
  1622. }
  1623. enum {
  1624. /*
  1625. * Generic Command Status:
  1626. */
  1627. NVME_SC_SUCCESS = 0x0,
  1628. NVME_SC_INVALID_OPCODE = 0x1,
  1629. NVME_SC_INVALID_FIELD = 0x2,
  1630. NVME_SC_CMDID_CONFLICT = 0x3,
  1631. NVME_SC_DATA_XFER_ERROR = 0x4,
  1632. NVME_SC_POWER_LOSS = 0x5,
  1633. NVME_SC_INTERNAL = 0x6,
  1634. NVME_SC_ABORT_REQ = 0x7,
  1635. NVME_SC_ABORT_QUEUE = 0x8,
  1636. NVME_SC_FUSED_FAIL = 0x9,
  1637. NVME_SC_FUSED_MISSING = 0xa,
  1638. NVME_SC_INVALID_NS = 0xb,
  1639. NVME_SC_CMD_SEQ_ERROR = 0xc,
  1640. NVME_SC_SGL_INVALID_LAST = 0xd,
  1641. NVME_SC_SGL_INVALID_COUNT = 0xe,
  1642. NVME_SC_SGL_INVALID_DATA = 0xf,
  1643. NVME_SC_SGL_INVALID_METADATA = 0x10,
  1644. NVME_SC_SGL_INVALID_TYPE = 0x11,
  1645. NVME_SC_CMB_INVALID_USE = 0x12,
  1646. NVME_SC_PRP_INVALID_OFFSET = 0x13,
  1647. NVME_SC_ATOMIC_WU_EXCEEDED = 0x14,
  1648. NVME_SC_OP_DENIED = 0x15,
  1649. NVME_SC_SGL_INVALID_OFFSET = 0x16,
  1650. NVME_SC_RESERVED = 0x17,
  1651. NVME_SC_HOST_ID_INCONSIST = 0x18,
  1652. NVME_SC_KA_TIMEOUT_EXPIRED = 0x19,
  1653. NVME_SC_KA_TIMEOUT_INVALID = 0x1A,
  1654. NVME_SC_ABORTED_PREEMPT_ABORT = 0x1B,
  1655. NVME_SC_SANITIZE_FAILED = 0x1C,
  1656. NVME_SC_SANITIZE_IN_PROGRESS = 0x1D,
  1657. NVME_SC_SGL_INVALID_GRANULARITY = 0x1E,
  1658. NVME_SC_CMD_NOT_SUP_CMB_QUEUE = 0x1F,
  1659. NVME_SC_NS_WRITE_PROTECTED = 0x20,
  1660. NVME_SC_CMD_INTERRUPTED = 0x21,
  1661. NVME_SC_TRANSIENT_TR_ERR = 0x22,
  1662. NVME_SC_ADMIN_COMMAND_MEDIA_NOT_READY = 0x24,
  1663. NVME_SC_INVALID_IO_CMD_SET = 0x2C,
  1664. NVME_SC_LBA_RANGE = 0x80,
  1665. NVME_SC_CAP_EXCEEDED = 0x81,
  1666. NVME_SC_NS_NOT_READY = 0x82,
  1667. NVME_SC_RESERVATION_CONFLICT = 0x83,
  1668. NVME_SC_FORMAT_IN_PROGRESS = 0x84,
  1669. /*
  1670. * Command Specific Status:
  1671. */
  1672. NVME_SC_CQ_INVALID = 0x100,
  1673. NVME_SC_QID_INVALID = 0x101,
  1674. NVME_SC_QUEUE_SIZE = 0x102,
  1675. NVME_SC_ABORT_LIMIT = 0x103,
  1676. NVME_SC_ABORT_MISSING = 0x104,
  1677. NVME_SC_ASYNC_LIMIT = 0x105,
  1678. NVME_SC_FIRMWARE_SLOT = 0x106,
  1679. NVME_SC_FIRMWARE_IMAGE = 0x107,
  1680. NVME_SC_INVALID_VECTOR = 0x108,
  1681. NVME_SC_INVALID_LOG_PAGE = 0x109,
  1682. NVME_SC_INVALID_FORMAT = 0x10a,
  1683. NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
  1684. NVME_SC_INVALID_QUEUE = 0x10c,
  1685. NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
  1686. NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
  1687. NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
  1688. NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
  1689. NVME_SC_FW_NEEDS_RESET = 0x111,
  1690. NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
  1691. NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113,
  1692. NVME_SC_OVERLAPPING_RANGE = 0x114,
  1693. NVME_SC_NS_INSUFFICIENT_CAP = 0x115,
  1694. NVME_SC_NS_ID_UNAVAILABLE = 0x116,
  1695. NVME_SC_NS_ALREADY_ATTACHED = 0x118,
  1696. NVME_SC_NS_IS_PRIVATE = 0x119,
  1697. NVME_SC_NS_NOT_ATTACHED = 0x11a,
  1698. NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
  1699. NVME_SC_CTRL_LIST_INVALID = 0x11c,
  1700. NVME_SC_SELT_TEST_IN_PROGRESS = 0x11d,
  1701. NVME_SC_BP_WRITE_PROHIBITED = 0x11e,
  1702. NVME_SC_CTRL_ID_INVALID = 0x11f,
  1703. NVME_SC_SEC_CTRL_STATE_INVALID = 0x120,
  1704. NVME_SC_CTRL_RES_NUM_INVALID = 0x121,
  1705. NVME_SC_RES_ID_INVALID = 0x122,
  1706. NVME_SC_PMR_SAN_PROHIBITED = 0x123,
  1707. NVME_SC_ANA_GROUP_ID_INVALID = 0x124,
  1708. NVME_SC_ANA_ATTACH_FAILED = 0x125,
  1709. /*
  1710. * I/O Command Set Specific - NVM commands:
  1711. */
  1712. NVME_SC_BAD_ATTRIBUTES = 0x180,
  1713. NVME_SC_INVALID_PI = 0x181,
  1714. NVME_SC_READ_ONLY = 0x182,
  1715. NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
  1716. /*
  1717. * I/O Command Set Specific - Fabrics commands:
  1718. */
  1719. NVME_SC_CONNECT_FORMAT = 0x180,
  1720. NVME_SC_CONNECT_CTRL_BUSY = 0x181,
  1721. NVME_SC_CONNECT_INVALID_PARAM = 0x182,
  1722. NVME_SC_CONNECT_RESTART_DISC = 0x183,
  1723. NVME_SC_CONNECT_INVALID_HOST = 0x184,
  1724. NVME_SC_DISCOVERY_RESTART = 0x190,
  1725. NVME_SC_AUTH_REQUIRED = 0x191,
  1726. /*
  1727. * I/O Command Set Specific - Zoned commands:
  1728. */
  1729. NVME_SC_ZONE_BOUNDARY_ERROR = 0x1b8,
  1730. NVME_SC_ZONE_FULL = 0x1b9,
  1731. NVME_SC_ZONE_READ_ONLY = 0x1ba,
  1732. NVME_SC_ZONE_OFFLINE = 0x1bb,
  1733. NVME_SC_ZONE_INVALID_WRITE = 0x1bc,
  1734. NVME_SC_ZONE_TOO_MANY_ACTIVE = 0x1bd,
  1735. NVME_SC_ZONE_TOO_MANY_OPEN = 0x1be,
  1736. NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf,
  1737. /*
  1738. * Media and Data Integrity Errors:
  1739. */
  1740. NVME_SC_WRITE_FAULT = 0x280,
  1741. NVME_SC_READ_ERROR = 0x281,
  1742. NVME_SC_GUARD_CHECK = 0x282,
  1743. NVME_SC_APPTAG_CHECK = 0x283,
  1744. NVME_SC_REFTAG_CHECK = 0x284,
  1745. NVME_SC_COMPARE_FAILED = 0x285,
  1746. NVME_SC_ACCESS_DENIED = 0x286,
  1747. NVME_SC_UNWRITTEN_BLOCK = 0x287,
  1748. /*
  1749. * Path-related Errors:
  1750. */
  1751. NVME_SC_INTERNAL_PATH_ERROR = 0x300,
  1752. NVME_SC_ANA_PERSISTENT_LOSS = 0x301,
  1753. NVME_SC_ANA_INACCESSIBLE = 0x302,
  1754. NVME_SC_ANA_TRANSITION = 0x303,
  1755. NVME_SC_CTRL_PATH_ERROR = 0x360,
  1756. NVME_SC_HOST_PATH_ERROR = 0x370,
  1757. NVME_SC_HOST_ABORTED_CMD = 0x371,
  1758. NVME_SC_CRD = 0x1800,
  1759. NVME_SC_MORE = 0x2000,
  1760. NVME_SC_DNR = 0x4000,
  1761. };
  1762. struct nvme_completion {
  1763. /*
  1764. * Used by Admin and Fabrics commands to return data:
  1765. */
  1766. union nvme_result {
  1767. __le16 u16;
  1768. __le32 u32;
  1769. __le64 u64;
  1770. } result;
  1771. __le16 sq_head; /* how much of this queue may be reclaimed */
  1772. __le16 sq_id; /* submission queue that generated this entry */
  1773. __u16 command_id; /* of the command which completed */
  1774. __le16 status; /* did the command fail, and if so, why? */
  1775. };
  1776. #define NVME_VS(major, minor, tertiary) \
  1777. (((major) << 16) | ((minor) << 8) | (tertiary))
  1778. #define NVME_MAJOR(ver) ((ver) >> 16)
  1779. #define NVME_MINOR(ver) (((ver) >> 8) & 0xff)
  1780. #define NVME_TERTIARY(ver) ((ver) & 0xff)
  1781. #endif /* _LINUX_NVME_H */