pmic.h 27 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * pmic.h -- Power Management Driver for Wolfson WM8350 PMIC
  4. *
  5. * Copyright 2007 Wolfson Microelectronics PLC
  6. */
  7. #ifndef __LINUX_MFD_WM8350_PMIC_H
  8. #define __LINUX_MFD_WM8350_PMIC_H
  9. #include <linux/platform_device.h>
  10. #include <linux/leds.h>
  11. #include <linux/regulator/machine.h>
  12. /*
  13. * Register values.
  14. */
  15. #define WM8350_CURRENT_SINK_DRIVER_A 0xAC
  16. #define WM8350_CSA_FLASH_CONTROL 0xAD
  17. #define WM8350_CURRENT_SINK_DRIVER_B 0xAE
  18. #define WM8350_CSB_FLASH_CONTROL 0xAF
  19. #define WM8350_DCDC_LDO_REQUESTED 0xB0
  20. #define WM8350_DCDC_ACTIVE_OPTIONS 0xB1
  21. #define WM8350_DCDC_SLEEP_OPTIONS 0xB2
  22. #define WM8350_POWER_CHECK_COMPARATOR 0xB3
  23. #define WM8350_DCDC1_CONTROL 0xB4
  24. #define WM8350_DCDC1_TIMEOUTS 0xB5
  25. #define WM8350_DCDC1_LOW_POWER 0xB6
  26. #define WM8350_DCDC2_CONTROL 0xB7
  27. #define WM8350_DCDC2_TIMEOUTS 0xB8
  28. #define WM8350_DCDC3_CONTROL 0xBA
  29. #define WM8350_DCDC3_TIMEOUTS 0xBB
  30. #define WM8350_DCDC3_LOW_POWER 0xBC
  31. #define WM8350_DCDC4_CONTROL 0xBD
  32. #define WM8350_DCDC4_TIMEOUTS 0xBE
  33. #define WM8350_DCDC4_LOW_POWER 0xBF
  34. #define WM8350_DCDC5_CONTROL 0xC0
  35. #define WM8350_DCDC5_TIMEOUTS 0xC1
  36. #define WM8350_DCDC6_CONTROL 0xC3
  37. #define WM8350_DCDC6_TIMEOUTS 0xC4
  38. #define WM8350_DCDC6_LOW_POWER 0xC5
  39. #define WM8350_LIMIT_SWITCH_CONTROL 0xC7
  40. #define WM8350_LDO1_CONTROL 0xC8
  41. #define WM8350_LDO1_TIMEOUTS 0xC9
  42. #define WM8350_LDO1_LOW_POWER 0xCA
  43. #define WM8350_LDO2_CONTROL 0xCB
  44. #define WM8350_LDO2_TIMEOUTS 0xCC
  45. #define WM8350_LDO2_LOW_POWER 0xCD
  46. #define WM8350_LDO3_CONTROL 0xCE
  47. #define WM8350_LDO3_TIMEOUTS 0xCF
  48. #define WM8350_LDO3_LOW_POWER 0xD0
  49. #define WM8350_LDO4_CONTROL 0xD1
  50. #define WM8350_LDO4_TIMEOUTS 0xD2
  51. #define WM8350_LDO4_LOW_POWER 0xD3
  52. #define WM8350_VCC_FAULT_MASKS 0xD7
  53. #define WM8350_MAIN_BANDGAP_CONTROL 0xD8
  54. #define WM8350_OSC_CONTROL 0xD9
  55. #define WM8350_RTC_TICK_CONTROL 0xDA
  56. #define WM8350_SECURITY 0xDB
  57. #define WM8350_RAM_BIST_1 0xDC
  58. #define WM8350_DCDC_LDO_STATUS 0xE1
  59. #define WM8350_GPIO_PIN_STATUS 0xE6
  60. #define WM8350_DCDC1_FORCE_PWM 0xF8
  61. #define WM8350_DCDC3_FORCE_PWM 0xFA
  62. #define WM8350_DCDC4_FORCE_PWM 0xFB
  63. #define WM8350_DCDC6_FORCE_PWM 0xFD
  64. /*
  65. * R172 (0xAC) - Current Sink Driver A
  66. */
  67. #define WM8350_CS1_HIB_MODE 0x1000
  68. #define WM8350_CS1_HIB_MODE_MASK 0x1000
  69. #define WM8350_CS1_HIB_MODE_SHIFT 12
  70. #define WM8350_CS1_ISEL_MASK 0x003F
  71. #define WM8350_CS1_ISEL_SHIFT 0
  72. /* Bit values for R172 (0xAC) */
  73. #define WM8350_CS1_HIB_MODE_DISABLE 0
  74. #define WM8350_CS1_HIB_MODE_LEAVE 1
  75. #define WM8350_CS1_ISEL_220M 0x3F
  76. /*
  77. * R173 (0xAD) - CSA Flash control
  78. */
  79. #define WM8350_CS1_FLASH_MODE 0x8000
  80. #define WM8350_CS1_TRIGSRC 0x4000
  81. #define WM8350_CS1_DRIVE 0x2000
  82. #define WM8350_CS1_FLASH_DUR_MASK 0x0300
  83. #define WM8350_CS1_OFF_RAMP_MASK 0x0030
  84. #define WM8350_CS1_ON_RAMP_MASK 0x0003
  85. /*
  86. * R174 (0xAE) - Current Sink Driver B
  87. */
  88. #define WM8350_CS2_HIB_MODE 0x1000
  89. #define WM8350_CS2_ISEL_MASK 0x003F
  90. /*
  91. * R175 (0xAF) - CSB Flash control
  92. */
  93. #define WM8350_CS2_FLASH_MODE 0x8000
  94. #define WM8350_CS2_TRIGSRC 0x4000
  95. #define WM8350_CS2_DRIVE 0x2000
  96. #define WM8350_CS2_FLASH_DUR_MASK 0x0300
  97. #define WM8350_CS2_OFF_RAMP_MASK 0x0030
  98. #define WM8350_CS2_ON_RAMP_MASK 0x0003
  99. /*
  100. * R176 (0xB0) - DCDC/LDO requested
  101. */
  102. #define WM8350_LS_ENA 0x8000
  103. #define WM8350_LDO4_ENA 0x0800
  104. #define WM8350_LDO3_ENA 0x0400
  105. #define WM8350_LDO2_ENA 0x0200
  106. #define WM8350_LDO1_ENA 0x0100
  107. #define WM8350_DC6_ENA 0x0020
  108. #define WM8350_DC5_ENA 0x0010
  109. #define WM8350_DC4_ENA 0x0008
  110. #define WM8350_DC3_ENA 0x0004
  111. #define WM8350_DC2_ENA 0x0002
  112. #define WM8350_DC1_ENA 0x0001
  113. /*
  114. * R177 (0xB1) - DCDC Active options
  115. */
  116. #define WM8350_PUTO_MASK 0x3000
  117. #define WM8350_PWRUP_DELAY_MASK 0x0300
  118. #define WM8350_DC6_ACTIVE 0x0020
  119. #define WM8350_DC4_ACTIVE 0x0008
  120. #define WM8350_DC3_ACTIVE 0x0004
  121. #define WM8350_DC1_ACTIVE 0x0001
  122. /*
  123. * R178 (0xB2) - DCDC Sleep options
  124. */
  125. #define WM8350_DC6_SLEEP 0x0020
  126. #define WM8350_DC4_SLEEP 0x0008
  127. #define WM8350_DC3_SLEEP 0x0004
  128. #define WM8350_DC1_SLEEP 0x0001
  129. /*
  130. * R179 (0xB3) - Power-check comparator
  131. */
  132. #define WM8350_PCCMP_ERRACT 0x4000
  133. #define WM8350_PCCMP_RAIL 0x0100
  134. #define WM8350_PCCMP_OFF_THR_MASK 0x0070
  135. #define WM8350_PCCMP_ON_THR_MASK 0x0007
  136. /*
  137. * R180 (0xB4) - DCDC1 Control
  138. */
  139. #define WM8350_DC1_OPFLT 0x0400
  140. #define WM8350_DC1_VSEL_MASK 0x007F
  141. #define WM8350_DC1_VSEL_SHIFT 0
  142. /*
  143. * R181 (0xB5) - DCDC1 Timeouts
  144. */
  145. #define WM8350_DC1_ERRACT_MASK 0xC000
  146. #define WM8350_DC1_ERRACT_SHIFT 14
  147. #define WM8350_DC1_ENSLOT_MASK 0x3C00
  148. #define WM8350_DC1_ENSLOT_SHIFT 10
  149. #define WM8350_DC1_SDSLOT_MASK 0x03C0
  150. #define WM8350_DC1_UVTO_MASK 0x0030
  151. #define WM8350_DC1_SDSLOT_SHIFT 6
  152. /* Bit values for R181 (0xB5) */
  153. #define WM8350_DC1_ERRACT_NONE 0
  154. #define WM8350_DC1_ERRACT_SHUTDOWN_CONV 1
  155. #define WM8350_DC1_ERRACT_SHUTDOWN_SYS 2
  156. /*
  157. * R182 (0xB6) - DCDC1 Low Power
  158. */
  159. #define WM8350_DC1_HIB_MODE_MASK 0x7000
  160. #define WM8350_DC1_HIB_TRIG_MASK 0x0300
  161. #define WM8350_DC1_VIMG_MASK 0x007F
  162. /*
  163. * R183 (0xB7) - DCDC2 Control
  164. */
  165. #define WM8350_DC2_MODE 0x4000
  166. #define WM8350_DC2_MODE_MASK 0x4000
  167. #define WM8350_DC2_MODE_SHIFT 14
  168. #define WM8350_DC2_HIB_MODE 0x1000
  169. #define WM8350_DC2_HIB_MODE_MASK 0x1000
  170. #define WM8350_DC2_HIB_MODE_SHIFT 12
  171. #define WM8350_DC2_HIB_TRIG_MASK 0x0300
  172. #define WM8350_DC2_HIB_TRIG_SHIFT 8
  173. #define WM8350_DC2_ILIM 0x0040
  174. #define WM8350_DC2_ILIM_MASK 0x0040
  175. #define WM8350_DC2_ILIM_SHIFT 6
  176. #define WM8350_DC2_RMP_MASK 0x0018
  177. #define WM8350_DC2_RMP_SHIFT 3
  178. #define WM8350_DC2_FBSRC_MASK 0x0003
  179. #define WM8350_DC2_FBSRC_SHIFT 0
  180. /* Bit values for R183 (0xB7) */
  181. #define WM8350_DC2_MODE_BOOST 0
  182. #define WM8350_DC2_MODE_SWITCH 1
  183. #define WM8350_DC2_HIB_MODE_ACTIVE 1
  184. #define WM8350_DC2_HIB_MODE_DISABLE 0
  185. #define WM8350_DC2_HIB_TRIG_NONE 0
  186. #define WM8350_DC2_HIB_TRIG_LPWR1 1
  187. #define WM8350_DC2_HIB_TRIG_LPWR2 2
  188. #define WM8350_DC2_HIB_TRIG_LPWR3 3
  189. #define WM8350_DC2_ILIM_HIGH 0
  190. #define WM8350_DC2_ILIM_LOW 1
  191. #define WM8350_DC2_RMP_30V 0
  192. #define WM8350_DC2_RMP_20V 1
  193. #define WM8350_DC2_RMP_10V 2
  194. #define WM8350_DC2_RMP_5V 3
  195. #define WM8350_DC2_FBSRC_FB2 0
  196. #define WM8350_DC2_FBSRC_ISINKA 1
  197. #define WM8350_DC2_FBSRC_ISINKB 2
  198. #define WM8350_DC2_FBSRC_USB 3
  199. /*
  200. * R184 (0xB8) - DCDC2 Timeouts
  201. */
  202. #define WM8350_DC2_ERRACT_MASK 0xC000
  203. #define WM8350_DC2_ERRACT_SHIFT 14
  204. #define WM8350_DC2_ENSLOT_MASK 0x3C00
  205. #define WM8350_DC2_ENSLOT_SHIFT 10
  206. #define WM8350_DC2_SDSLOT_MASK 0x03C0
  207. #define WM8350_DC2_UVTO_MASK 0x0030
  208. /* Bit values for R184 (0xB8) */
  209. #define WM8350_DC2_ERRACT_NONE 0
  210. #define WM8350_DC2_ERRACT_SHUTDOWN_CONV 1
  211. #define WM8350_DC2_ERRACT_SHUTDOWN_SYS 2
  212. /*
  213. * R186 (0xBA) - DCDC3 Control
  214. */
  215. #define WM8350_DC3_OPFLT 0x0400
  216. #define WM8350_DC3_VSEL_MASK 0x007F
  217. #define WM8350_DC3_VSEL_SHIFT 0
  218. /*
  219. * R187 (0xBB) - DCDC3 Timeouts
  220. */
  221. #define WM8350_DC3_ERRACT_MASK 0xC000
  222. #define WM8350_DC3_ERRACT_SHIFT 14
  223. #define WM8350_DC3_ENSLOT_MASK 0x3C00
  224. #define WM8350_DC3_ENSLOT_SHIFT 10
  225. #define WM8350_DC3_SDSLOT_MASK 0x03C0
  226. #define WM8350_DC3_UVTO_MASK 0x0030
  227. #define WM8350_DC3_SDSLOT_SHIFT 6
  228. /* Bit values for R187 (0xBB) */
  229. #define WM8350_DC3_ERRACT_NONE 0
  230. #define WM8350_DC3_ERRACT_SHUTDOWN_CONV 1
  231. #define WM8350_DC3_ERRACT_SHUTDOWN_SYS 2
  232. /*
  233. * R188 (0xBC) - DCDC3 Low Power
  234. */
  235. #define WM8350_DC3_HIB_MODE_MASK 0x7000
  236. #define WM8350_DC3_HIB_TRIG_MASK 0x0300
  237. #define WM8350_DC3_VIMG_MASK 0x007F
  238. /*
  239. * R189 (0xBD) - DCDC4 Control
  240. */
  241. #define WM8350_DC4_OPFLT 0x0400
  242. #define WM8350_DC4_VSEL_MASK 0x007F
  243. #define WM8350_DC4_VSEL_SHIFT 0
  244. /*
  245. * R190 (0xBE) - DCDC4 Timeouts
  246. */
  247. #define WM8350_DC4_ERRACT_MASK 0xC000
  248. #define WM8350_DC4_ERRACT_SHIFT 14
  249. #define WM8350_DC4_ENSLOT_MASK 0x3C00
  250. #define WM8350_DC4_ENSLOT_SHIFT 10
  251. #define WM8350_DC4_SDSLOT_MASK 0x03C0
  252. #define WM8350_DC4_UVTO_MASK 0x0030
  253. #define WM8350_DC4_SDSLOT_SHIFT 6
  254. /* Bit values for R190 (0xBE) */
  255. #define WM8350_DC4_ERRACT_NONE 0
  256. #define WM8350_DC4_ERRACT_SHUTDOWN_CONV 1
  257. #define WM8350_DC4_ERRACT_SHUTDOWN_SYS 2
  258. /*
  259. * R191 (0xBF) - DCDC4 Low Power
  260. */
  261. #define WM8350_DC4_HIB_MODE_MASK 0x7000
  262. #define WM8350_DC4_HIB_TRIG_MASK 0x0300
  263. #define WM8350_DC4_VIMG_MASK 0x007F
  264. /*
  265. * R192 (0xC0) - DCDC5 Control
  266. */
  267. #define WM8350_DC5_MODE 0x4000
  268. #define WM8350_DC5_MODE_MASK 0x4000
  269. #define WM8350_DC5_MODE_SHIFT 14
  270. #define WM8350_DC5_HIB_MODE 0x1000
  271. #define WM8350_DC5_HIB_MODE_MASK 0x1000
  272. #define WM8350_DC5_HIB_MODE_SHIFT 12
  273. #define WM8350_DC5_HIB_TRIG_MASK 0x0300
  274. #define WM8350_DC5_HIB_TRIG_SHIFT 8
  275. #define WM8350_DC5_ILIM 0x0040
  276. #define WM8350_DC5_ILIM_MASK 0x0040
  277. #define WM8350_DC5_ILIM_SHIFT 6
  278. #define WM8350_DC5_RMP_MASK 0x0018
  279. #define WM8350_DC5_RMP_SHIFT 3
  280. #define WM8350_DC5_FBSRC_MASK 0x0003
  281. #define WM8350_DC5_FBSRC_SHIFT 0
  282. /* Bit values for R192 (0xC0) */
  283. #define WM8350_DC5_MODE_BOOST 0
  284. #define WM8350_DC5_MODE_SWITCH 1
  285. #define WM8350_DC5_HIB_MODE_ACTIVE 1
  286. #define WM8350_DC5_HIB_MODE_DISABLE 0
  287. #define WM8350_DC5_HIB_TRIG_NONE 0
  288. #define WM8350_DC5_HIB_TRIG_LPWR1 1
  289. #define WM8350_DC5_HIB_TRIG_LPWR2 2
  290. #define WM8350_DC5_HIB_TRIG_LPWR3 3
  291. #define WM8350_DC5_ILIM_HIGH 0
  292. #define WM8350_DC5_ILIM_LOW 1
  293. #define WM8350_DC5_RMP_30V 0
  294. #define WM8350_DC5_RMP_20V 1
  295. #define WM8350_DC5_RMP_10V 2
  296. #define WM8350_DC5_RMP_5V 3
  297. #define WM8350_DC5_FBSRC_FB2 0
  298. #define WM8350_DC5_FBSRC_ISINKA 1
  299. #define WM8350_DC5_FBSRC_ISINKB 2
  300. #define WM8350_DC5_FBSRC_USB 3
  301. /*
  302. * R193 (0xC1) - DCDC5 Timeouts
  303. */
  304. #define WM8350_DC5_ERRACT_MASK 0xC000
  305. #define WM8350_DC5_ERRACT_SHIFT 14
  306. #define WM8350_DC5_ENSLOT_MASK 0x3C00
  307. #define WM8350_DC5_ENSLOT_SHIFT 10
  308. #define WM8350_DC5_SDSLOT_MASK 0x03C0
  309. #define WM8350_DC5_UVTO_MASK 0x0030
  310. #define WM8350_DC5_SDSLOT_SHIFT 6
  311. /* Bit values for R193 (0xC1) */
  312. #define WM8350_DC5_ERRACT_NONE 0
  313. #define WM8350_DC5_ERRACT_SHUTDOWN_CONV 1
  314. #define WM8350_DC5_ERRACT_SHUTDOWN_SYS 2
  315. /*
  316. * R195 (0xC3) - DCDC6 Control
  317. */
  318. #define WM8350_DC6_OPFLT 0x0400
  319. #define WM8350_DC6_VSEL_MASK 0x007F
  320. #define WM8350_DC6_VSEL_SHIFT 0
  321. /*
  322. * R196 (0xC4) - DCDC6 Timeouts
  323. */
  324. #define WM8350_DC6_ERRACT_MASK 0xC000
  325. #define WM8350_DC6_ERRACT_SHIFT 14
  326. #define WM8350_DC6_ENSLOT_MASK 0x3C00
  327. #define WM8350_DC6_ENSLOT_SHIFT 10
  328. #define WM8350_DC6_SDSLOT_MASK 0x03C0
  329. #define WM8350_DC6_UVTO_MASK 0x0030
  330. #define WM8350_DC6_SDSLOT_SHIFT 6
  331. /* Bit values for R196 (0xC4) */
  332. #define WM8350_DC6_ERRACT_NONE 0
  333. #define WM8350_DC6_ERRACT_SHUTDOWN_CONV 1
  334. #define WM8350_DC6_ERRACT_SHUTDOWN_SYS 2
  335. /*
  336. * R197 (0xC5) - DCDC6 Low Power
  337. */
  338. #define WM8350_DC6_HIB_MODE_MASK 0x7000
  339. #define WM8350_DC6_HIB_TRIG_MASK 0x0300
  340. #define WM8350_DC6_VIMG_MASK 0x007F
  341. /*
  342. * R199 (0xC7) - Limit Switch Control
  343. */
  344. #define WM8350_LS_ERRACT_MASK 0xC000
  345. #define WM8350_LS_ERRACT_SHIFT 14
  346. #define WM8350_LS_ENSLOT_MASK 0x3C00
  347. #define WM8350_LS_ENSLOT_SHIFT 10
  348. #define WM8350_LS_SDSLOT_MASK 0x03C0
  349. #define WM8350_LS_SDSLOT_SHIFT 6
  350. #define WM8350_LS_HIB_MODE 0x0010
  351. #define WM8350_LS_HIB_MODE_MASK 0x0010
  352. #define WM8350_LS_HIB_MODE_SHIFT 4
  353. #define WM8350_LS_HIB_PROT 0x0002
  354. #define WM8350_LS_HIB_PROT_MASK 0x0002
  355. #define WM8350_LS_HIB_PROT_SHIFT 1
  356. #define WM8350_LS_PROT 0x0001
  357. #define WM8350_LS_PROT_MASK 0x0001
  358. #define WM8350_LS_PROT_SHIFT 0
  359. /* Bit values for R199 (0xC7) */
  360. #define WM8350_LS_ERRACT_NONE 0
  361. #define WM8350_LS_ERRACT_SHUTDOWN_CONV 1
  362. #define WM8350_LS_ERRACT_SHUTDOWN_SYS 2
  363. /*
  364. * R200 (0xC8) - LDO1 Control
  365. */
  366. #define WM8350_LDO1_SWI 0x4000
  367. #define WM8350_LDO1_OPFLT 0x0400
  368. #define WM8350_LDO1_VSEL_MASK 0x001F
  369. #define WM8350_LDO1_VSEL_SHIFT 0
  370. /*
  371. * R201 (0xC9) - LDO1 Timeouts
  372. */
  373. #define WM8350_LDO1_ERRACT_MASK 0xC000
  374. #define WM8350_LDO1_ERRACT_SHIFT 14
  375. #define WM8350_LDO1_ENSLOT_MASK 0x3C00
  376. #define WM8350_LDO1_ENSLOT_SHIFT 10
  377. #define WM8350_LDO1_SDSLOT_MASK 0x03C0
  378. #define WM8350_LDO1_UVTO_MASK 0x0030
  379. #define WM8350_LDO1_SDSLOT_SHIFT 6
  380. /* Bit values for R201 (0xC9) */
  381. #define WM8350_LDO1_ERRACT_NONE 0
  382. #define WM8350_LDO1_ERRACT_SHUTDOWN_CONV 1
  383. #define WM8350_LDO1_ERRACT_SHUTDOWN_SYS 2
  384. /*
  385. * R202 (0xCA) - LDO1 Low Power
  386. */
  387. #define WM8350_LDO1_HIB_MODE_MASK 0x3000
  388. #define WM8350_LDO1_HIB_TRIG_MASK 0x0300
  389. #define WM8350_LDO1_VIMG_MASK 0x001F
  390. #define WM8350_LDO1_HIB_MODE_DIS (0x1 << 12)
  391. /*
  392. * R203 (0xCB) - LDO2 Control
  393. */
  394. #define WM8350_LDO2_SWI 0x4000
  395. #define WM8350_LDO2_OPFLT 0x0400
  396. #define WM8350_LDO2_VSEL_MASK 0x001F
  397. #define WM8350_LDO2_VSEL_SHIFT 0
  398. /*
  399. * R204 (0xCC) - LDO2 Timeouts
  400. */
  401. #define WM8350_LDO2_ERRACT_MASK 0xC000
  402. #define WM8350_LDO2_ERRACT_SHIFT 14
  403. #define WM8350_LDO2_ENSLOT_MASK 0x3C00
  404. #define WM8350_LDO2_ENSLOT_SHIFT 10
  405. #define WM8350_LDO2_SDSLOT_MASK 0x03C0
  406. #define WM8350_LDO2_SDSLOT_SHIFT 6
  407. /* Bit values for R204 (0xCC) */
  408. #define WM8350_LDO2_ERRACT_NONE 0
  409. #define WM8350_LDO2_ERRACT_SHUTDOWN_CONV 1
  410. #define WM8350_LDO2_ERRACT_SHUTDOWN_SYS 2
  411. /*
  412. * R205 (0xCD) - LDO2 Low Power
  413. */
  414. #define WM8350_LDO2_HIB_MODE_MASK 0x3000
  415. #define WM8350_LDO2_HIB_TRIG_MASK 0x0300
  416. #define WM8350_LDO2_VIMG_MASK 0x001F
  417. /*
  418. * R206 (0xCE) - LDO3 Control
  419. */
  420. #define WM8350_LDO3_SWI 0x4000
  421. #define WM8350_LDO3_OPFLT 0x0400
  422. #define WM8350_LDO3_VSEL_MASK 0x001F
  423. #define WM8350_LDO3_VSEL_SHIFT 0
  424. /*
  425. * R207 (0xCF) - LDO3 Timeouts
  426. */
  427. #define WM8350_LDO3_ERRACT_MASK 0xC000
  428. #define WM8350_LDO3_ERRACT_SHIFT 14
  429. #define WM8350_LDO3_ENSLOT_MASK 0x3C00
  430. #define WM8350_LDO3_ENSLOT_SHIFT 10
  431. #define WM8350_LDO3_SDSLOT_MASK 0x03C0
  432. #define WM8350_LDO3_UVTO_MASK 0x0030
  433. #define WM8350_LDO3_SDSLOT_SHIFT 6
  434. /* Bit values for R207 (0xCF) */
  435. #define WM8350_LDO3_ERRACT_NONE 0
  436. #define WM8350_LDO3_ERRACT_SHUTDOWN_CONV 1
  437. #define WM8350_LDO3_ERRACT_SHUTDOWN_SYS 2
  438. /*
  439. * R208 (0xD0) - LDO3 Low Power
  440. */
  441. #define WM8350_LDO3_HIB_MODE_MASK 0x3000
  442. #define WM8350_LDO3_HIB_TRIG_MASK 0x0300
  443. #define WM8350_LDO3_VIMG_MASK 0x001F
  444. /*
  445. * R209 (0xD1) - LDO4 Control
  446. */
  447. #define WM8350_LDO4_SWI 0x4000
  448. #define WM8350_LDO4_OPFLT 0x0400
  449. #define WM8350_LDO4_VSEL_MASK 0x001F
  450. #define WM8350_LDO4_VSEL_SHIFT 0
  451. /*
  452. * R210 (0xD2) - LDO4 Timeouts
  453. */
  454. #define WM8350_LDO4_ERRACT_MASK 0xC000
  455. #define WM8350_LDO4_ERRACT_SHIFT 14
  456. #define WM8350_LDO4_ENSLOT_MASK 0x3C00
  457. #define WM8350_LDO4_ENSLOT_SHIFT 10
  458. #define WM8350_LDO4_SDSLOT_MASK 0x03C0
  459. #define WM8350_LDO4_UVTO_MASK 0x0030
  460. #define WM8350_LDO4_SDSLOT_SHIFT 6
  461. /* Bit values for R210 (0xD2) */
  462. #define WM8350_LDO4_ERRACT_NONE 0
  463. #define WM8350_LDO4_ERRACT_SHUTDOWN_CONV 1
  464. #define WM8350_LDO4_ERRACT_SHUTDOWN_SYS 2
  465. /*
  466. * R211 (0xD3) - LDO4 Low Power
  467. */
  468. #define WM8350_LDO4_HIB_MODE_MASK 0x3000
  469. #define WM8350_LDO4_HIB_TRIG_MASK 0x0300
  470. #define WM8350_LDO4_VIMG_MASK 0x001F
  471. /*
  472. * R215 (0xD7) - VCC_FAULT Masks
  473. */
  474. #define WM8350_LS_FAULT 0x8000
  475. #define WM8350_LDO4_FAULT 0x0800
  476. #define WM8350_LDO3_FAULT 0x0400
  477. #define WM8350_LDO2_FAULT 0x0200
  478. #define WM8350_LDO1_FAULT 0x0100
  479. #define WM8350_DC6_FAULT 0x0020
  480. #define WM8350_DC5_FAULT 0x0010
  481. #define WM8350_DC4_FAULT 0x0008
  482. #define WM8350_DC3_FAULT 0x0004
  483. #define WM8350_DC2_FAULT 0x0002
  484. #define WM8350_DC1_FAULT 0x0001
  485. /*
  486. * R216 (0xD8) - Main Bandgap Control
  487. */
  488. #define WM8350_MBG_LOAD_FUSES 0x8000
  489. #define WM8350_MBG_FUSE_WPREP 0x4000
  490. #define WM8350_MBG_FUSE_WRITE 0x2000
  491. #define WM8350_MBG_FUSE_TRIM_MASK 0x1F00
  492. #define WM8350_MBG_TRIM_SRC 0x0020
  493. #define WM8350_MBG_USER_TRIM_MASK 0x001F
  494. /*
  495. * R217 (0xD9) - OSC Control
  496. */
  497. #define WM8350_OSC_LOAD_FUSES 0x8000
  498. #define WM8350_OSC_FUSE_WPREP 0x4000
  499. #define WM8350_OSC_FUSE_WRITE 0x2000
  500. #define WM8350_OSC_FUSE_TRIM_MASK 0x0F00
  501. #define WM8350_OSC_TRIM_SRC 0x0020
  502. #define WM8350_OSC_USER_TRIM_MASK 0x000F
  503. /*
  504. * R248 (0xF8) - DCDC1 Force PWM
  505. */
  506. #define WM8350_DCDC1_FORCE_PWM_ENA 0x0010
  507. /*
  508. * R250 (0xFA) - DCDC3 Force PWM
  509. */
  510. #define WM8350_DCDC3_FORCE_PWM_ENA 0x0010
  511. /*
  512. * R251 (0xFB) - DCDC4 Force PWM
  513. */
  514. #define WM8350_DCDC4_FORCE_PWM_ENA 0x0010
  515. /*
  516. * R253 (0xFD) - DCDC1 Force PWM
  517. */
  518. #define WM8350_DCDC6_FORCE_PWM_ENA 0x0010
  519. /*
  520. * DCDC's
  521. */
  522. #define WM8350_DCDC_1 0
  523. #define WM8350_DCDC_2 1
  524. #define WM8350_DCDC_3 2
  525. #define WM8350_DCDC_4 3
  526. #define WM8350_DCDC_5 4
  527. #define WM8350_DCDC_6 5
  528. /* DCDC modes */
  529. #define WM8350_DCDC_ACTIVE_STANDBY 0
  530. #define WM8350_DCDC_ACTIVE_PULSE 1
  531. #define WM8350_DCDC_SLEEP_NORMAL 0
  532. #define WM8350_DCDC_SLEEP_LOW 1
  533. /* DCDC Low power (Hibernate) mode */
  534. #define WM8350_DCDC_HIB_MODE_CUR (0 << 12)
  535. #define WM8350_DCDC_HIB_MODE_IMAGE (1 << 12)
  536. #define WM8350_DCDC_HIB_MODE_STANDBY (2 << 12)
  537. #define WM8350_DCDC_HIB_MODE_LDO (4 << 12)
  538. #define WM8350_DCDC_HIB_MODE_LDO_IM (5 << 12)
  539. #define WM8350_DCDC_HIB_MODE_DIS (7 << 12)
  540. #define WM8350_DCDC_HIB_MODE_MASK (7 << 12)
  541. /* DCDC Low Power (Hibernate) signal */
  542. #define WM8350_DCDC_HIB_SIG_REG (0 << 8)
  543. #define WM8350_DCDC_HIB_SIG_LPWR1 (1 << 8)
  544. #define WM8350_DCDC_HIB_SIG_LPWR2 (2 << 8)
  545. #define WM8350_DCDC_HIB_SIG_LPWR3 (3 << 8)
  546. /* LDO Low power (Hibernate) mode */
  547. #define WM8350_LDO_HIB_MODE_IMAGE (0 << 0)
  548. #define WM8350_LDO_HIB_MODE_DIS (1 << 0)
  549. /* LDO Low Power (Hibernate) signal */
  550. #define WM8350_LDO_HIB_SIG_REG (0 << 8)
  551. #define WM8350_LDO_HIB_SIG_LPWR1 (1 << 8)
  552. #define WM8350_LDO_HIB_SIG_LPWR2 (2 << 8)
  553. #define WM8350_LDO_HIB_SIG_LPWR3 (3 << 8)
  554. /*
  555. * LDOs
  556. */
  557. #define WM8350_LDO_1 6
  558. #define WM8350_LDO_2 7
  559. #define WM8350_LDO_3 8
  560. #define WM8350_LDO_4 9
  561. /*
  562. * ISINKs
  563. */
  564. #define WM8350_ISINK_A 10
  565. #define WM8350_ISINK_B 11
  566. #define WM8350_ISINK_MODE_BOOST 0
  567. #define WM8350_ISINK_MODE_SWITCH 1
  568. #define WM8350_ISINK_ILIM_NORMAL 0
  569. #define WM8350_ISINK_ILIM_LOW 1
  570. #define WM8350_ISINK_FLASH_DISABLE 0
  571. #define WM8350_ISINK_FLASH_ENABLE 1
  572. #define WM8350_ISINK_FLASH_TRIG_BIT 0
  573. #define WM8350_ISINK_FLASH_TRIG_GPIO 1
  574. #define WM8350_ISINK_FLASH_MODE_EN (1 << 13)
  575. #define WM8350_ISINK_FLASH_MODE_DIS (0 << 13)
  576. #define WM8350_ISINK_FLASH_DUR_32MS (0 << 8)
  577. #define WM8350_ISINK_FLASH_DUR_64MS (1 << 8)
  578. #define WM8350_ISINK_FLASH_DUR_96MS (2 << 8)
  579. #define WM8350_ISINK_FLASH_DUR_1024MS (3 << 8)
  580. #define WM8350_ISINK_FLASH_ON_INSTANT (0 << 0)
  581. #define WM8350_ISINK_FLASH_ON_0_25S (1 << 0)
  582. #define WM8350_ISINK_FLASH_ON_0_50S (2 << 0)
  583. #define WM8350_ISINK_FLASH_ON_1_00S (3 << 0)
  584. #define WM8350_ISINK_FLASH_ON_1_95S (1 << 0)
  585. #define WM8350_ISINK_FLASH_ON_3_91S (2 << 0)
  586. #define WM8350_ISINK_FLASH_ON_7_80S (3 << 0)
  587. #define WM8350_ISINK_FLASH_OFF_INSTANT (0 << 4)
  588. #define WM8350_ISINK_FLASH_OFF_0_25S (1 << 4)
  589. #define WM8350_ISINK_FLASH_OFF_0_50S (2 << 4)
  590. #define WM8350_ISINK_FLASH_OFF_1_00S (3 << 4)
  591. #define WM8350_ISINK_FLASH_OFF_1_95S (1 << 4)
  592. #define WM8350_ISINK_FLASH_OFF_3_91S (2 << 4)
  593. #define WM8350_ISINK_FLASH_OFF_7_80S (3 << 4)
  594. /*
  595. * Regulator Interrupts.
  596. */
  597. #define WM8350_IRQ_CS1 13
  598. #define WM8350_IRQ_CS2 14
  599. #define WM8350_IRQ_UV_LDO4 25
  600. #define WM8350_IRQ_UV_LDO3 26
  601. #define WM8350_IRQ_UV_LDO2 27
  602. #define WM8350_IRQ_UV_LDO1 28
  603. #define WM8350_IRQ_UV_DC6 29
  604. #define WM8350_IRQ_UV_DC5 30
  605. #define WM8350_IRQ_UV_DC4 31
  606. #define WM8350_IRQ_UV_DC3 32
  607. #define WM8350_IRQ_UV_DC2 33
  608. #define WM8350_IRQ_UV_DC1 34
  609. #define WM8350_IRQ_OC_LS 35
  610. #define NUM_WM8350_REGULATORS 12
  611. struct wm8350;
  612. struct platform_device;
  613. struct regulator_init_data;
  614. /*
  615. * WM8350 LED platform data
  616. */
  617. struct wm8350_led_platform_data {
  618. const char *name;
  619. const char *default_trigger;
  620. int max_uA;
  621. };
  622. struct wm8350_led {
  623. struct platform_device *pdev;
  624. struct work_struct work;
  625. spinlock_t value_lock;
  626. enum led_brightness value;
  627. struct led_classdev cdev;
  628. int max_uA_index;
  629. int enabled;
  630. struct regulator *isink;
  631. struct regulator_consumer_supply isink_consumer;
  632. struct regulator_init_data isink_init;
  633. struct regulator *dcdc;
  634. struct regulator_consumer_supply dcdc_consumer;
  635. struct regulator_init_data dcdc_init;
  636. };
  637. struct wm8350_pmic {
  638. /* Number of regulators of each type on this device */
  639. int max_dcdc;
  640. int max_isink;
  641. /* ISINK to DCDC mapping */
  642. int isink_A_dcdc;
  643. int isink_B_dcdc;
  644. /* hibernate configs */
  645. u16 dcdc1_hib_mode;
  646. u16 dcdc3_hib_mode;
  647. u16 dcdc4_hib_mode;
  648. u16 dcdc6_hib_mode;
  649. /* regulator devices */
  650. struct platform_device *pdev[NUM_WM8350_REGULATORS];
  651. /* LED devices */
  652. struct wm8350_led led[2];
  653. };
  654. int wm8350_register_regulator(struct wm8350 *wm8350, int reg,
  655. struct regulator_init_data *initdata);
  656. int wm8350_register_led(struct wm8350 *wm8350, int lednum, int dcdc, int isink,
  657. struct wm8350_led_platform_data *pdata);
  658. /*
  659. * Additional DCDC control not supported via regulator API
  660. */
  661. int wm8350_dcdc_set_slot(struct wm8350 *wm8350, int dcdc, u16 start,
  662. u16 stop, u16 fault);
  663. int wm8350_dcdc25_set_mode(struct wm8350 *wm8350, int dcdc, u16 mode,
  664. u16 ilim, u16 ramp, u16 feedback);
  665. /*
  666. * Additional LDO control not supported via regulator API
  667. */
  668. int wm8350_ldo_set_slot(struct wm8350 *wm8350, int ldo, u16 start, u16 stop);
  669. /*
  670. * Additional ISINK control not supported via regulator API
  671. */
  672. int wm8350_isink_set_flash(struct wm8350 *wm8350, int isink, u16 mode,
  673. u16 trigger, u16 duration, u16 on_ramp,
  674. u16 off_ramp, u16 drive);
  675. #endif