brcmphy.h 14 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #ifndef _LINUX_BRCMPHY_H
  3. #define _LINUX_BRCMPHY_H
  4. #include <linux/phy.h>
  5. /* All Broadcom Ethernet switches have a pseudo-PHY at address 30 which is used
  6. * to configure the switch internal registers via MDIO accesses.
  7. */
  8. #define BRCM_PSEUDO_PHY_ADDR 30
  9. #define PHY_ID_BCM50610 0x0143bd60
  10. #define PHY_ID_BCM50610M 0x0143bd70
  11. #define PHY_ID_BCM5241 0x0143bc30
  12. #define PHY_ID_BCMAC131 0x0143bc70
  13. #define PHY_ID_BCM5481 0x0143bca0
  14. #define PHY_ID_BCM5395 0x0143bcf0
  15. #define PHY_ID_BCM53125 0x03625f20
  16. #define PHY_ID_BCM53128 0x03625e10
  17. #define PHY_ID_BCM54810 0x03625d00
  18. #define PHY_ID_BCM54811 0x03625cc0
  19. #define PHY_ID_BCM5482 0x0143bcb0
  20. #define PHY_ID_BCM5411 0x00206070
  21. #define PHY_ID_BCM5421 0x002060e0
  22. #define PHY_ID_BCM54210E 0x600d84a0
  23. #define PHY_ID_BCM5464 0x002060b0
  24. #define PHY_ID_BCM5461 0x002060c0
  25. #define PHY_ID_BCM54612E 0x03625e60
  26. #define PHY_ID_BCM54616S 0x03625d10
  27. #define PHY_ID_BCM54140 0xae025009
  28. #define PHY_ID_BCM57780 0x03625d90
  29. #define PHY_ID_BCM89610 0x03625cd0
  30. #define PHY_ID_BCM72113 0x35905310
  31. #define PHY_ID_BCM72116 0x35905350
  32. #define PHY_ID_BCM72165 0x35905340
  33. #define PHY_ID_BCM7250 0xae025280
  34. #define PHY_ID_BCM7255 0xae025120
  35. #define PHY_ID_BCM7260 0xae025190
  36. #define PHY_ID_BCM7268 0xae025090
  37. #define PHY_ID_BCM7271 0xae0253b0
  38. #define PHY_ID_BCM7278 0xae0251a0
  39. #define PHY_ID_BCM7364 0xae025260
  40. #define PHY_ID_BCM7366 0x600d8490
  41. #define PHY_ID_BCM7346 0x600d8650
  42. #define PHY_ID_BCM7362 0x600d84b0
  43. #define PHY_ID_BCM7425 0x600d86b0
  44. #define PHY_ID_BCM7429 0x600d8730
  45. #define PHY_ID_BCM7435 0x600d8750
  46. #define PHY_ID_BCM74371 0xae0252e0
  47. #define PHY_ID_BCM7439 0x600d8480
  48. #define PHY_ID_BCM7439_2 0xae025080
  49. #define PHY_ID_BCM7445 0x600d8510
  50. #define PHY_ID_BCM7712 0x35905330
  51. #define PHY_ID_BCM_CYGNUS 0xae025200
  52. #define PHY_ID_BCM_OMEGA 0xae025100
  53. #define PHY_BCM_OUI_MASK 0xfffffc00
  54. #define PHY_BCM_OUI_1 0x00206000
  55. #define PHY_BCM_OUI_2 0x0143bc00
  56. #define PHY_BCM_OUI_3 0x03625c00
  57. #define PHY_BCM_OUI_4 0x600d8400
  58. #define PHY_BCM_OUI_5 0x03625e00
  59. #define PHY_BCM_OUI_6 0xae025000
  60. #define PHY_BRCM_AUTO_PWRDWN_ENABLE 0x00000001
  61. #define PHY_BRCM_RX_REFCLK_UNUSED 0x00000002
  62. #define PHY_BRCM_CLEAR_RGMII_MODE 0x00000004
  63. #define PHY_BRCM_DIS_TXCRXC_NOENRGY 0x00000008
  64. #define PHY_BRCM_EN_MASTER_MODE 0x00000010
  65. #define PHY_BRCM_IDDQ_SUSPEND 0x00000020
  66. /* Broadcom BCM7xxx specific workarounds */
  67. #define PHY_BRCM_7XXX_REV(x) (((x) >> 8) & 0xff)
  68. #define PHY_BRCM_7XXX_PATCH(x) ((x) & 0xff)
  69. #define PHY_BCM_FLAGS_VALID 0x80000000
  70. /* Broadcom BCM54XX register definitions, common to most Broadcom PHYs */
  71. #define MII_BCM54XX_ECR 0x10 /* BCM54xx extended control register */
  72. #define MII_BCM54XX_ECR_IM 0x1000 /* Interrupt mask */
  73. #define MII_BCM54XX_ECR_IF 0x0800 /* Interrupt force */
  74. #define MII_BCM54XX_ECR_FIFOE 0x0001 /* FIFO elasticity */
  75. #define MII_BCM54XX_ESR 0x11 /* BCM54xx extended status register */
  76. #define MII_BCM54XX_ESR_IS 0x1000 /* Interrupt status */
  77. #define MII_BCM54XX_EXP_DATA 0x15 /* Expansion register data */
  78. #define MII_BCM54XX_EXP_SEL 0x17 /* Expansion register select */
  79. #define MII_BCM54XX_EXP_SEL_TOP 0x0d00 /* TOP_MISC expansion register select */
  80. #define MII_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */
  81. #define MII_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */
  82. #define MII_BCM54XX_EXP_SEL_ETC 0x0d00 /* Expansion register spare + 2k mem */
  83. #define MII_BCM54XX_AUX_CTL 0x18 /* Auxiliary control register */
  84. #define MII_BCM54XX_ISR 0x1a /* BCM54xx interrupt status register */
  85. #define MII_BCM54XX_IMR 0x1b /* BCM54xx interrupt mask register */
  86. #define MII_BCM54XX_INT_CRCERR 0x0001 /* CRC error */
  87. #define MII_BCM54XX_INT_LINK 0x0002 /* Link status changed */
  88. #define MII_BCM54XX_INT_SPEED 0x0004 /* Link speed change */
  89. #define MII_BCM54XX_INT_DUPLEX 0x0008 /* Duplex mode changed */
  90. #define MII_BCM54XX_INT_LRS 0x0010 /* Local receiver status changed */
  91. #define MII_BCM54XX_INT_RRS 0x0020 /* Remote receiver status changed */
  92. #define MII_BCM54XX_INT_SSERR 0x0040 /* Scrambler synchronization error */
  93. #define MII_BCM54XX_INT_UHCD 0x0080 /* Unsupported HCD negotiated */
  94. #define MII_BCM54XX_INT_NHCD 0x0100 /* No HCD */
  95. #define MII_BCM54XX_INT_NHCDL 0x0200 /* No HCD link */
  96. #define MII_BCM54XX_INT_ANPR 0x0400 /* Auto-negotiation page received */
  97. #define MII_BCM54XX_INT_LC 0x0800 /* All counters below 128 */
  98. #define MII_BCM54XX_INT_HC 0x1000 /* Counter above 32768 */
  99. #define MII_BCM54XX_INT_MDIX 0x2000 /* MDIX status change */
  100. #define MII_BCM54XX_INT_PSERR 0x4000 /* Pair swap error */
  101. #define MII_BCM54XX_SHD 0x1c /* 0x1c shadow registers */
  102. #define MII_BCM54XX_SHD_WRITE 0x8000
  103. #define MII_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10)
  104. #define MII_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0)
  105. #define MII_BCM54XX_RDB_ADDR 0x1e
  106. #define MII_BCM54XX_RDB_DATA 0x1f
  107. /* legacy access control via rdb/expansion register */
  108. #define BCM54XX_RDB_REG0087 0x0087
  109. #define BCM54XX_EXP_REG7E (MII_BCM54XX_EXP_SEL_ER + 0x7E)
  110. #define BCM54XX_ACCESS_MODE_LEGACY_EN BIT(15)
  111. /*
  112. * AUXILIARY CONTROL SHADOW ACCESS REGISTERS. (PHY REG 0x18)
  113. */
  114. #define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x00
  115. #define MII_BCM54XX_AUXCTL_ACTL_TX_6DB 0x0400
  116. #define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA 0x0800
  117. #define MII_BCM54XX_AUXCTL_ACTL_EXT_PKT_LEN 0x4000
  118. #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x07
  119. #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN 0x0010
  120. #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_EN 0x0080
  121. #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN 0x0100
  122. #define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200
  123. #define MII_BCM54XX_AUXCTL_MISC_WREN 0x8000
  124. #define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT 12
  125. #define MII_BCM54XX_AUXCTL_SHDWSEL_MASK 0x0007
  126. /*
  127. * Broadcom LED source encodings. These are used in BCM5461, BCM5481,
  128. * BCM5482, and possibly some others.
  129. */
  130. #define BCM_LED_SRC_LINKSPD1 0x0
  131. #define BCM_LED_SRC_LINKSPD2 0x1
  132. #define BCM_LED_SRC_XMITLED 0x2
  133. #define BCM_LED_SRC_ACTIVITYLED 0x3
  134. #define BCM_LED_SRC_FDXLED 0x4
  135. #define BCM_LED_SRC_SLAVE 0x5
  136. #define BCM_LED_SRC_INTR 0x6
  137. #define BCM_LED_SRC_QUALITY 0x7
  138. #define BCM_LED_SRC_RCVLED 0x8
  139. #define BCM_LED_SRC_WIRESPEED 0x9
  140. #define BCM_LED_SRC_MULTICOLOR1 0xa
  141. #define BCM_LED_SRC_OPENSHORT 0xb
  142. #define BCM_LED_SRC_OFF 0xe /* Tied high */
  143. #define BCM_LED_SRC_ON 0xf /* Tied low */
  144. /*
  145. * Broadcom Multicolor LED configurations (expansion register 4)
  146. */
  147. #define BCM_EXP_MULTICOLOR (MII_BCM54XX_EXP_SEL_ER + 0x04)
  148. #define BCM_LED_MULTICOLOR_IN_PHASE BIT(8)
  149. #define BCM_LED_MULTICOLOR_LINK_ACT 0x0
  150. #define BCM_LED_MULTICOLOR_SPEED 0x1
  151. #define BCM_LED_MULTICOLOR_ACT_FLASH 0x2
  152. #define BCM_LED_MULTICOLOR_FDX 0x3
  153. #define BCM_LED_MULTICOLOR_OFF 0x4
  154. #define BCM_LED_MULTICOLOR_ON 0x5
  155. #define BCM_LED_MULTICOLOR_ALT 0x6
  156. #define BCM_LED_MULTICOLOR_FLASH 0x7
  157. #define BCM_LED_MULTICOLOR_LINK 0x8
  158. #define BCM_LED_MULTICOLOR_ACT 0x9
  159. #define BCM_LED_MULTICOLOR_PROGRAM 0xa
  160. /*
  161. * BCM5482: Shadow registers
  162. * Shadow values go into bits [14:10] of register 0x1c to select a shadow
  163. * register to access.
  164. */
  165. /* 00100: Reserved control register 2 */
  166. #define BCM54XX_SHD_SCR2 0x04
  167. #define BCM54XX_SHD_SCR2_WSPD_RTRY_DIS 0x100
  168. #define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT 2
  169. #define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET 2
  170. #define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK 0x7
  171. /* 00101: Spare Control Register 3 */
  172. #define BCM54XX_SHD_SCR3 0x05
  173. #define BCM54XX_SHD_SCR3_DEF_CLK125 0x0001
  174. #define BCM54XX_SHD_SCR3_DLLAPD_DIS 0x0002
  175. #define BCM54XX_SHD_SCR3_TRDDAPD 0x0004
  176. #define BCM54XX_SHD_SCR3_RXCTXC_DIS 0x0100
  177. /* 01010: Auto Power-Down */
  178. #define BCM54XX_SHD_APD 0x0a
  179. #define BCM_APD_CLR_MASK 0xFE9F /* clear bits 5, 6 & 8 */
  180. #define BCM54XX_SHD_APD_EN 0x0020
  181. #define BCM_NO_ANEG_APD_EN 0x0060 /* bits 5 & 6 */
  182. #define BCM_APD_SINGLELP_EN 0x0100 /* Bit 8 */
  183. #define BCM5482_SHD_LEDS1 0x0d /* 01101: LED Selector 1 */
  184. /* LED3 / ~LINKSPD[2] selector */
  185. #define BCM5482_SHD_LEDS1_LED3(src) ((src & 0xf) << 4)
  186. /* LED1 / ~LINKSPD[1] selector */
  187. #define BCM5482_SHD_LEDS1_LED1(src) ((src & 0xf) << 0)
  188. #define BCM54XX_SHD_RGMII_MODE 0x0b /* 01011: RGMII Mode Selector */
  189. #define BCM5482_SHD_SSD 0x14 /* 10100: Secondary SerDes control */
  190. #define BCM5482_SHD_SSD_LEDM 0x0008 /* SSD LED Mode enable */
  191. #define BCM5482_SHD_SSD_EN 0x0001 /* SSD enable */
  192. /* 10011: SerDes 100-FX Control Register */
  193. #define BCM54616S_SHD_100FX_CTRL 0x13
  194. #define BCM54616S_100FX_MODE BIT(0) /* 100-FX SerDes Enable */
  195. /* 11111: Mode Control Register */
  196. #define BCM54XX_SHD_MODE 0x1f
  197. #define BCM54XX_SHD_INTF_SEL_MASK GENMASK(2, 1) /* INTERF_SEL[1:0] */
  198. #define BCM54XX_SHD_INTF_SEL_RGMII 0x02
  199. #define BCM54XX_SHD_INTF_SEL_SGMII 0x04
  200. #define BCM54XX_SHD_INTF_SEL_GBIC 0x06
  201. #define BCM54XX_SHD_MODE_1000BX BIT(0) /* Enable 1000-X registers */
  202. /*
  203. * EXPANSION SHADOW ACCESS REGISTERS. (PHY REG 0x15, 0x16, and 0x17)
  204. */
  205. #define MII_BCM54XX_EXP_AADJ1CH0 0x001f
  206. #define MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN 0x0200
  207. #define MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF 0x0100
  208. #define MII_BCM54XX_EXP_AADJ1CH3 0x601f
  209. #define MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ 0x0002
  210. #define MII_BCM54XX_EXP_EXP08 0x0F08
  211. #define MII_BCM54XX_EXP_EXP08_RJCT_2MHZ 0x0001
  212. #define MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE 0x0200
  213. #define MII_BCM54XX_EXP_EXP08_FORCE_DAC_WAKE 0x0100
  214. #define MII_BCM54XX_EXP_EXP75 0x0f75
  215. #define MII_BCM54XX_EXP_EXP75_VDACCTRL 0x003c
  216. #define MII_BCM54XX_EXP_EXP75_CM_OSC 0x0001
  217. #define MII_BCM54XX_EXP_EXP96 0x0f96
  218. #define MII_BCM54XX_EXP_EXP96_MYST 0x0010
  219. #define MII_BCM54XX_EXP_EXP97 0x0f97
  220. #define MII_BCM54XX_EXP_EXP97_MYST 0x0c0c
  221. /* Top-MISC expansion registers */
  222. #define BCM54XX_TOP_MISC_IDDQ_CTRL (MII_BCM54XX_EXP_SEL_TOP + 0x06)
  223. #define BCM54XX_TOP_MISC_IDDQ_LP (1 << 0)
  224. #define BCM54XX_TOP_MISC_IDDQ_SD (1 << 2)
  225. #define BCM54XX_TOP_MISC_IDDQ_SR (1 << 3)
  226. /*
  227. * BCM5482: Secondary SerDes registers
  228. */
  229. #define BCM5482_SSD_1000BX_CTL 0x00 /* 1000BASE-X Control */
  230. #define BCM5482_SSD_1000BX_CTL_PWRDOWN 0x0800 /* Power-down SSD */
  231. #define BCM5482_SSD_SGMII_SLAVE 0x15 /* SGMII Slave Register */
  232. #define BCM5482_SSD_SGMII_SLAVE_EN 0x0002 /* Slave mode enable */
  233. #define BCM5482_SSD_SGMII_SLAVE_AD 0x0001 /* Slave auto-detection */
  234. /* BCM54810 Registers */
  235. #define BCM54810_EXP_BROADREACH_LRE_MISC_CTL (MII_BCM54XX_EXP_SEL_ER + 0x90)
  236. #define BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN (1 << 0)
  237. #define BCM54810_SHD_CLK_CTL 0x3
  238. #define BCM54810_SHD_CLK_CTL_GTXCLK_EN (1 << 9)
  239. /* BCM54612E Registers */
  240. #define BCM54612E_EXP_SPARE0 (MII_BCM54XX_EXP_SEL_ETC + 0x34)
  241. #define BCM54612E_LED4_CLK125OUT_EN (1 << 1)
  242. /*****************************************************************************/
  243. /* Fast Ethernet Transceiver definitions. */
  244. /*****************************************************************************/
  245. #define MII_BRCM_FET_INTREG 0x1a /* Interrupt register */
  246. #define MII_BRCM_FET_IR_MASK 0x0100 /* Mask all interrupts */
  247. #define MII_BRCM_FET_IR_LINK_EN 0x0200 /* Link status change enable */
  248. #define MII_BRCM_FET_IR_SPEED_EN 0x0400 /* Link speed change enable */
  249. #define MII_BRCM_FET_IR_DUPLEX_EN 0x0800 /* Duplex mode change enable */
  250. #define MII_BRCM_FET_IR_ENABLE 0x4000 /* Interrupt enable */
  251. #define MII_BRCM_FET_BRCMTEST 0x1f /* Brcm test register */
  252. #define MII_BRCM_FET_BT_SRE 0x0080 /* Shadow register enable */
  253. /*** Shadow register definitions ***/
  254. #define MII_BRCM_FET_SHDW_MISCCTRL 0x10 /* Shadow misc ctrl */
  255. #define MII_BRCM_FET_SHDW_MC_FAME 0x4000 /* Force Auto MDIX enable */
  256. #define MII_BRCM_FET_SHDW_AUXMODE4 0x1a /* Auxiliary mode 4 */
  257. #define MII_BRCM_FET_SHDW_AM4_STANDBY 0x0008 /* Standby enable */
  258. #define MII_BRCM_FET_SHDW_AM4_LED_MASK 0x0003
  259. #define MII_BRCM_FET_SHDW_AM4_LED_MODE1 0x0001
  260. #define MII_BRCM_FET_SHDW_AUXSTAT2 0x1b /* Auxiliary status 2 */
  261. #define MII_BRCM_FET_SHDW_AS2_APDE 0x0020 /* Auto power down enable */
  262. #define BRCM_CL45VEN_EEE_CONTROL 0x803d
  263. #define LPI_FEATURE_EN 0x8000
  264. #define LPI_FEATURE_EN_DIG1000X 0x4000
  265. /* Core register definitions*/
  266. #define MII_BRCM_CORE_BASE12 0x12
  267. #define MII_BRCM_CORE_BASE13 0x13
  268. #define MII_BRCM_CORE_BASE14 0x14
  269. #define MII_BRCM_CORE_BASE1E 0x1E
  270. #define MII_BRCM_CORE_EXPB0 0xB0
  271. #define MII_BRCM_CORE_EXPB1 0xB1
  272. /* Enhanced Cable Diagnostics */
  273. #define BCM54XX_RDB_ECD_CTRL 0x2a0
  274. #define BCM54XX_EXP_ECD_CTRL (MII_BCM54XX_EXP_SEL_ER + 0xc0)
  275. #define BCM54XX_ECD_CTRL_CABLE_TYPE_CAT3 1 /* CAT3 or worse */
  276. #define BCM54XX_ECD_CTRL_CABLE_TYPE_CAT5 0 /* CAT5 or better */
  277. #define BCM54XX_ECD_CTRL_CABLE_TYPE_MASK BIT(0) /* cable type */
  278. #define BCM54XX_ECD_CTRL_INVALID BIT(3) /* invalid result */
  279. #define BCM54XX_ECD_CTRL_UNIT_CM 0 /* centimeters */
  280. #define BCM54XX_ECD_CTRL_UNIT_M 1 /* meters */
  281. #define BCM54XX_ECD_CTRL_UNIT_MASK BIT(10) /* cable length unit */
  282. #define BCM54XX_ECD_CTRL_IN_PROGRESS BIT(11) /* test in progress */
  283. #define BCM54XX_ECD_CTRL_BREAK_LINK BIT(12) /* unconnect link
  284. * during test
  285. */
  286. #define BCM54XX_ECD_CTRL_CROSS_SHORT_DIS BIT(13) /* disable inter-pair
  287. * short check
  288. */
  289. #define BCM54XX_ECD_CTRL_RUN BIT(15) /* run immediate */
  290. #define BCM54XX_RDB_ECD_FAULT_TYPE 0x2a1
  291. #define BCM54XX_EXP_ECD_FAULT_TYPE (MII_BCM54XX_EXP_SEL_ER + 0xc1)
  292. #define BCM54XX_ECD_FAULT_TYPE_INVALID 0x0
  293. #define BCM54XX_ECD_FAULT_TYPE_OK 0x1
  294. #define BCM54XX_ECD_FAULT_TYPE_OPEN 0x2
  295. #define BCM54XX_ECD_FAULT_TYPE_SAME_SHORT 0x3 /* short same pair */
  296. #define BCM54XX_ECD_FAULT_TYPE_CROSS_SHORT 0x4 /* short different pairs */
  297. #define BCM54XX_ECD_FAULT_TYPE_BUSY 0x9
  298. #define BCM54XX_ECD_FAULT_TYPE_PAIR_D_MASK GENMASK(3, 0)
  299. #define BCM54XX_ECD_FAULT_TYPE_PAIR_C_MASK GENMASK(7, 4)
  300. #define BCM54XX_ECD_FAULT_TYPE_PAIR_B_MASK GENMASK(11, 8)
  301. #define BCM54XX_ECD_FAULT_TYPE_PAIR_A_MASK GENMASK(15, 12)
  302. #define BCM54XX_ECD_PAIR_A_LENGTH_RESULTS 0x2a2
  303. #define BCM54XX_ECD_PAIR_B_LENGTH_RESULTS 0x2a3
  304. #define BCM54XX_ECD_PAIR_C_LENGTH_RESULTS 0x2a4
  305. #define BCM54XX_ECD_PAIR_D_LENGTH_RESULTS 0x2a5
  306. #define BCM54XX_RDB_ECD_PAIR_A_LENGTH_RESULTS 0x2a2
  307. #define BCM54XX_EXP_ECD_PAIR_A_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc2)
  308. #define BCM54XX_RDB_ECD_PAIR_B_LENGTH_RESULTS 0x2a3
  309. #define BCM54XX_EXP_ECD_PAIR_B_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc3)
  310. #define BCM54XX_RDB_ECD_PAIR_C_LENGTH_RESULTS 0x2a4
  311. #define BCM54XX_EXP_ECD_PAIR_C_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc4)
  312. #define BCM54XX_RDB_ECD_PAIR_D_LENGTH_RESULTS 0x2a5
  313. #define BCM54XX_EXP_ECD_PAIR_D_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc5)
  314. #define BCM54XX_ECD_LENGTH_RESULTS_INVALID 0xffff
  315. #endif /* _LINUX_BRCMPHY_H */