| 1234567891011121314151617181920212223242526272829303132333435363738394041 |
- /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
- #ifndef _DT_BINDINGS_RESET_TOSHIBA_TMPV770X_H_
- #define _DT_BINDINGS_RESET_TOSHIBA_TMPV770X_H_
- /* Reset */
- #define TMPV770X_RESET_PIETHER_2P5M 0
- #define TMPV770X_RESET_PIETHER_25M 1
- #define TMPV770X_RESET_PIETHER_50M 2
- #define TMPV770X_RESET_PIETHER_125M 3
- #define TMPV770X_RESET_HOX 4
- #define TMPV770X_RESET_PCIE_MSTR 5
- #define TMPV770X_RESET_PCIE_AUX 6
- #define TMPV770X_RESET_PIINTC 7
- #define TMPV770X_RESET_PIETHER_BUS 8
- #define TMPV770X_RESET_PISPI0 9
- #define TMPV770X_RESET_PISPI1 10
- #define TMPV770X_RESET_PISPI2 11
- #define TMPV770X_RESET_PISPI3 12
- #define TMPV770X_RESET_PISPI4 13
- #define TMPV770X_RESET_PISPI5 14
- #define TMPV770X_RESET_PISPI6 15
- #define TMPV770X_RESET_PIUART0 16
- #define TMPV770X_RESET_PIUART1 17
- #define TMPV770X_RESET_PIUART2 18
- #define TMPV770X_RESET_PIUART3 19
- #define TMPV770X_RESET_PII2C0 20
- #define TMPV770X_RESET_PII2C1 21
- #define TMPV770X_RESET_PII2C2 22
- #define TMPV770X_RESET_PII2C3 23
- #define TMPV770X_RESET_PII2C4 24
- #define TMPV770X_RESET_PII2C5 25
- #define TMPV770X_RESET_PII2C6 26
- #define TMPV770X_RESET_PII2C7 27
- #define TMPV770X_RESET_PII2C8 28
- #define TMPV770X_RESET_PIPCMIF 29
- #define TMPV770X_RESET_PICKMON 30
- #define TMPV770X_RESET_SBUSCLK 31
- #define TMPV770X_NR_RESET 32
- #endif /*_DT_BINDINGS_RESET_TOSHIBA_TMPV770X_H_ */
|
