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- /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
- /*
- * Copyright (C) 2020 Pengutronix, Sascha Hauer <[email protected]>
- */
- #ifndef __DT_BINDINGS_IMX8MP_POWER_DOMAIN_POWER_H__
- #define __DT_BINDINGS_IMX8MP_POWER_DOMAIN_POWER_H__
- #define IMX8MP_POWER_DOMAIN_MIPI_PHY1 0
- #define IMX8MP_POWER_DOMAIN_PCIE_PHY 1
- #define IMX8MP_POWER_DOMAIN_USB1_PHY 2
- #define IMX8MP_POWER_DOMAIN_USB2_PHY 3
- #define IMX8MP_POWER_DOMAIN_MLMIX 4
- #define IMX8MP_POWER_DOMAIN_AUDIOMIX 5
- #define IMX8MP_POWER_DOMAIN_GPU2D 6
- #define IMX8MP_POWER_DOMAIN_GPUMIX 7
- #define IMX8MP_POWER_DOMAIN_VPUMIX 8
- #define IMX8MP_POWER_DOMAIN_GPU3D 9
- #define IMX8MP_POWER_DOMAIN_MEDIAMIX 10
- #define IMX8MP_POWER_DOMAIN_VPU_G1 11
- #define IMX8MP_POWER_DOMAIN_VPU_G2 12
- #define IMX8MP_POWER_DOMAIN_VPU_VC8000E 13
- #define IMX8MP_POWER_DOMAIN_HDMIMIX 14
- #define IMX8MP_POWER_DOMAIN_HDMI_PHY 15
- #define IMX8MP_POWER_DOMAIN_MIPI_PHY2 16
- #define IMX8MP_POWER_DOMAIN_HSIOMIX 17
- #define IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP 18
- #define IMX8MP_HSIOBLK_PD_USB 0
- #define IMX8MP_HSIOBLK_PD_USB_PHY1 1
- #define IMX8MP_HSIOBLK_PD_USB_PHY2 2
- #define IMX8MP_HSIOBLK_PD_PCIE 3
- #define IMX8MP_HSIOBLK_PD_PCIE_PHY 4
- #define IMX8MP_MEDIABLK_PD_MIPI_DSI_1 0
- #define IMX8MP_MEDIABLK_PD_MIPI_CSI2_1 1
- #define IMX8MP_MEDIABLK_PD_LCDIF_1 2
- #define IMX8MP_MEDIABLK_PD_ISI 3
- #define IMX8MP_MEDIABLK_PD_MIPI_CSI2_2 4
- #define IMX8MP_MEDIABLK_PD_LCDIF_2 5
- #define IMX8MP_MEDIABLK_PD_ISP 6
- #define IMX8MP_MEDIABLK_PD_DWE 7
- #define IMX8MP_MEDIABLK_PD_MIPI_DSI_2 8
- #define IMX8MP_HDMIBLK_PD_IRQSTEER 0
- #define IMX8MP_HDMIBLK_PD_LCDIF 1
- #define IMX8MP_HDMIBLK_PD_PAI 2
- #define IMX8MP_HDMIBLK_PD_PVI 3
- #define IMX8MP_HDMIBLK_PD_TRNG 4
- #define IMX8MP_HDMIBLK_PD_HDMI_TX 5
- #define IMX8MP_HDMIBLK_PD_HDMI_TX_PHY 6
- #define IMX8MP_HDMIBLK_PD_HDCP 7
- #define IMX8MP_HDMIBLK_PD_HRV 8
- #define IMX8MP_VPUBLK_PD_G1 0
- #define IMX8MP_VPUBLK_PD_G2 1
- #define IMX8MP_VPUBLK_PD_VC8000E 2
- #endif
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