sppctl-sp7021.h 7.2 KB

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  1. /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
  2. /*
  3. * Sunplus SP7021 dt-bindings Pinctrl header file
  4. * Copyright (C) Sunplus Tech/Tibbo Tech.
  5. * Author: Dvorkin Dmitry <[email protected]>
  6. */
  7. #ifndef __DT_BINDINGS_PINCTRL_SPPCTL_SP7021_H__
  8. #define __DT_BINDINGS_PINCTRL_SPPCTL_SP7021_H__
  9. #include <dt-bindings/pinctrl/sppctl.h>
  10. /*
  11. * Please don't change the order of the following defines.
  12. * They are based on order of 'hardware' control register
  13. * defined in MOON2 ~ MOON3 registers.
  14. */
  15. #define MUXF_GPIO 0
  16. #define MUXF_IOP 1
  17. #define MUXF_L2SW_CLK_OUT 2
  18. #define MUXF_L2SW_MAC_SMI_MDC 3
  19. #define MUXF_L2SW_LED_FLASH0 4
  20. #define MUXF_L2SW_LED_FLASH1 5
  21. #define MUXF_L2SW_LED_ON0 6
  22. #define MUXF_L2SW_LED_ON1 7
  23. #define MUXF_L2SW_MAC_SMI_MDIO 8
  24. #define MUXF_L2SW_P0_MAC_RMII_TXEN 9
  25. #define MUXF_L2SW_P0_MAC_RMII_TXD0 10
  26. #define MUXF_L2SW_P0_MAC_RMII_TXD1 11
  27. #define MUXF_L2SW_P0_MAC_RMII_CRSDV 12
  28. #define MUXF_L2SW_P0_MAC_RMII_RXD0 13
  29. #define MUXF_L2SW_P0_MAC_RMII_RXD1 14
  30. #define MUXF_L2SW_P0_MAC_RMII_RXER 15
  31. #define MUXF_L2SW_P1_MAC_RMII_TXEN 16
  32. #define MUXF_L2SW_P1_MAC_RMII_TXD0 17
  33. #define MUXF_L2SW_P1_MAC_RMII_TXD1 18
  34. #define MUXF_L2SW_P1_MAC_RMII_CRSDV 19
  35. #define MUXF_L2SW_P1_MAC_RMII_RXD0 20
  36. #define MUXF_L2SW_P1_MAC_RMII_RXD1 21
  37. #define MUXF_L2SW_P1_MAC_RMII_RXER 22
  38. #define MUXF_DAISY_MODE 23
  39. #define MUXF_SDIO_CLK 24
  40. #define MUXF_SDIO_CMD 25
  41. #define MUXF_SDIO_D0 26
  42. #define MUXF_SDIO_D1 27
  43. #define MUXF_SDIO_D2 28
  44. #define MUXF_SDIO_D3 29
  45. #define MUXF_PWM0 30
  46. #define MUXF_PWM1 31
  47. #define MUXF_PWM2 32
  48. #define MUXF_PWM3 33
  49. #define MUXF_PWM4 34
  50. #define MUXF_PWM5 35
  51. #define MUXF_PWM6 36
  52. #define MUXF_PWM7 37
  53. #define MUXF_ICM0_D 38
  54. #define MUXF_ICM1_D 39
  55. #define MUXF_ICM2_D 40
  56. #define MUXF_ICM3_D 41
  57. #define MUXF_ICM0_CLK 42
  58. #define MUXF_ICM1_CLK 43
  59. #define MUXF_ICM2_CLK 44
  60. #define MUXF_ICM3_CLK 45
  61. #define MUXF_SPIM0_INT 46
  62. #define MUXF_SPIM0_CLK 47
  63. #define MUXF_SPIM0_EN 48
  64. #define MUXF_SPIM0_DO 49
  65. #define MUXF_SPIM0_DI 50
  66. #define MUXF_SPIM1_INT 51
  67. #define MUXF_SPIM1_CLK 52
  68. #define MUXF_SPIM1_EN 53
  69. #define MUXF_SPIM1_DO 54
  70. #define MUXF_SPIM1_DI 55
  71. #define MUXF_SPIM2_INT 56
  72. #define MUXF_SPIM2_CLK 57
  73. #define MUXF_SPIM2_EN 58
  74. #define MUXF_SPIM2_DO 59
  75. #define MUXF_SPIM2_DI 60
  76. #define MUXF_SPIM3_INT 61
  77. #define MUXF_SPIM3_CLK 62
  78. #define MUXF_SPIM3_EN 63
  79. #define MUXF_SPIM3_DO 64
  80. #define MUXF_SPIM3_DI 65
  81. #define MUXF_SPI0S_INT 66
  82. #define MUXF_SPI0S_CLK 67
  83. #define MUXF_SPI0S_EN 68
  84. #define MUXF_SPI0S_DO 69
  85. #define MUXF_SPI0S_DI 70
  86. #define MUXF_SPI1S_INT 71
  87. #define MUXF_SPI1S_CLK 72
  88. #define MUXF_SPI1S_EN 73
  89. #define MUXF_SPI1S_DO 74
  90. #define MUXF_SPI1S_DI 75
  91. #define MUXF_SPI2S_INT 76
  92. #define MUXF_SPI2S_CLK 77
  93. #define MUXF_SPI2S_EN 78
  94. #define MUXF_SPI2S_DO 79
  95. #define MUXF_SPI2S_DI 80
  96. #define MUXF_SPI3S_INT 81
  97. #define MUXF_SPI3S_CLK 82
  98. #define MUXF_SPI3S_EN 83
  99. #define MUXF_SPI3S_DO 84
  100. #define MUXF_SPI3S_DI 85
  101. #define MUXF_I2CM0_CLK 86
  102. #define MUXF_I2CM0_DAT 87
  103. #define MUXF_I2CM1_CLK 88
  104. #define MUXF_I2CM1_DAT 89
  105. #define MUXF_I2CM2_CLK 90
  106. #define MUXF_I2CM2_DAT 91
  107. #define MUXF_I2CM3_CLK 92
  108. #define MUXF_I2CM3_DAT 93
  109. #define MUXF_UA1_TX 94
  110. #define MUXF_UA1_RX 95
  111. #define MUXF_UA1_CTS 96
  112. #define MUXF_UA1_RTS 97
  113. #define MUXF_UA2_TX 98
  114. #define MUXF_UA2_RX 99
  115. #define MUXF_UA2_CTS 100
  116. #define MUXF_UA2_RTS 101
  117. #define MUXF_UA3_TX 102
  118. #define MUXF_UA3_RX 103
  119. #define MUXF_UA3_CTS 104
  120. #define MUXF_UA3_RTS 105
  121. #define MUXF_UA4_TX 106
  122. #define MUXF_UA4_RX 107
  123. #define MUXF_UA4_CTS 108
  124. #define MUXF_UA4_RTS 109
  125. #define MUXF_TIMER0_INT 110
  126. #define MUXF_TIMER1_INT 111
  127. #define MUXF_TIMER2_INT 112
  128. #define MUXF_TIMER3_INT 113
  129. #define MUXF_GPIO_INT0 114
  130. #define MUXF_GPIO_INT1 115
  131. #define MUXF_GPIO_INT2 116
  132. #define MUXF_GPIO_INT3 117
  133. #define MUXF_GPIO_INT4 118
  134. #define MUXF_GPIO_INT5 119
  135. #define MUXF_GPIO_INT6 120
  136. #define MUXF_GPIO_INT7 121
  137. /*
  138. * Please don't change the order of the following defines.
  139. * They are based on order of items in array 'sppctl_list_funcs'
  140. * in Sunplus pinctrl driver.
  141. */
  142. #define GROP_SPI_FLASH 122
  143. #define GROP_SPI_FLASH_4BIT 123
  144. #define GROP_SPI_NAND 124
  145. #define GROP_CARD0_EMMC 125
  146. #define GROP_SD_CARD 126
  147. #define GROP_UA0 127
  148. #define GROP_ACHIP_DEBUG 128
  149. #define GROP_ACHIP_UA2AXI 129
  150. #define GROP_FPGA_IFX 130
  151. #define GROP_HDMI_TX 131
  152. #define GROP_AUD_EXT_ADC_IFX0 132
  153. #define GROP_AUD_EXT_DAC_IFX0 133
  154. #define GROP_SPDIF_RX 134
  155. #define GROP_SPDIF_TX 135
  156. #define GROP_TDMTX_IFX0 136
  157. #define GROP_TDMRX_IFX0 137
  158. #define GROP_PDMRX_IFX0 138
  159. #define GROP_PCM_IEC_TX 139
  160. #define GROP_LCDIF 140
  161. #define GROP_DVD_DSP_DEBUG 141
  162. #define GROP_I2C_DEBUG 142
  163. #define GROP_I2C_SLAVE 143
  164. #define GROP_WAKEUP 144
  165. #define GROP_UART2AXI 145
  166. #define GROP_USB0_I2C 146
  167. #define GROP_USB1_I2C 147
  168. #define GROP_USB0_OTG 148
  169. #define GROP_USB1_OTG 149
  170. #define GROP_UPHY0_DEBUG 150
  171. #define GROP_UPHY1_DEBUG 151
  172. #define GROP_UPHY0_EXT 152
  173. #define GROP_PROBE_PORT 153
  174. #endif