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android_kernel_...
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include
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dt-bindings
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memory
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tegra234-mc.h

tegra234-mc.h 4.6 KB
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  1. /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
    2. 

  2. /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
    3. 

  3. 

  4. #ifndef DT_BINDINGS_MEMORY_TEGRA234_MC_H
    5. 

  5. #define DT_BINDINGS_MEMORY_TEGRA234_MC_H
    6. 

  6. 

  7. /* special clients */
    8. 

  8. #define TEGRA234_SID_INVALID		0x00
    9. 

  9. #define TEGRA234_SID_PASSTHROUGH	0x7f
    10. 

  10. 

  11. /* NISO0 stream IDs */
    12. 

  12. #define TEGRA234_SID_APE	0x02
    13. 

  13. #define TEGRA234_SID_HDA	0x03
    14. 

  14. #define TEGRA234_SID_GPCDMA	0x04
    15. 

  15. #define TEGRA234_SID_MGBE	0x06
    16. 

  16. #define TEGRA234_SID_PCIE0	0x12
    17. 

  17. #define TEGRA234_SID_PCIE4	0x13
    18. 

  18. #define TEGRA234_SID_PCIE5	0x14
    19. 

  19. #define TEGRA234_SID_PCIE6	0x15
    20. 

  20. #define TEGRA234_SID_PCIE9	0x1f
    21. 

  21. #define TEGRA234_SID_MGBE_VF1	0x49
    22. 

  22. #define TEGRA234_SID_MGBE_VF2	0x4a
    23. 

  23. #define TEGRA234_SID_MGBE_VF3	0x4b
    24. 

  24. 

  25. /* NISO1 stream IDs */
    26. 

  26. #define TEGRA234_SID_SDMMC4	0x02
    27. 

  27. #define TEGRA234_SID_PCIE1	0x05
    28. 

  28. #define TEGRA234_SID_PCIE2	0x06
    29. 

  29. #define TEGRA234_SID_PCIE3	0x07
    30. 

  30. #define TEGRA234_SID_PCIE7	0x08
    31. 

  31. #define TEGRA234_SID_PCIE8	0x09
    32. 

  32. #define TEGRA234_SID_PCIE10	0x0b
    33. 

  33. #define TEGRA234_SID_BPMP	0x10
    34. 

  34. #define TEGRA234_SID_HOST1X	0x27
    35. 

  35. #define TEGRA234_SID_VIC	0x34
    36. 

  36. 

  37. /* Shared stream IDs */
    38. 

  38. #define TEGRA234_SID_HOST1X_CTX0	0x35
    39. 

  39. #define TEGRA234_SID_HOST1X_CTX1	0x36
    40. 

  40. #define TEGRA234_SID_HOST1X_CTX2	0x37
    41. 

  41. #define TEGRA234_SID_HOST1X_CTX3	0x38
    42. 

  42. #define TEGRA234_SID_HOST1X_CTX4	0x39
    43. 

  43. #define TEGRA234_SID_HOST1X_CTX5	0x3a
    44. 

  44. #define TEGRA234_SID_HOST1X_CTX6	0x3b
    45. 

  45. #define TEGRA234_SID_HOST1X_CTX7	0x3c
    46. 

  46. 

  47. /*
    48. 

  48.  * memory client IDs
    49. 

  49.  */
    50. 

  50. 

  51. /* High-definition audio (HDA) read clients */
    52. 

  52. #define TEGRA234_MEMORY_CLIENT_HDAR 0x15
    53. 

  53. #define TEGRA234_MEMORY_CLIENT_HOST1XDMAR 0x16
    54. 

  54. /* PCIE6 read clients */
    55. 

  55. #define TEGRA234_MEMORY_CLIENT_PCIE6AR 0x28
    56. 

  56. /* PCIE6 write clients */
    57. 

  57. #define TEGRA234_MEMORY_CLIENT_PCIE6AW 0x29
    58. 

  58. /* PCIE7 read clients */
    59. 

  59. #define TEGRA234_MEMORY_CLIENT_PCIE7AR 0x2a
    60. 

  60. /* PCIE7 write clients */
    61. 

  61. #define TEGRA234_MEMORY_CLIENT_PCIE7AW 0x30
    62. 

  62. /* PCIE8 read clients */
    63. 

  63. #define TEGRA234_MEMORY_CLIENT_PCIE8AR 0x32
    64. 

  64. /* High-definition audio (HDA) write clients */
    65. 

  65. #define TEGRA234_MEMORY_CLIENT_HDAW 0x35
    66. 

  66. /* PCIE8 write clients */
    67. 

  67. #define TEGRA234_MEMORY_CLIENT_PCIE8AW 0x3b
    68. 

  68. /* PCIE9 read clients */
    69. 

  69. #define TEGRA234_MEMORY_CLIENT_PCIE9AR 0x3c
    70. 

  70. /* PCIE6r1 read clients */
    71. 

  71. #define TEGRA234_MEMORY_CLIENT_PCIE6AR1 0x3d
    72. 

  72. /* PCIE9 write clients */
    73. 

  73. #define TEGRA234_MEMORY_CLIENT_PCIE9AW 0x3e
    74. 

  74. /* PCIE10 read clients */
    75. 

  75. #define TEGRA234_MEMORY_CLIENT_PCIE10AR 0x3f
    76. 

  76. /* PCIE10 write clients */
    77. 

  77. #define TEGRA234_MEMORY_CLIENT_PCIE10AW 0x40
    78. 

  78. /* PCIE10r1 read clients */
    79. 

  79. #define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48
    80. 

  80. /* PCIE7r1 read clients */
    81. 

  81. #define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49
    82. 

  82. /* MGBE0 read client */
    83. 

  83. #define TEGRA234_MEMORY_CLIENT_MGBEARD 0x58
    84. 

  84. /* MGBEB read client */
    85. 

  85. #define TEGRA234_MEMORY_CLIENT_MGBEBRD 0x59
    86. 

  86. /* MGBEC read client */
    87. 

  87. #define TEGRA234_MEMORY_CLIENT_MGBECRD 0x5a
    88. 

  88. /* MGBED read client */
    89. 

  89. #define TEGRA234_MEMORY_CLIENT_MGBEDRD 0x5b
    90. 

  90. /* MGBE0 write client */
    91. 

  91. #define TEGRA234_MEMORY_CLIENT_MGBEAWR 0x5c
    92. 

  92. /* MGBEB write client */
    93. 

  93. #define TEGRA234_MEMORY_CLIENT_MGBEBWR 0x5f
    94. 

  94. /* MGBEC write client */
    95. 

  95. #define TEGRA234_MEMORY_CLIENT_MGBECWR 0x61
    96. 

  96. /* sdmmcd memory read client */
    97. 

  97. #define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63
    98. 

  98. /* MGBED write client */
    99. 

  99. #define TEGRA234_MEMORY_CLIENT_MGBEDWR 0x65
    100. 

  100. /* sdmmcd memory write client */
    101. 

  101. #define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67
    102. 

  102. #define TEGRA234_MEMORY_CLIENT_VICSRD 0x6c
    103. 

  103. #define TEGRA234_MEMORY_CLIENT_VICSWR 0x6d
    104. 

  104. /* BPMP read client */
    105. 

  105. #define TEGRA234_MEMORY_CLIENT_BPMPR 0x93
    106. 

  106. /* BPMP write client */
    107. 

  107. #define TEGRA234_MEMORY_CLIENT_BPMPW 0x94
    108. 

  108. /* BPMPDMA read client */
    109. 

  109. #define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95
    110. 

  110. /* BPMPDMA write client */
    111. 

  111. #define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96
    112. 

  112. /* APEDMA read client */
    113. 

  113. #define TEGRA234_MEMORY_CLIENT_APEDMAR 0x9f
    114. 

  114. /* APEDMA write client */
    115. 

  115. #define TEGRA234_MEMORY_CLIENT_APEDMAW 0xa0
    116. 

  116. /* PCIE0 read clients */
    117. 

  117. #define TEGRA234_MEMORY_CLIENT_PCIE0R 0xd8
    118. 

  118. /* PCIE0 write clients */
    119. 

  119. #define TEGRA234_MEMORY_CLIENT_PCIE0W 0xd9
    120. 

  120. /* PCIE1 read clients */
    121. 

  121. #define TEGRA234_MEMORY_CLIENT_PCIE1R 0xda
    122. 

  122. /* PCIE1 write clients */
    123. 

  123. #define TEGRA234_MEMORY_CLIENT_PCIE1W 0xdb
    124. 

  124. /* PCIE2 read clients */
    125. 

  125. #define TEGRA234_MEMORY_CLIENT_PCIE2AR 0xdc
    126. 

  126. /* PCIE2 write clients */
    127. 

  127. #define TEGRA234_MEMORY_CLIENT_PCIE2AW 0xdd
    128. 

  128. /* PCIE3 read clients */
    129. 

  129. #define TEGRA234_MEMORY_CLIENT_PCIE3R 0xde
    130. 

  130. /* PCIE3 write clients */
    131. 

  131. #define TEGRA234_MEMORY_CLIENT_PCIE3W 0xdf
    132. 

  132. /* PCIE4 read clients */
    133. 

  133. #define TEGRA234_MEMORY_CLIENT_PCIE4R 0xe0
    134. 

  134. /* PCIE4 write clients */
    135. 

  135. #define TEGRA234_MEMORY_CLIENT_PCIE4W 0xe1
    136. 

  136. /* PCIE5 read clients */
    137. 

  137. #define TEGRA234_MEMORY_CLIENT_PCIE5R 0xe2
    138. 

  138. /* PCIE5 write clients */
    139. 

  139. #define TEGRA234_MEMORY_CLIENT_PCIE5W 0xe3
    140. 

  140. /* PCIE5r1 read clients */
    141. 

  141. #define TEGRA234_MEMORY_CLIENT_PCIE5R1 0xef
    142. 

  142. 

  143. #endif
    144.