qcom,anorak.h 4.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
  4. */
  5. #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_ANORAK_H
  6. #define __DT_BINDINGS_INTERCONNECT_QCOM_ANORAK_H
  7. #define MASTER_GPU_TCU 0
  8. #define MASTER_SYS_TCU 1
  9. #define MASTER_APPSS_PROC 2
  10. #define MASTER_LLCC 3
  11. #define MASTER_CNOC_LPASS_AG_NOC 4
  12. #define MASTER_GIC_AHB 5
  13. #define MASTER_CDSP_NOC_CFG 6
  14. #define MASTER_QDSS_BAM 7
  15. #define MASTER_QUP_0 8
  16. #define MASTER_QUP_1 9
  17. #define MASTER_A1NOC_CFG 10
  18. #define MASTER_A2NOC_CFG 11
  19. #define MASTER_A1NOC_SNOC 12
  20. #define MASTER_A2NOC_SNOC 13
  21. #define MASTER_CAMNOC_HF 14
  22. #define MASTER_CAMNOC_ICP 15
  23. #define MASTER_CAMNOC_SF 16
  24. #define MASTER_CNOC_A2NOC 17
  25. #define MASTER_GEM_NOC_CNOC 18
  26. #define MASTER_GFX3D 19
  27. #define MASTER_LPASS_ANOC 20
  28. #define MASTER_MDP0 21
  29. #define MASTER_MDP1 22
  30. #define MASTER_CNOC_MNOC_CFG 23
  31. #define MASTER_MNOC_HF_MEM_NOC 24
  32. #define MASTER_MNOC_SF_MEM_NOC 25
  33. #define MASTER_COMPUTE_NOC 26
  34. #define MASTER_ANOC_PCIE_GEM_NOC 27
  35. #define MASTER_PCIE_ANOC_CFG 28
  36. #define MASTER_SNOC_CFG 29
  37. #define MASTER_SNOC_GC_MEM_NOC 30
  38. #define MASTER_SNOC_SF_MEM_NOC 31
  39. #define MASTER_CDSP_HCP 32
  40. #define MASTER_VIDEO 33
  41. #define MASTER_VIDEO_CV_PROC 34
  42. #define MASTER_VIDEO_PROC 35
  43. #define MASTER_VIDEO_V_PROC 36
  44. #define MASTER_QUP_CORE_0 37
  45. #define MASTER_QUP_CORE_1 38
  46. #define MASTER_CRYPTO 39
  47. #define MASTER_IPA 40
  48. #define MASTER_LPASS_PROC 41
  49. #define MASTER_CDSP_PROC 42
  50. #define MASTER_SP 43
  51. #define MASTER_GIC 44
  52. #define MASTER_PCIE_0 45
  53. #define MASTER_PCIE_1 46
  54. #define MASTER_PCIE_4 47
  55. #define MASTER_QDSS_DAP 48
  56. #define MASTER_QDSS_ETR 49
  57. #define MASTER_QDSS_ETR_1 50
  58. #define MASTER_SDCC_2 51
  59. #define MASTER_UFS_MEM 52
  60. #define MASTER_USB3_0 53
  61. #define MASTER_DDR_RT 54
  62. #define SLAVE_EBI1 512
  63. #define SLAVE_AHB2PHY_SOUTH 513
  64. #define SLAVE_AHB2PHY_NORTH 514
  65. #define SLAVE_AOSS 515
  66. #define SLAVE_CAMERA_CFG 516
  67. #define SLAVE_CLK_CTL 517
  68. #define SLAVE_CDSP_CFG 518
  69. #define SLAVE_RBCPR_CX_CFG 519
  70. #define SLAVE_RBCPR_MMCX_CFG 520
  71. #define SLAVE_RBCPR_MXA_CFG 521
  72. #define SLAVE_RBCPR_MXC_CFG 522
  73. #define SLAVE_CRYPTO_0_CFG 523
  74. #define SLAVE_CX_RDPM 524
  75. #define SLAVE_DISPLAY_CFG 525
  76. #define SLAVE_DISPLAY1_CFG 526
  77. #define SLAVE_GFX3D_CFG 527
  78. #define SLAVE_IMEM_CFG 528
  79. #define SLAVE_IPA_CFG 529
  80. #define SLAVE_IPC_ROUTER_CFG 530
  81. #define SLAVE_LPASS 531
  82. #define SLAVE_LPASS_CORE_CFG 532
  83. #define SLAVE_LPASS_LPI_CFG 533
  84. #define SLAVE_LPASS_MPU_CFG 534
  85. #define SLAVE_LPASS_TOP_CFG 535
  86. #define SLAVE_MX_RDPM 536
  87. #define SLAVE_PDM 537
  88. #define SLAVE_PRNG 538
  89. #define SLAVE_QDSS_CFG 539
  90. #define SLAVE_QUP_0 540
  91. #define SLAVE_QUP_1 541
  92. #define SLAVE_SDCC_2 542
  93. #define SLAVE_SPSS_CFG 543
  94. #define SLAVE_TCSR 544
  95. #define SLAVE_TLMM 545
  96. #define SLAVE_TME_CFG 546
  97. #define SLAVE_UFS_MEM_CFG 547
  98. #define SLAVE_USB3_0 548
  99. #define SLAVE_VENUS_CFG 549
  100. #define SLAVE_VSENSE_CTRL_CFG 550
  101. #define SLAVE_A1NOC_CFG 551
  102. #define SLAVE_A1NOC_SNOC 552
  103. #define SLAVE_A2NOC_CFG 553
  104. #define SLAVE_A2NOC_SNOC 554
  105. #define SLAVE_CNOC_A2NOC 555
  106. #define SLAVE_DDRSS_CFG 556
  107. #define SLAVE_GEM_NOC_CNOC 557
  108. #define SLAVE_SNOC_GEM_NOC_GC 558
  109. #define SLAVE_SNOC_GEM_NOC_SF 559
  110. #define SLAVE_LLCC 560
  111. #define SLAVE_MNOC_HF_MEM_NOC 561
  112. #define SLAVE_MNOC_SF_MEM_NOC 562
  113. #define SLAVE_CNOC_MNOC_CFG 563
  114. #define SLAVE_CDSP_MEM_NOC 564
  115. #define SLAVE_PCIE_ANOC_CFG 565
  116. #define SLAVE_ANOC_PCIE_GEM_NOC 566
  117. #define SLAVE_SNOC_CFG 567
  118. #define SLAVE_LPASS_SNOC 568
  119. #define SLAVE_QUP_CORE_0 569
  120. #define SLAVE_QUP_CORE_1 570
  121. #define SLAVE_IMEM 571
  122. #define SLAVE_SERVICE_NSP_NOC 572
  123. #define SLAVE_SERVICE_A1NOC 573
  124. #define SLAVE_SERVICE_A2NOC 574
  125. #define SLAVE_SERVICE_CNOC 575
  126. #define SLAVE_SERVICE_MNOC 576
  127. #define SLAVE_SERVICES_LPASS_AML_NOC 577
  128. #define SLAVE_SERVICE_LPASS_AG_NOC 578
  129. #define SLAVE_SERVICE_PCIE_ANOC 579
  130. #define SLAVE_SERVICE_SNOC 580
  131. #define SLAVE_QDSS_STM 581
  132. #define SLAVE_TCU 582
  133. #define SLAVE_DDR_RT 583
  134. #define MASTER_LLCC_DISP 1000
  135. #define MASTER_MDP0_DISP 1001
  136. #define MASTER_MNOC_HF_MEM_NOC_DISP 1002
  137. #define MASTER_ANOC_PCIE_GEM_NOC_DISP 1003
  138. #define SLAVE_EBI1_DISP 1512
  139. #define SLAVE_LLCC_DISP 1513
  140. #define SLAVE_MNOC_HF_MEM_NOC_DISP 1514
  141. #define MASTER_LLCC_DISP2 2000
  142. #define MASTER_MDP1_DISP2 2001
  143. #define MASTER_MNOC_HF_MEM_NOC_DISP2 2002
  144. #define MASTER_ANOC_PCIE_GEM_NOC_DISP2 2003
  145. #define SLAVE_EBI1_DISP2 2512
  146. #define SLAVE_LLCC_DISP2 2513
  147. #define SLAVE_MNOC_HF_MEM_NOC_DISP2 2514
  148. #endif