sh73a0-clock.h 1.8 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182
  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Copyright 2014 Ulrich Hecht
  4. */
  5. #ifndef __DT_BINDINGS_CLOCK_SH73A0_H__
  6. #define __DT_BINDINGS_CLOCK_SH73A0_H__
  7. /* CPG */
  8. #define SH73A0_CLK_MAIN 0
  9. #define SH73A0_CLK_PLL0 1
  10. #define SH73A0_CLK_PLL1 2
  11. #define SH73A0_CLK_PLL2 3
  12. #define SH73A0_CLK_PLL3 4
  13. #define SH73A0_CLK_DSI0PHY 5
  14. #define SH73A0_CLK_DSI1PHY 6
  15. #define SH73A0_CLK_ZG 7
  16. #define SH73A0_CLK_M3 8
  17. #define SH73A0_CLK_B 9
  18. #define SH73A0_CLK_M1 10
  19. #define SH73A0_CLK_M2 11
  20. #define SH73A0_CLK_Z 12
  21. #define SH73A0_CLK_ZX 13
  22. #define SH73A0_CLK_HP 14
  23. /* MSTP0 */
  24. #define SH73A0_CLK_IIC2 1
  25. #define SH73A0_CLK_MSIOF0 0
  26. /* MSTP1 */
  27. #define SH73A0_CLK_CEU1 29
  28. #define SH73A0_CLK_CSI2_RX1 28
  29. #define SH73A0_CLK_CEU0 27
  30. #define SH73A0_CLK_CSI2_RX0 26
  31. #define SH73A0_CLK_TMU0 25
  32. #define SH73A0_CLK_DSITX0 18
  33. #define SH73A0_CLK_IIC0 16
  34. #define SH73A0_CLK_SGX 12
  35. #define SH73A0_CLK_LCDC0 0
  36. /* MSTP2 */
  37. #define SH73A0_CLK_SCIFA7 19
  38. #define SH73A0_CLK_SY_DMAC 18
  39. #define SH73A0_CLK_MP_DMAC 17
  40. #define SH73A0_CLK_MSIOF3 15
  41. #define SH73A0_CLK_MSIOF1 8
  42. #define SH73A0_CLK_SCIFA5 7
  43. #define SH73A0_CLK_SCIFB 6
  44. #define SH73A0_CLK_MSIOF2 5
  45. #define SH73A0_CLK_SCIFA0 4
  46. #define SH73A0_CLK_SCIFA1 3
  47. #define SH73A0_CLK_SCIFA2 2
  48. #define SH73A0_CLK_SCIFA3 1
  49. #define SH73A0_CLK_SCIFA4 0
  50. /* MSTP3 */
  51. #define SH73A0_CLK_SCIFA6 31
  52. #define SH73A0_CLK_CMT1 29
  53. #define SH73A0_CLK_FSI 28
  54. #define SH73A0_CLK_IRDA 25
  55. #define SH73A0_CLK_IIC1 23
  56. #define SH73A0_CLK_USB 22
  57. #define SH73A0_CLK_FLCTL 15
  58. #define SH73A0_CLK_SDHI0 14
  59. #define SH73A0_CLK_SDHI1 13
  60. #define SH73A0_CLK_MMCIF0 12
  61. #define SH73A0_CLK_SDHI2 11
  62. #define SH73A0_CLK_TPU0 4
  63. #define SH73A0_CLK_TPU1 3
  64. #define SH73A0_CLK_TPU2 2
  65. #define SH73A0_CLK_TPU3 1
  66. #define SH73A0_CLK_TPU4 0
  67. /* MSTP4 */
  68. #define SH73A0_CLK_IIC3 11
  69. #define SH73A0_CLK_IIC4 10
  70. #define SH73A0_CLK_KEYSC 3
  71. /* MSTP5 */
  72. #define SH73A0_CLK_INTCA0 8
  73. #endif