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r7s72100-clock.h

r7s72100-clock.h 2.6 KB
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  1. /* SPDX-License-Identifier: GPL-2.0
    2. 

  2.  *
    3. 

  3.  * Copyright (C) 2014 Renesas Solutions Corp.
    4. 

  4.  * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef __DT_BINDINGS_CLOCK_R7S72100_H__
    8. 

  8. #define __DT_BINDINGS_CLOCK_R7S72100_H__
    9. 

  9. 

  10. #define R7S72100_CLK_PLL	0
    11. 

  11. #define R7S72100_CLK_I		1
    12. 

  12. #define R7S72100_CLK_G		2
    13. 

  13. 

  14. /* MSTP2 */
    15. 

  15. #define R7S72100_CLK_CORESIGHT	0
    16. 

  16. 

  17. /* MSTP3 */
    18. 

  18. #define R7S72100_CLK_IEBUS	7
    19. 

  19. #define R7S72100_CLK_IRDA	6
    20. 

  20. #define R7S72100_CLK_LIN0	5
    21. 

  21. #define R7S72100_CLK_LIN1	4
    22. 

  22. #define R7S72100_CLK_MTU2	3
    23. 

  23. #define R7S72100_CLK_CAN	2
    24. 

  24. #define R7S72100_CLK_ADCPWR	1
    25. 

  25. #define R7S72100_CLK_PWM	0
    26. 

  26. 

  27. /* MSTP4 */
    28. 

  28. #define R7S72100_CLK_SCIF0	7
    29. 

  29. #define R7S72100_CLK_SCIF1	6
    30. 

  30. #define R7S72100_CLK_SCIF2	5
    31. 

  31. #define R7S72100_CLK_SCIF3	4
    32. 

  32. #define R7S72100_CLK_SCIF4	3
    33. 

  33. #define R7S72100_CLK_SCIF5	2
    34. 

  34. #define R7S72100_CLK_SCIF6	1
    35. 

  35. #define R7S72100_CLK_SCIF7	0
    36. 

  36. 

  37. /* MSTP5 */
    38. 

  38. #define R7S72100_CLK_SCI0	7
    39. 

  39. #define R7S72100_CLK_SCI1	6
    40. 

  40. #define R7S72100_CLK_SG0	5
    41. 

  41. #define R7S72100_CLK_SG1	4
    42. 

  42. #define R7S72100_CLK_SG2	3
    43. 

  43. #define R7S72100_CLK_SG3	2
    44. 

  44. #define R7S72100_CLK_OSTM0	1
    45. 

  45. #define R7S72100_CLK_OSTM1	0
    46. 

  46. 

  47. /* MSTP6 */
    48. 

  48. #define R7S72100_CLK_ADC	7
    49. 

  49. #define R7S72100_CLK_CEU	6
    50. 

  50. #define R7S72100_CLK_DOC0	5
    51. 

  51. #define R7S72100_CLK_DOC1	4
    52. 

  52. #define R7S72100_CLK_DRC0	3
    53. 

  53. #define R7S72100_CLK_DRC1	2
    54. 

  54. #define R7S72100_CLK_JCU	1
    55. 

  55. #define R7S72100_CLK_RTC	0
    56. 

  56. 

  57. /* MSTP7 */
    58. 

  58. #define R7S72100_CLK_VDEC0	7
    59. 

  59. #define R7S72100_CLK_VDEC1	6
    60. 

  60. #define R7S72100_CLK_ETHER	4
    61. 

  61. #define R7S72100_CLK_NAND	3
    62. 

  62. #define R7S72100_CLK_USB0	1
    63. 

  63. #define R7S72100_CLK_USB1	0
    64. 

  64. 

  65. /* MSTP8 */
    66. 

  66. #define R7S72100_CLK_IMR0	7
    67. 

  67. #define R7S72100_CLK_IMR1	6
    68. 

  68. #define R7S72100_CLK_IMRDISP	5
    69. 

  69. #define R7S72100_CLK_MMCIF	4
    70. 

  70. #define R7S72100_CLK_MLB	3
    71. 

  71. #define R7S72100_CLK_ETHAVB	2
    72. 

  72. #define R7S72100_CLK_SCUX	1
    73. 

  73. 

  74. /* MSTP9 */
    75. 

  75. #define R7S72100_CLK_I2C0	7
    76. 

  76. #define R7S72100_CLK_I2C1	6
    77. 

  77. #define R7S72100_CLK_I2C2	5
    78. 

  78. #define R7S72100_CLK_I2C3	4
    79. 

  79. #define R7S72100_CLK_SPIBSC0	3
    80. 

  80. #define R7S72100_CLK_SPIBSC1	2
    81. 

  81. #define R7S72100_CLK_VDC50	1	/* and LVDS */
    82. 

  82. #define R7S72100_CLK_VDC51	0
    83. 

  83. 

  84. /* MSTP10 */
    85. 

  85. #define R7S72100_CLK_SPI0	7
    86. 

  86. #define R7S72100_CLK_SPI1	6
    87. 

  87. #define R7S72100_CLK_SPI2	5
    88. 

  88. #define R7S72100_CLK_SPI3	4
    89. 

  89. #define R7S72100_CLK_SPI4	3
    90. 

  90. #define R7S72100_CLK_CDROM	2
    91. 

  91. #define R7S72100_CLK_SPDIF	1
    92. 

  92. #define R7S72100_CLK_RGPVG2	0
    93. 

  93. 

  94. /* MSTP11 */
    95. 

  95. #define R7S72100_CLK_SSI0	5
    96. 

  96. #define R7S72100_CLK_SSI1	4
    97. 

  97. #define R7S72100_CLK_SSI2	3
    98. 

  98. #define R7S72100_CLK_SSI3	2
    99. 

  99. #define R7S72100_CLK_SSI4	1
    100. 

  100. #define R7S72100_CLK_SSI5	0
    101. 

  101. 

  102. /* MSTP12 */
    103. 

  103. #define R7S72100_CLK_SDHI00	3
    104. 

  104. #define R7S72100_CLK_SDHI01	2
    105. 

  105. #define R7S72100_CLK_SDHI10	1
    106. 

  106. #define R7S72100_CLK_SDHI11	0
    107. 

  107. 

  108. /* MSTP13 */
    109. 

  109. #define R7S72100_CLK_PIX1	2
    110. 

  110. #define R7S72100_CLK_PIX0	1
    111. 

  111. 

  112. #endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */
    113.