| 1234567891011121314151617181920212223242526272829303132333435363738394041424344454647 |
- /* SPDX-License-Identifier: GPL-2.0 */
- /* Copyright (c) 2018, 2020 The Linux Foundation. All rights reserved. */
- /* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. */
- #ifndef _DT_BINDINGS_CLK_MSM_RPMH_H
- #define _DT_BINDINGS_CLK_MSM_RPMH_H
- /* RPMh controlled clocks */
- #define RPMH_CXO_CLK 0
- #define RPMH_CXO_CLK_A 1
- #define RPMH_LN_BB_CLK2 2
- #define RPMH_LN_BB_CLK2_A 3
- #define RPMH_LN_BB_CLK3 4
- #define RPMH_LN_BB_CLK3_A 5
- #define RPMH_RF_CLK1 6
- #define RPMH_RF_CLK1_A 7
- #define RPMH_RF_CLK2 8
- #define RPMH_RF_CLK2_A 9
- #define RPMH_RF_CLK3 10
- #define RPMH_RF_CLK3_A 11
- #define RPMH_IPA_CLK 12
- #define RPMH_LN_BB_CLK1 13
- #define RPMH_LN_BB_CLK1_A 14
- #define RPMH_CE_CLK 15
- #define RPMH_QPIC_CLK 16
- #define RPMH_DIV_CLK1 17
- #define RPMH_DIV_CLK1_A 18
- #define RPMH_RF_CLK4 19
- #define RPMH_RF_CLK4_A 20
- #define RPMH_RF_CLK5 21
- #define RPMH_RF_CLK5_A 22
- #define RPMH_PKA_CLK 23
- #define RPMH_HWKM_CLK 24
- #define RPMH_QLINK_CLK 25
- #define RPMH_QLINK_CLK_A 26
- #define RPMH_CXO_PAD_CLK 27
- #define RPMH_CXO_PAD_CLK_A 28
- #define RPMH_LN_BB_CLK4 29
- #define RPMH_LN_BB_CLK4_A 30
- #define RPMH_LN_BB_CLK7 31
- #define RPMH_LN_BB_CLK7_A 32
- #define RPMH_LN_BB_CLK8 33
- #define RPMH_LN_BB_CLK8_A 34
- #define RPMH_LN_BB_CLK9 35
- #define RPMH_LN_BB_CLK9_A 36
- #endif
|
