sp805_wdt.c 8.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * drivers/char/watchdog/sp805-wdt.c
  4. *
  5. * Watchdog driver for ARM SP805 watchdog module
  6. *
  7. * Copyright (C) 2010 ST Microelectronics
  8. * Viresh Kumar <[email protected]>
  9. *
  10. * This file is licensed under the terms of the GNU General Public
  11. * License version 2 or later. This program is licensed "as is" without any
  12. * warranty of any kind, whether express or implied.
  13. */
  14. #include <linux/device.h>
  15. #include <linux/resource.h>
  16. #include <linux/amba/bus.h>
  17. #include <linux/bitops.h>
  18. #include <linux/clk.h>
  19. #include <linux/io.h>
  20. #include <linux/ioport.h>
  21. #include <linux/kernel.h>
  22. #include <linux/math64.h>
  23. #include <linux/module.h>
  24. #include <linux/moduleparam.h>
  25. #include <linux/pm.h>
  26. #include <linux/property.h>
  27. #include <linux/slab.h>
  28. #include <linux/spinlock.h>
  29. #include <linux/types.h>
  30. #include <linux/watchdog.h>
  31. /* default timeout in seconds */
  32. #define DEFAULT_TIMEOUT 60
  33. #define MODULE_NAME "sp805-wdt"
  34. /* watchdog register offsets and masks */
  35. #define WDTLOAD 0x000
  36. #define LOAD_MIN 0x00000001
  37. #define LOAD_MAX 0xFFFFFFFF
  38. #define WDTVALUE 0x004
  39. #define WDTCONTROL 0x008
  40. /* control register masks */
  41. #define INT_ENABLE (1 << 0)
  42. #define RESET_ENABLE (1 << 1)
  43. #define ENABLE_MASK (INT_ENABLE | RESET_ENABLE)
  44. #define WDTINTCLR 0x00C
  45. #define WDTRIS 0x010
  46. #define WDTMIS 0x014
  47. #define INT_MASK (1 << 0)
  48. #define WDTLOCK 0xC00
  49. #define UNLOCK 0x1ACCE551
  50. #define LOCK 0x00000001
  51. /**
  52. * struct sp805_wdt: sp805 wdt device structure
  53. * @wdd: instance of struct watchdog_device
  54. * @lock: spin lock protecting dev structure and io access
  55. * @base: base address of wdt
  56. * @clk: (optional) clock structure of wdt
  57. * @rate: (optional) clock rate when provided via properties
  58. * @adev: amba device structure of wdt
  59. * @status: current status of wdt
  60. * @load_val: load value to be set for current timeout
  61. */
  62. struct sp805_wdt {
  63. struct watchdog_device wdd;
  64. spinlock_t lock;
  65. void __iomem *base;
  66. struct clk *clk;
  67. u64 rate;
  68. struct amba_device *adev;
  69. unsigned int load_val;
  70. };
  71. static bool nowayout = WATCHDOG_NOWAYOUT;
  72. module_param(nowayout, bool, 0);
  73. MODULE_PARM_DESC(nowayout,
  74. "Set to 1 to keep watchdog running after device release");
  75. /* returns true if wdt is running; otherwise returns false */
  76. static bool wdt_is_running(struct watchdog_device *wdd)
  77. {
  78. struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
  79. u32 wdtcontrol = readl_relaxed(wdt->base + WDTCONTROL);
  80. return (wdtcontrol & ENABLE_MASK) == ENABLE_MASK;
  81. }
  82. /* This routine finds load value that will reset system in required timeout */
  83. static int wdt_setload(struct watchdog_device *wdd, unsigned int timeout)
  84. {
  85. struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
  86. u64 load, rate;
  87. rate = wdt->rate;
  88. /*
  89. * sp805 runs counter with given value twice, after the end of first
  90. * counter it gives an interrupt and then starts counter again. If
  91. * interrupt already occurred then it resets the system. This is why
  92. * load is half of what should be required.
  93. */
  94. load = div_u64(rate, 2) * timeout - 1;
  95. load = (load > LOAD_MAX) ? LOAD_MAX : load;
  96. load = (load < LOAD_MIN) ? LOAD_MIN : load;
  97. spin_lock(&wdt->lock);
  98. wdt->load_val = load;
  99. /* roundup timeout to closest positive integer value */
  100. wdd->timeout = div_u64((load + 1) * 2 + (rate / 2), rate);
  101. spin_unlock(&wdt->lock);
  102. return 0;
  103. }
  104. /* returns number of seconds left for reset to occur */
  105. static unsigned int wdt_timeleft(struct watchdog_device *wdd)
  106. {
  107. struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
  108. u64 load;
  109. spin_lock(&wdt->lock);
  110. load = readl_relaxed(wdt->base + WDTVALUE);
  111. /*If the interrupt is inactive then time left is WDTValue + WDTLoad. */
  112. if (!(readl_relaxed(wdt->base + WDTRIS) & INT_MASK))
  113. load += wdt->load_val + 1;
  114. spin_unlock(&wdt->lock);
  115. return div_u64(load, wdt->rate);
  116. }
  117. static int
  118. wdt_restart(struct watchdog_device *wdd, unsigned long mode, void *cmd)
  119. {
  120. struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
  121. writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
  122. writel_relaxed(0, wdt->base + WDTCONTROL);
  123. writel_relaxed(0, wdt->base + WDTLOAD);
  124. writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base + WDTCONTROL);
  125. /* Flush posted writes. */
  126. readl_relaxed(wdt->base + WDTLOCK);
  127. return 0;
  128. }
  129. static int wdt_config(struct watchdog_device *wdd, bool ping)
  130. {
  131. struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
  132. int ret;
  133. if (!ping) {
  134. ret = clk_prepare_enable(wdt->clk);
  135. if (ret) {
  136. dev_err(&wdt->adev->dev, "clock enable fail");
  137. return ret;
  138. }
  139. }
  140. spin_lock(&wdt->lock);
  141. writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
  142. writel_relaxed(wdt->load_val, wdt->base + WDTLOAD);
  143. writel_relaxed(INT_MASK, wdt->base + WDTINTCLR);
  144. if (!ping)
  145. writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base +
  146. WDTCONTROL);
  147. writel_relaxed(LOCK, wdt->base + WDTLOCK);
  148. /* Flush posted writes. */
  149. readl_relaxed(wdt->base + WDTLOCK);
  150. spin_unlock(&wdt->lock);
  151. return 0;
  152. }
  153. static int wdt_ping(struct watchdog_device *wdd)
  154. {
  155. return wdt_config(wdd, true);
  156. }
  157. /* enables watchdog timers reset */
  158. static int wdt_enable(struct watchdog_device *wdd)
  159. {
  160. return wdt_config(wdd, false);
  161. }
  162. /* disables watchdog timers reset */
  163. static int wdt_disable(struct watchdog_device *wdd)
  164. {
  165. struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
  166. spin_lock(&wdt->lock);
  167. writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
  168. writel_relaxed(0, wdt->base + WDTCONTROL);
  169. writel_relaxed(LOCK, wdt->base + WDTLOCK);
  170. /* Flush posted writes. */
  171. readl_relaxed(wdt->base + WDTLOCK);
  172. spin_unlock(&wdt->lock);
  173. clk_disable_unprepare(wdt->clk);
  174. return 0;
  175. }
  176. static const struct watchdog_info wdt_info = {
  177. .options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
  178. .identity = MODULE_NAME,
  179. };
  180. static const struct watchdog_ops wdt_ops = {
  181. .owner = THIS_MODULE,
  182. .start = wdt_enable,
  183. .stop = wdt_disable,
  184. .ping = wdt_ping,
  185. .set_timeout = wdt_setload,
  186. .get_timeleft = wdt_timeleft,
  187. .restart = wdt_restart,
  188. };
  189. static int
  190. sp805_wdt_probe(struct amba_device *adev, const struct amba_id *id)
  191. {
  192. struct sp805_wdt *wdt;
  193. u64 rate = 0;
  194. int ret = 0;
  195. wdt = devm_kzalloc(&adev->dev, sizeof(*wdt), GFP_KERNEL);
  196. if (!wdt) {
  197. ret = -ENOMEM;
  198. goto err;
  199. }
  200. wdt->base = devm_ioremap_resource(&adev->dev, &adev->res);
  201. if (IS_ERR(wdt->base))
  202. return PTR_ERR(wdt->base);
  203. /*
  204. * When driver probe with ACPI device, clock devices
  205. * are not available, so watchdog rate get from
  206. * clock-frequency property given in _DSD object.
  207. */
  208. device_property_read_u64(&adev->dev, "clock-frequency", &rate);
  209. wdt->clk = devm_clk_get_optional(&adev->dev, NULL);
  210. if (IS_ERR(wdt->clk))
  211. return dev_err_probe(&adev->dev, PTR_ERR(wdt->clk), "Clock not found\n");
  212. wdt->rate = clk_get_rate(wdt->clk);
  213. if (!wdt->rate)
  214. wdt->rate = rate;
  215. if (!wdt->rate) {
  216. dev_err(&adev->dev, "no clock-frequency property\n");
  217. return -ENODEV;
  218. }
  219. wdt->adev = adev;
  220. wdt->wdd.info = &wdt_info;
  221. wdt->wdd.ops = &wdt_ops;
  222. wdt->wdd.parent = &adev->dev;
  223. spin_lock_init(&wdt->lock);
  224. watchdog_set_nowayout(&wdt->wdd, nowayout);
  225. watchdog_set_drvdata(&wdt->wdd, wdt);
  226. watchdog_set_restart_priority(&wdt->wdd, 128);
  227. watchdog_stop_on_unregister(&wdt->wdd);
  228. /*
  229. * If 'timeout-sec' devicetree property is specified, use that.
  230. * Otherwise, use DEFAULT_TIMEOUT
  231. */
  232. wdt->wdd.timeout = DEFAULT_TIMEOUT;
  233. watchdog_init_timeout(&wdt->wdd, 0, &adev->dev);
  234. wdt_setload(&wdt->wdd, wdt->wdd.timeout);
  235. /*
  236. * If HW is already running, enable/reset the wdt and set the running
  237. * bit to tell the wdt subsystem
  238. */
  239. if (wdt_is_running(&wdt->wdd)) {
  240. wdt_enable(&wdt->wdd);
  241. set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
  242. }
  243. watchdog_stop_on_reboot(&wdt->wdd);
  244. ret = watchdog_register_device(&wdt->wdd);
  245. if (ret)
  246. goto err;
  247. amba_set_drvdata(adev, wdt);
  248. dev_info(&adev->dev, "registration successful\n");
  249. return 0;
  250. err:
  251. dev_err(&adev->dev, "Probe Failed!!!\n");
  252. return ret;
  253. }
  254. static void sp805_wdt_remove(struct amba_device *adev)
  255. {
  256. struct sp805_wdt *wdt = amba_get_drvdata(adev);
  257. watchdog_unregister_device(&wdt->wdd);
  258. watchdog_set_drvdata(&wdt->wdd, NULL);
  259. }
  260. static int __maybe_unused sp805_wdt_suspend(struct device *dev)
  261. {
  262. struct sp805_wdt *wdt = dev_get_drvdata(dev);
  263. if (watchdog_active(&wdt->wdd))
  264. return wdt_disable(&wdt->wdd);
  265. return 0;
  266. }
  267. static int __maybe_unused sp805_wdt_resume(struct device *dev)
  268. {
  269. struct sp805_wdt *wdt = dev_get_drvdata(dev);
  270. if (watchdog_active(&wdt->wdd))
  271. return wdt_enable(&wdt->wdd);
  272. return 0;
  273. }
  274. static SIMPLE_DEV_PM_OPS(sp805_wdt_dev_pm_ops, sp805_wdt_suspend,
  275. sp805_wdt_resume);
  276. static const struct amba_id sp805_wdt_ids[] = {
  277. {
  278. .id = 0x00141805,
  279. .mask = 0x00ffffff,
  280. },
  281. {
  282. .id = 0x001bb824,
  283. .mask = 0x00ffffff,
  284. },
  285. { 0, 0 },
  286. };
  287. MODULE_DEVICE_TABLE(amba, sp805_wdt_ids);
  288. static struct amba_driver sp805_wdt_driver = {
  289. .drv = {
  290. .name = MODULE_NAME,
  291. .pm = &sp805_wdt_dev_pm_ops,
  292. },
  293. .id_table = sp805_wdt_ids,
  294. .probe = sp805_wdt_probe,
  295. .remove = sp805_wdt_remove,
  296. };
  297. module_amba_driver(sp805_wdt_driver);
  298. MODULE_AUTHOR("Viresh Kumar <[email protected]>");
  299. MODULE_DESCRIPTION("ARM SP805 Watchdog Driver");
  300. MODULE_LICENSE("GPL");