max77620_wdt.c 7.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Maxim MAX77620 Watchdog Driver
  4. *
  5. * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
  6. * Copyright (C) 2022 Luca Ceresoli
  7. *
  8. * Author: Laxman Dewangan <[email protected]>
  9. * Author: Luca Ceresoli <[email protected]>
  10. */
  11. #include <linux/err.h>
  12. #include <linux/init.h>
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/mod_devicetable.h>
  16. #include <linux/mfd/max77620.h>
  17. #include <linux/mfd/max77714.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/regmap.h>
  20. #include <linux/slab.h>
  21. #include <linux/watchdog.h>
  22. static bool nowayout = WATCHDOG_NOWAYOUT;
  23. /**
  24. * struct max77620_variant - Data specific to a chip variant
  25. * @wdt_info: watchdog descriptor
  26. * @reg_onoff_cnfg2: ONOFF_CNFG2 register offset
  27. * @reg_cnfg_glbl2: CNFG_GLBL2 register offset
  28. * @reg_cnfg_glbl3: CNFG_GLBL3 register offset
  29. * @wdtc_mask: WDTC bit mask in CNFG_GLBL3 (=bits to update to ping the watchdog)
  30. * @bit_wd_rst_wk: WD_RST_WK bit offset within ONOFF_CNFG2
  31. * @cnfg_glbl2_cfg_bits: configuration bits to enable in CNFG_GLBL2 register
  32. */
  33. struct max77620_variant {
  34. u8 reg_onoff_cnfg2;
  35. u8 reg_cnfg_glbl2;
  36. u8 reg_cnfg_glbl3;
  37. u8 wdtc_mask;
  38. u8 bit_wd_rst_wk;
  39. u8 cnfg_glbl2_cfg_bits;
  40. };
  41. struct max77620_wdt {
  42. struct device *dev;
  43. struct regmap *rmap;
  44. const struct max77620_variant *drv_data;
  45. struct watchdog_device wdt_dev;
  46. };
  47. static const struct max77620_variant max77620_wdt_data = {
  48. .reg_onoff_cnfg2 = MAX77620_REG_ONOFFCNFG2,
  49. .reg_cnfg_glbl2 = MAX77620_REG_CNFGGLBL2,
  50. .reg_cnfg_glbl3 = MAX77620_REG_CNFGGLBL3,
  51. .wdtc_mask = MAX77620_WDTC_MASK,
  52. .bit_wd_rst_wk = MAX77620_ONOFFCNFG2_WD_RST_WK,
  53. /* Set WDT clear in OFF and sleep mode */
  54. .cnfg_glbl2_cfg_bits = MAX77620_WDTSLPC | MAX77620_WDTOFFC,
  55. };
  56. static const struct max77620_variant max77714_wdt_data = {
  57. .reg_onoff_cnfg2 = MAX77714_CNFG2_ONOFF,
  58. .reg_cnfg_glbl2 = MAX77714_CNFG_GLBL2,
  59. .reg_cnfg_glbl3 = MAX77714_CNFG_GLBL3,
  60. .wdtc_mask = MAX77714_WDTC,
  61. .bit_wd_rst_wk = MAX77714_WD_RST_WK,
  62. /* Set WDT clear in sleep mode (there is no WDTOFFC on MAX77714) */
  63. .cnfg_glbl2_cfg_bits = MAX77714_WDTSLPC,
  64. };
  65. static int max77620_wdt_start(struct watchdog_device *wdt_dev)
  66. {
  67. struct max77620_wdt *wdt = watchdog_get_drvdata(wdt_dev);
  68. return regmap_update_bits(wdt->rmap, wdt->drv_data->reg_cnfg_glbl2,
  69. MAX77620_WDTEN, MAX77620_WDTEN);
  70. }
  71. static int max77620_wdt_stop(struct watchdog_device *wdt_dev)
  72. {
  73. struct max77620_wdt *wdt = watchdog_get_drvdata(wdt_dev);
  74. return regmap_update_bits(wdt->rmap, wdt->drv_data->reg_cnfg_glbl2,
  75. MAX77620_WDTEN, 0);
  76. }
  77. static int max77620_wdt_ping(struct watchdog_device *wdt_dev)
  78. {
  79. struct max77620_wdt *wdt = watchdog_get_drvdata(wdt_dev);
  80. return regmap_update_bits(wdt->rmap, wdt->drv_data->reg_cnfg_glbl3,
  81. wdt->drv_data->wdtc_mask, 0x1);
  82. }
  83. static int max77620_wdt_set_timeout(struct watchdog_device *wdt_dev,
  84. unsigned int timeout)
  85. {
  86. struct max77620_wdt *wdt = watchdog_get_drvdata(wdt_dev);
  87. unsigned int wdt_timeout;
  88. u8 regval;
  89. int ret;
  90. switch (timeout) {
  91. case 0 ... 2:
  92. regval = MAX77620_TWD_2s;
  93. wdt_timeout = 2;
  94. break;
  95. case 3 ... 16:
  96. regval = MAX77620_TWD_16s;
  97. wdt_timeout = 16;
  98. break;
  99. case 17 ... 64:
  100. regval = MAX77620_TWD_64s;
  101. wdt_timeout = 64;
  102. break;
  103. default:
  104. regval = MAX77620_TWD_128s;
  105. wdt_timeout = 128;
  106. break;
  107. }
  108. /*
  109. * "If the value of TWD needs to be changed, clear the system
  110. * watchdog timer first [...], then change the value of TWD."
  111. * (MAX77714 datasheet but applies to MAX77620 too)
  112. */
  113. ret = regmap_update_bits(wdt->rmap, wdt->drv_data->reg_cnfg_glbl3,
  114. wdt->drv_data->wdtc_mask, 0x1);
  115. if (ret < 0)
  116. return ret;
  117. ret = regmap_update_bits(wdt->rmap, wdt->drv_data->reg_cnfg_glbl2,
  118. MAX77620_TWD_MASK, regval);
  119. if (ret < 0)
  120. return ret;
  121. wdt_dev->timeout = wdt_timeout;
  122. return 0;
  123. }
  124. static const struct watchdog_info max77620_wdt_info = {
  125. .identity = "max77620-watchdog",
  126. .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
  127. };
  128. static const struct watchdog_ops max77620_wdt_ops = {
  129. .start = max77620_wdt_start,
  130. .stop = max77620_wdt_stop,
  131. .ping = max77620_wdt_ping,
  132. .set_timeout = max77620_wdt_set_timeout,
  133. };
  134. static int max77620_wdt_probe(struct platform_device *pdev)
  135. {
  136. const struct platform_device_id *id = platform_get_device_id(pdev);
  137. struct device *dev = &pdev->dev;
  138. struct max77620_wdt *wdt;
  139. struct watchdog_device *wdt_dev;
  140. unsigned int regval;
  141. int ret;
  142. wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
  143. if (!wdt)
  144. return -ENOMEM;
  145. wdt->dev = dev;
  146. wdt->drv_data = (const struct max77620_variant *) id->driver_data;
  147. wdt->rmap = dev_get_regmap(dev->parent, NULL);
  148. if (!wdt->rmap) {
  149. dev_err(wdt->dev, "Failed to get parent regmap\n");
  150. return -ENODEV;
  151. }
  152. wdt_dev = &wdt->wdt_dev;
  153. wdt_dev->info = &max77620_wdt_info;
  154. wdt_dev->ops = &max77620_wdt_ops;
  155. wdt_dev->min_timeout = 2;
  156. wdt_dev->max_timeout = 128;
  157. wdt_dev->max_hw_heartbeat_ms = 128 * 1000;
  158. platform_set_drvdata(pdev, wdt);
  159. /* Enable WD_RST_WK - WDT expire results in a restart */
  160. ret = regmap_update_bits(wdt->rmap, wdt->drv_data->reg_onoff_cnfg2,
  161. wdt->drv_data->bit_wd_rst_wk,
  162. wdt->drv_data->bit_wd_rst_wk);
  163. if (ret < 0) {
  164. dev_err(wdt->dev, "Failed to set WD_RST_WK: %d\n", ret);
  165. return ret;
  166. }
  167. /* Set the "auto WDT clear" bits available on the chip */
  168. ret = regmap_update_bits(wdt->rmap, wdt->drv_data->reg_cnfg_glbl2,
  169. wdt->drv_data->cnfg_glbl2_cfg_bits,
  170. wdt->drv_data->cnfg_glbl2_cfg_bits);
  171. if (ret < 0) {
  172. dev_err(wdt->dev, "Failed to set WDT OFF mode: %d\n", ret);
  173. return ret;
  174. }
  175. /* Check if WDT running and if yes then set flags properly */
  176. ret = regmap_read(wdt->rmap, wdt->drv_data->reg_cnfg_glbl2, &regval);
  177. if (ret < 0) {
  178. dev_err(wdt->dev, "Failed to read WDT CFG register: %d\n", ret);
  179. return ret;
  180. }
  181. switch (regval & MAX77620_TWD_MASK) {
  182. case MAX77620_TWD_2s:
  183. wdt_dev->timeout = 2;
  184. break;
  185. case MAX77620_TWD_16s:
  186. wdt_dev->timeout = 16;
  187. break;
  188. case MAX77620_TWD_64s:
  189. wdt_dev->timeout = 64;
  190. break;
  191. default:
  192. wdt_dev->timeout = 128;
  193. break;
  194. }
  195. if (regval & MAX77620_WDTEN)
  196. set_bit(WDOG_HW_RUNNING, &wdt_dev->status);
  197. watchdog_set_nowayout(wdt_dev, nowayout);
  198. watchdog_set_drvdata(wdt_dev, wdt);
  199. watchdog_stop_on_unregister(wdt_dev);
  200. return devm_watchdog_register_device(dev, wdt_dev);
  201. }
  202. static const struct platform_device_id max77620_wdt_devtype[] = {
  203. { "max77620-watchdog", (kernel_ulong_t)&max77620_wdt_data },
  204. { "max77714-watchdog", (kernel_ulong_t)&max77714_wdt_data },
  205. { },
  206. };
  207. MODULE_DEVICE_TABLE(platform, max77620_wdt_devtype);
  208. static struct platform_driver max77620_wdt_driver = {
  209. .driver = {
  210. .name = "max77620-watchdog",
  211. },
  212. .probe = max77620_wdt_probe,
  213. .id_table = max77620_wdt_devtype,
  214. };
  215. module_platform_driver(max77620_wdt_driver);
  216. MODULE_DESCRIPTION("Max77620 watchdog timer driver");
  217. module_param(nowayout, bool, 0);
  218. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
  219. "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  220. MODULE_AUTHOR("Laxman Dewangan <[email protected]>");
  221. MODULE_AUTHOR("Luca Ceresoli <[email protected]>");
  222. MODULE_LICENSE("GPL v2");