sm501fb.c 53 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* linux/drivers/video/sm501fb.c
  3. *
  4. * Copyright (c) 2006 Simtec Electronics
  5. * Vincent Sanders <[email protected]>
  6. * Ben Dooks <[email protected]>
  7. *
  8. * Framebuffer driver for the Silicon Motion SM501
  9. */
  10. #include <linux/module.h>
  11. #include <linux/kernel.h>
  12. #include <linux/errno.h>
  13. #include <linux/string.h>
  14. #include <linux/mm.h>
  15. #include <linux/tty.h>
  16. #include <linux/slab.h>
  17. #include <linux/delay.h>
  18. #include <linux/fb.h>
  19. #include <linux/init.h>
  20. #include <linux/vmalloc.h>
  21. #include <linux/dma-mapping.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/workqueue.h>
  24. #include <linux/wait.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/clk.h>
  27. #include <linux/console.h>
  28. #include <linux/io.h>
  29. #include <linux/uaccess.h>
  30. #include <asm/div64.h>
  31. #ifdef CONFIG_PM
  32. #include <linux/pm.h>
  33. #endif
  34. #include <linux/sm501.h>
  35. #include <linux/sm501-regs.h>
  36. #include "edid.h"
  37. static char *fb_mode = "640x480-16@60";
  38. static unsigned long default_bpp = 16;
  39. static const struct fb_videomode sm501_default_mode = {
  40. .refresh = 60,
  41. .xres = 640,
  42. .yres = 480,
  43. .pixclock = 20833,
  44. .left_margin = 142,
  45. .right_margin = 13,
  46. .upper_margin = 21,
  47. .lower_margin = 1,
  48. .hsync_len = 69,
  49. .vsync_len = 3,
  50. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  51. .vmode = FB_VMODE_NONINTERLACED
  52. };
  53. #define NR_PALETTE 256
  54. enum sm501_controller {
  55. HEAD_CRT = 0,
  56. HEAD_PANEL = 1,
  57. };
  58. /* SM501 memory address.
  59. *
  60. * This structure is used to track memory usage within the SM501 framebuffer
  61. * allocation. The sm_addr field is stored as an offset as it is often used
  62. * against both the physical and mapped addresses.
  63. */
  64. struct sm501_mem {
  65. unsigned long size;
  66. unsigned long sm_addr; /* offset from base of sm501 fb. */
  67. void __iomem *k_addr;
  68. };
  69. /* private data that is shared between all frambuffers* */
  70. struct sm501fb_info {
  71. struct device *dev;
  72. struct fb_info *fb[2]; /* fb info for both heads */
  73. struct resource *fbmem_res; /* framebuffer resource */
  74. struct resource *regs_res; /* registers resource */
  75. struct resource *regs2d_res; /* 2d registers resource */
  76. struct sm501_platdata_fb *pdata; /* our platform data */
  77. unsigned long pm_crt_ctrl; /* pm: crt ctrl save */
  78. int irq;
  79. int swap_endian; /* set to swap rgb=>bgr */
  80. void __iomem *regs; /* remapped registers */
  81. void __iomem *regs2d; /* 2d remapped registers */
  82. void __iomem *fbmem; /* remapped framebuffer */
  83. size_t fbmem_len; /* length of remapped region */
  84. u8 *edid_data;
  85. };
  86. /* per-framebuffer private data */
  87. struct sm501fb_par {
  88. u32 pseudo_palette[16];
  89. enum sm501_controller head;
  90. struct sm501_mem cursor;
  91. struct sm501_mem screen;
  92. struct fb_ops ops;
  93. void *store_fb;
  94. void *store_cursor;
  95. void __iomem *cursor_regs;
  96. struct sm501fb_info *info;
  97. };
  98. /* Helper functions */
  99. static inline int h_total(struct fb_var_screeninfo *var)
  100. {
  101. return var->xres + var->left_margin +
  102. var->right_margin + var->hsync_len;
  103. }
  104. static inline int v_total(struct fb_var_screeninfo *var)
  105. {
  106. return var->yres + var->upper_margin +
  107. var->lower_margin + var->vsync_len;
  108. }
  109. /* sm501fb_sync_regs()
  110. *
  111. * This call is mainly for PCI bus systems where we need to
  112. * ensure that any writes to the bus are completed before the
  113. * next phase, or after completing a function.
  114. */
  115. static inline void sm501fb_sync_regs(struct sm501fb_info *info)
  116. {
  117. smc501_readl(info->regs);
  118. }
  119. /* sm501_alloc_mem
  120. *
  121. * This is an attempt to lay out memory for the two framebuffers and
  122. * everything else
  123. *
  124. * |fbmem_res->start fbmem_res->end|
  125. * | |
  126. * |fb[0].fix.smem_start | |fb[1].fix.smem_start | 2K |
  127. * |-> fb[0].fix.smem_len <-| spare |-> fb[1].fix.smem_len <-|-> cursors <-|
  128. *
  129. * The "spare" space is for the 2d engine data
  130. * the fixed is space for the cursors (2x1Kbyte)
  131. *
  132. * we need to allocate memory for the 2D acceleration engine
  133. * command list and the data for the engine to deal with.
  134. *
  135. * - all allocations must be 128bit aligned
  136. * - cursors are 64x64x2 bits (1Kbyte)
  137. *
  138. */
  139. #define SM501_MEMF_CURSOR (1)
  140. #define SM501_MEMF_PANEL (2)
  141. #define SM501_MEMF_CRT (4)
  142. #define SM501_MEMF_ACCEL (8)
  143. static int sm501_alloc_mem(struct sm501fb_info *inf, struct sm501_mem *mem,
  144. unsigned int why, size_t size, u32 smem_len)
  145. {
  146. struct sm501fb_par *par;
  147. struct fb_info *fbi;
  148. unsigned int ptr;
  149. unsigned int end;
  150. switch (why) {
  151. case SM501_MEMF_CURSOR:
  152. ptr = inf->fbmem_len - size;
  153. inf->fbmem_len = ptr; /* adjust available memory. */
  154. break;
  155. case SM501_MEMF_PANEL:
  156. if (size > inf->fbmem_len)
  157. return -ENOMEM;
  158. ptr = inf->fbmem_len - size;
  159. fbi = inf->fb[HEAD_CRT];
  160. /* round down, some programs such as directfb do not draw
  161. * 0,0 correctly unless the start is aligned to a page start.
  162. */
  163. if (ptr > 0)
  164. ptr &= ~(PAGE_SIZE - 1);
  165. if (fbi && ptr < smem_len)
  166. return -ENOMEM;
  167. break;
  168. case SM501_MEMF_CRT:
  169. ptr = 0;
  170. /* check to see if we have panel memory allocated
  171. * which would put an limit on available memory. */
  172. fbi = inf->fb[HEAD_PANEL];
  173. if (fbi) {
  174. par = fbi->par;
  175. end = par->screen.k_addr ? par->screen.sm_addr : inf->fbmem_len;
  176. } else
  177. end = inf->fbmem_len;
  178. if ((ptr + size) > end)
  179. return -ENOMEM;
  180. break;
  181. case SM501_MEMF_ACCEL:
  182. fbi = inf->fb[HEAD_CRT];
  183. ptr = fbi ? smem_len : 0;
  184. fbi = inf->fb[HEAD_PANEL];
  185. if (fbi) {
  186. par = fbi->par;
  187. end = par->screen.sm_addr;
  188. } else
  189. end = inf->fbmem_len;
  190. if ((ptr + size) > end)
  191. return -ENOMEM;
  192. break;
  193. default:
  194. return -EINVAL;
  195. }
  196. mem->size = size;
  197. mem->sm_addr = ptr;
  198. mem->k_addr = inf->fbmem + ptr;
  199. dev_dbg(inf->dev, "%s: result %08lx, %p - %u, %zd\n",
  200. __func__, mem->sm_addr, mem->k_addr, why, size);
  201. return 0;
  202. }
  203. /* sm501fb_ps_to_hz
  204. *
  205. * Converts a period in picoseconds to Hz.
  206. *
  207. * Note, we try to keep this in Hz to minimise rounding with
  208. * the limited PLL settings on the SM501.
  209. */
  210. static unsigned long sm501fb_ps_to_hz(unsigned long psvalue)
  211. {
  212. unsigned long long numerator=1000000000000ULL;
  213. /* 10^12 / picosecond period gives frequency in Hz */
  214. do_div(numerator, psvalue);
  215. return (unsigned long)numerator;
  216. }
  217. /* sm501fb_hz_to_ps is identical to the opposite transform */
  218. #define sm501fb_hz_to_ps(x) sm501fb_ps_to_hz(x)
  219. /* sm501fb_setup_gamma
  220. *
  221. * Programs a linear 1.0 gamma ramp in case the gamma
  222. * correction is enabled without programming anything else.
  223. */
  224. static void sm501fb_setup_gamma(struct sm501fb_info *fbi,
  225. unsigned long palette)
  226. {
  227. unsigned long value = 0;
  228. int offset;
  229. /* set gamma values */
  230. for (offset = 0; offset < 256 * 4; offset += 4) {
  231. smc501_writel(value, fbi->regs + palette + offset);
  232. value += 0x010101; /* Advance RGB by 1,1,1.*/
  233. }
  234. }
  235. /* sm501fb_check_var
  236. *
  237. * check common variables for both panel and crt
  238. */
  239. static int sm501fb_check_var(struct fb_var_screeninfo *var,
  240. struct fb_info *info)
  241. {
  242. struct sm501fb_par *par = info->par;
  243. struct sm501fb_info *sm = par->info;
  244. unsigned long tmp;
  245. /* check we can fit these values into the registers */
  246. if (var->hsync_len > 255 || var->vsync_len > 63)
  247. return -EINVAL;
  248. /* hdisplay end and hsync start */
  249. if ((var->xres + var->right_margin) > 4096)
  250. return -EINVAL;
  251. /* vdisplay end and vsync start */
  252. if ((var->yres + var->lower_margin) > 2048)
  253. return -EINVAL;
  254. /* hard limits of device */
  255. if (h_total(var) > 4096 || v_total(var) > 2048)
  256. return -EINVAL;
  257. /* check our line length is going to be 128 bit aligned */
  258. tmp = (var->xres * var->bits_per_pixel) / 8;
  259. if ((tmp & 15) != 0)
  260. return -EINVAL;
  261. /* check the virtual size */
  262. if (var->xres_virtual > 4096 || var->yres_virtual > 2048)
  263. return -EINVAL;
  264. /* can cope with 8,16 or 32bpp */
  265. if (var->bits_per_pixel <= 8)
  266. var->bits_per_pixel = 8;
  267. else if (var->bits_per_pixel <= 16)
  268. var->bits_per_pixel = 16;
  269. else if (var->bits_per_pixel == 24)
  270. var->bits_per_pixel = 32;
  271. /* set r/g/b positions and validate bpp */
  272. switch(var->bits_per_pixel) {
  273. case 8:
  274. var->red.length = var->bits_per_pixel;
  275. var->red.offset = 0;
  276. var->green.length = var->bits_per_pixel;
  277. var->green.offset = 0;
  278. var->blue.length = var->bits_per_pixel;
  279. var->blue.offset = 0;
  280. var->transp.length = 0;
  281. var->transp.offset = 0;
  282. break;
  283. case 16:
  284. if (sm->pdata->flags & SM501_FBPD_SWAP_FB_ENDIAN) {
  285. var->blue.offset = 11;
  286. var->green.offset = 5;
  287. var->red.offset = 0;
  288. } else {
  289. var->red.offset = 11;
  290. var->green.offset = 5;
  291. var->blue.offset = 0;
  292. }
  293. var->transp.offset = 0;
  294. var->red.length = 5;
  295. var->green.length = 6;
  296. var->blue.length = 5;
  297. var->transp.length = 0;
  298. break;
  299. case 32:
  300. if (sm->pdata->flags & SM501_FBPD_SWAP_FB_ENDIAN) {
  301. var->transp.offset = 0;
  302. var->red.offset = 8;
  303. var->green.offset = 16;
  304. var->blue.offset = 24;
  305. } else {
  306. var->transp.offset = 24;
  307. var->red.offset = 16;
  308. var->green.offset = 8;
  309. var->blue.offset = 0;
  310. }
  311. var->red.length = 8;
  312. var->green.length = 8;
  313. var->blue.length = 8;
  314. var->transp.length = 0;
  315. break;
  316. default:
  317. return -EINVAL;
  318. }
  319. return 0;
  320. }
  321. /*
  322. * sm501fb_check_var_crt():
  323. *
  324. * check the parameters for the CRT head, and either bring them
  325. * back into range, or return -EINVAL.
  326. */
  327. static int sm501fb_check_var_crt(struct fb_var_screeninfo *var,
  328. struct fb_info *info)
  329. {
  330. return sm501fb_check_var(var, info);
  331. }
  332. /* sm501fb_check_var_pnl():
  333. *
  334. * check the parameters for the CRT head, and either bring them
  335. * back into range, or return -EINVAL.
  336. */
  337. static int sm501fb_check_var_pnl(struct fb_var_screeninfo *var,
  338. struct fb_info *info)
  339. {
  340. return sm501fb_check_var(var, info);
  341. }
  342. /* sm501fb_set_par_common
  343. *
  344. * set common registers for framebuffers
  345. */
  346. static int sm501fb_set_par_common(struct fb_info *info,
  347. struct fb_var_screeninfo *var)
  348. {
  349. struct sm501fb_par *par = info->par;
  350. struct sm501fb_info *fbi = par->info;
  351. unsigned long pixclock; /* pixelclock in Hz */
  352. unsigned long sm501pixclock; /* pixelclock the 501 can achieve in Hz */
  353. unsigned int mem_type;
  354. unsigned int clock_type;
  355. unsigned int head_addr;
  356. unsigned int smem_len;
  357. dev_dbg(fbi->dev, "%s: %dx%d, bpp = %d, virtual %dx%d\n",
  358. __func__, var->xres, var->yres, var->bits_per_pixel,
  359. var->xres_virtual, var->yres_virtual);
  360. switch (par->head) {
  361. case HEAD_CRT:
  362. mem_type = SM501_MEMF_CRT;
  363. clock_type = SM501_CLOCK_V2XCLK;
  364. head_addr = SM501_DC_CRT_FB_ADDR;
  365. break;
  366. case HEAD_PANEL:
  367. mem_type = SM501_MEMF_PANEL;
  368. clock_type = SM501_CLOCK_P2XCLK;
  369. head_addr = SM501_DC_PANEL_FB_ADDR;
  370. break;
  371. default:
  372. mem_type = 0; /* stop compiler warnings */
  373. head_addr = 0;
  374. clock_type = 0;
  375. }
  376. switch (var->bits_per_pixel) {
  377. case 8:
  378. info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
  379. break;
  380. case 16:
  381. info->fix.visual = FB_VISUAL_TRUECOLOR;
  382. break;
  383. case 32:
  384. info->fix.visual = FB_VISUAL_TRUECOLOR;
  385. break;
  386. }
  387. /* allocate fb memory within 501 */
  388. info->fix.line_length = (var->xres_virtual * var->bits_per_pixel)/8;
  389. smem_len = info->fix.line_length * var->yres_virtual;
  390. dev_dbg(fbi->dev, "%s: line length = %u\n", __func__,
  391. info->fix.line_length);
  392. if (sm501_alloc_mem(fbi, &par->screen, mem_type, smem_len, smem_len)) {
  393. dev_err(fbi->dev, "no memory available\n");
  394. return -ENOMEM;
  395. }
  396. mutex_lock(&info->mm_lock);
  397. info->fix.smem_start = fbi->fbmem_res->start + par->screen.sm_addr;
  398. info->fix.smem_len = smem_len;
  399. mutex_unlock(&info->mm_lock);
  400. info->screen_base = fbi->fbmem + par->screen.sm_addr;
  401. info->screen_size = info->fix.smem_len;
  402. /* set start of framebuffer to the screen */
  403. smc501_writel(par->screen.sm_addr | SM501_ADDR_FLIP,
  404. fbi->regs + head_addr);
  405. /* program CRT clock */
  406. pixclock = sm501fb_ps_to_hz(var->pixclock);
  407. sm501pixclock = sm501_set_clock(fbi->dev->parent, clock_type,
  408. pixclock);
  409. /* update fb layer with actual clock used */
  410. var->pixclock = sm501fb_hz_to_ps(sm501pixclock);
  411. dev_dbg(fbi->dev, "%s: pixclock(ps) = %u, pixclock(Hz) = %lu, "
  412. "sm501pixclock = %lu, error = %ld%%\n",
  413. __func__, var->pixclock, pixclock, sm501pixclock,
  414. ((pixclock - sm501pixclock)*100)/pixclock);
  415. return 0;
  416. }
  417. /* sm501fb_set_par_geometry
  418. *
  419. * set the geometry registers for specified framebuffer.
  420. */
  421. static void sm501fb_set_par_geometry(struct fb_info *info,
  422. struct fb_var_screeninfo *var)
  423. {
  424. struct sm501fb_par *par = info->par;
  425. struct sm501fb_info *fbi = par->info;
  426. void __iomem *base = fbi->regs;
  427. unsigned long reg;
  428. if (par->head == HEAD_CRT)
  429. base += SM501_DC_CRT_H_TOT;
  430. else
  431. base += SM501_DC_PANEL_H_TOT;
  432. /* set framebuffer width and display width */
  433. reg = info->fix.line_length;
  434. reg |= ((var->xres * var->bits_per_pixel)/8) << 16;
  435. smc501_writel(reg, fbi->regs + (par->head == HEAD_CRT ?
  436. SM501_DC_CRT_FB_OFFSET : SM501_DC_PANEL_FB_OFFSET));
  437. /* program horizontal total */
  438. reg = (h_total(var) - 1) << 16;
  439. reg |= (var->xres - 1);
  440. smc501_writel(reg, base + SM501_OFF_DC_H_TOT);
  441. /* program horizontal sync */
  442. reg = var->hsync_len << 16;
  443. reg |= var->xres + var->right_margin - 1;
  444. smc501_writel(reg, base + SM501_OFF_DC_H_SYNC);
  445. /* program vertical total */
  446. reg = (v_total(var) - 1) << 16;
  447. reg |= (var->yres - 1);
  448. smc501_writel(reg, base + SM501_OFF_DC_V_TOT);
  449. /* program vertical sync */
  450. reg = var->vsync_len << 16;
  451. reg |= var->yres + var->lower_margin - 1;
  452. smc501_writel(reg, base + SM501_OFF_DC_V_SYNC);
  453. }
  454. /* sm501fb_pan_crt
  455. *
  456. * pan the CRT display output within an virtual framebuffer
  457. */
  458. static int sm501fb_pan_crt(struct fb_var_screeninfo *var,
  459. struct fb_info *info)
  460. {
  461. struct sm501fb_par *par = info->par;
  462. struct sm501fb_info *fbi = par->info;
  463. unsigned int bytes_pixel = info->var.bits_per_pixel / 8;
  464. unsigned long reg;
  465. unsigned long xoffs;
  466. xoffs = var->xoffset * bytes_pixel;
  467. reg = smc501_readl(fbi->regs + SM501_DC_CRT_CONTROL);
  468. reg &= ~SM501_DC_CRT_CONTROL_PIXEL_MASK;
  469. reg |= ((xoffs & 15) / bytes_pixel) << 4;
  470. smc501_writel(reg, fbi->regs + SM501_DC_CRT_CONTROL);
  471. reg = (par->screen.sm_addr + xoffs +
  472. var->yoffset * info->fix.line_length);
  473. smc501_writel(reg | SM501_ADDR_FLIP, fbi->regs + SM501_DC_CRT_FB_ADDR);
  474. sm501fb_sync_regs(fbi);
  475. return 0;
  476. }
  477. /* sm501fb_pan_pnl
  478. *
  479. * pan the panel display output within an virtual framebuffer
  480. */
  481. static int sm501fb_pan_pnl(struct fb_var_screeninfo *var,
  482. struct fb_info *info)
  483. {
  484. struct sm501fb_par *par = info->par;
  485. struct sm501fb_info *fbi = par->info;
  486. unsigned long reg;
  487. reg = var->xoffset | (info->var.xres_virtual << 16);
  488. smc501_writel(reg, fbi->regs + SM501_DC_PANEL_FB_WIDTH);
  489. reg = var->yoffset | (info->var.yres_virtual << 16);
  490. smc501_writel(reg, fbi->regs + SM501_DC_PANEL_FB_HEIGHT);
  491. sm501fb_sync_regs(fbi);
  492. return 0;
  493. }
  494. /* sm501fb_set_par_crt
  495. *
  496. * Set the CRT video mode from the fb_info structure
  497. */
  498. static int sm501fb_set_par_crt(struct fb_info *info)
  499. {
  500. struct sm501fb_par *par = info->par;
  501. struct sm501fb_info *fbi = par->info;
  502. struct fb_var_screeninfo *var = &info->var;
  503. unsigned long control; /* control register */
  504. int ret;
  505. /* activate new configuration */
  506. dev_dbg(fbi->dev, "%s(%p)\n", __func__, info);
  507. /* enable CRT DAC - note 0 is on!*/
  508. sm501_misc_control(fbi->dev->parent, 0, SM501_MISC_DAC_POWER);
  509. control = smc501_readl(fbi->regs + SM501_DC_CRT_CONTROL);
  510. control &= (SM501_DC_CRT_CONTROL_PIXEL_MASK |
  511. SM501_DC_CRT_CONTROL_GAMMA |
  512. SM501_DC_CRT_CONTROL_BLANK |
  513. SM501_DC_CRT_CONTROL_SEL |
  514. SM501_DC_CRT_CONTROL_CP |
  515. SM501_DC_CRT_CONTROL_TVP);
  516. /* set the sync polarities before we check data source */
  517. if ((var->sync & FB_SYNC_HOR_HIGH_ACT) == 0)
  518. control |= SM501_DC_CRT_CONTROL_HSP;
  519. if ((var->sync & FB_SYNC_VERT_HIGH_ACT) == 0)
  520. control |= SM501_DC_CRT_CONTROL_VSP;
  521. if ((control & SM501_DC_CRT_CONTROL_SEL) == 0) {
  522. /* the head is displaying panel data... */
  523. sm501_alloc_mem(fbi, &par->screen, SM501_MEMF_CRT, 0,
  524. info->fix.smem_len);
  525. goto out_update;
  526. }
  527. ret = sm501fb_set_par_common(info, var);
  528. if (ret) {
  529. dev_err(fbi->dev, "failed to set common parameters\n");
  530. return ret;
  531. }
  532. sm501fb_pan_crt(var, info);
  533. sm501fb_set_par_geometry(info, var);
  534. control |= SM501_FIFO_3; /* fill if >3 free slots */
  535. switch(var->bits_per_pixel) {
  536. case 8:
  537. control |= SM501_DC_CRT_CONTROL_8BPP;
  538. break;
  539. case 16:
  540. control |= SM501_DC_CRT_CONTROL_16BPP;
  541. sm501fb_setup_gamma(fbi, SM501_DC_CRT_PALETTE);
  542. break;
  543. case 32:
  544. control |= SM501_DC_CRT_CONTROL_32BPP;
  545. sm501fb_setup_gamma(fbi, SM501_DC_CRT_PALETTE);
  546. break;
  547. default:
  548. BUG();
  549. }
  550. control |= SM501_DC_CRT_CONTROL_SEL; /* CRT displays CRT data */
  551. control |= SM501_DC_CRT_CONTROL_TE; /* enable CRT timing */
  552. control |= SM501_DC_CRT_CONTROL_ENABLE; /* enable CRT plane */
  553. out_update:
  554. dev_dbg(fbi->dev, "new control is %08lx\n", control);
  555. smc501_writel(control, fbi->regs + SM501_DC_CRT_CONTROL);
  556. sm501fb_sync_regs(fbi);
  557. return 0;
  558. }
  559. static void sm501fb_panel_power(struct sm501fb_info *fbi, int to)
  560. {
  561. unsigned long control;
  562. void __iomem *ctrl_reg = fbi->regs + SM501_DC_PANEL_CONTROL;
  563. struct sm501_platdata_fbsub *pd = fbi->pdata->fb_pnl;
  564. control = smc501_readl(ctrl_reg);
  565. if (to && (control & SM501_DC_PANEL_CONTROL_VDD) == 0) {
  566. /* enable panel power */
  567. control |= SM501_DC_PANEL_CONTROL_VDD; /* FPVDDEN */
  568. smc501_writel(control, ctrl_reg);
  569. sm501fb_sync_regs(fbi);
  570. mdelay(10);
  571. control |= SM501_DC_PANEL_CONTROL_DATA; /* DATA */
  572. smc501_writel(control, ctrl_reg);
  573. sm501fb_sync_regs(fbi);
  574. mdelay(10);
  575. /* VBIASEN */
  576. if (!(pd->flags & SM501FB_FLAG_PANEL_NO_VBIASEN)) {
  577. if (pd->flags & SM501FB_FLAG_PANEL_INV_VBIASEN)
  578. control &= ~SM501_DC_PANEL_CONTROL_BIAS;
  579. else
  580. control |= SM501_DC_PANEL_CONTROL_BIAS;
  581. smc501_writel(control, ctrl_reg);
  582. sm501fb_sync_regs(fbi);
  583. mdelay(10);
  584. }
  585. if (!(pd->flags & SM501FB_FLAG_PANEL_NO_FPEN)) {
  586. if (pd->flags & SM501FB_FLAG_PANEL_INV_FPEN)
  587. control &= ~SM501_DC_PANEL_CONTROL_FPEN;
  588. else
  589. control |= SM501_DC_PANEL_CONTROL_FPEN;
  590. smc501_writel(control, ctrl_reg);
  591. sm501fb_sync_regs(fbi);
  592. mdelay(10);
  593. }
  594. } else if (!to && (control & SM501_DC_PANEL_CONTROL_VDD) != 0) {
  595. /* disable panel power */
  596. if (!(pd->flags & SM501FB_FLAG_PANEL_NO_FPEN)) {
  597. if (pd->flags & SM501FB_FLAG_PANEL_INV_FPEN)
  598. control |= SM501_DC_PANEL_CONTROL_FPEN;
  599. else
  600. control &= ~SM501_DC_PANEL_CONTROL_FPEN;
  601. smc501_writel(control, ctrl_reg);
  602. sm501fb_sync_regs(fbi);
  603. mdelay(10);
  604. }
  605. if (!(pd->flags & SM501FB_FLAG_PANEL_NO_VBIASEN)) {
  606. if (pd->flags & SM501FB_FLAG_PANEL_INV_VBIASEN)
  607. control |= SM501_DC_PANEL_CONTROL_BIAS;
  608. else
  609. control &= ~SM501_DC_PANEL_CONTROL_BIAS;
  610. smc501_writel(control, ctrl_reg);
  611. sm501fb_sync_regs(fbi);
  612. mdelay(10);
  613. }
  614. control &= ~SM501_DC_PANEL_CONTROL_DATA;
  615. smc501_writel(control, ctrl_reg);
  616. sm501fb_sync_regs(fbi);
  617. mdelay(10);
  618. control &= ~SM501_DC_PANEL_CONTROL_VDD;
  619. smc501_writel(control, ctrl_reg);
  620. sm501fb_sync_regs(fbi);
  621. mdelay(10);
  622. }
  623. sm501fb_sync_regs(fbi);
  624. }
  625. /* sm501fb_set_par_pnl
  626. *
  627. * Set the panel video mode from the fb_info structure
  628. */
  629. static int sm501fb_set_par_pnl(struct fb_info *info)
  630. {
  631. struct sm501fb_par *par = info->par;
  632. struct sm501fb_info *fbi = par->info;
  633. struct fb_var_screeninfo *var = &info->var;
  634. unsigned long control;
  635. unsigned long reg;
  636. int ret;
  637. dev_dbg(fbi->dev, "%s(%p)\n", __func__, info);
  638. /* activate this new configuration */
  639. ret = sm501fb_set_par_common(info, var);
  640. if (ret)
  641. return ret;
  642. sm501fb_pan_pnl(var, info);
  643. sm501fb_set_par_geometry(info, var);
  644. /* update control register */
  645. control = smc501_readl(fbi->regs + SM501_DC_PANEL_CONTROL);
  646. control &= (SM501_DC_PANEL_CONTROL_GAMMA |
  647. SM501_DC_PANEL_CONTROL_VDD |
  648. SM501_DC_PANEL_CONTROL_DATA |
  649. SM501_DC_PANEL_CONTROL_BIAS |
  650. SM501_DC_PANEL_CONTROL_FPEN |
  651. SM501_DC_PANEL_CONTROL_CP |
  652. SM501_DC_PANEL_CONTROL_CK |
  653. SM501_DC_PANEL_CONTROL_HP |
  654. SM501_DC_PANEL_CONTROL_VP |
  655. SM501_DC_PANEL_CONTROL_HPD |
  656. SM501_DC_PANEL_CONTROL_VPD);
  657. control |= SM501_FIFO_3; /* fill if >3 free slots */
  658. switch(var->bits_per_pixel) {
  659. case 8:
  660. control |= SM501_DC_PANEL_CONTROL_8BPP;
  661. break;
  662. case 16:
  663. control |= SM501_DC_PANEL_CONTROL_16BPP;
  664. sm501fb_setup_gamma(fbi, SM501_DC_PANEL_PALETTE);
  665. break;
  666. case 32:
  667. control |= SM501_DC_PANEL_CONTROL_32BPP;
  668. sm501fb_setup_gamma(fbi, SM501_DC_PANEL_PALETTE);
  669. break;
  670. default:
  671. BUG();
  672. }
  673. smc501_writel(0x0, fbi->regs + SM501_DC_PANEL_PANNING_CONTROL);
  674. /* panel plane top left and bottom right location */
  675. smc501_writel(0x00, fbi->regs + SM501_DC_PANEL_TL_LOC);
  676. reg = var->xres - 1;
  677. reg |= (var->yres - 1) << 16;
  678. smc501_writel(reg, fbi->regs + SM501_DC_PANEL_BR_LOC);
  679. /* program panel control register */
  680. control |= SM501_DC_PANEL_CONTROL_TE; /* enable PANEL timing */
  681. control |= SM501_DC_PANEL_CONTROL_EN; /* enable PANEL gfx plane */
  682. if ((var->sync & FB_SYNC_HOR_HIGH_ACT) == 0)
  683. control |= SM501_DC_PANEL_CONTROL_HSP;
  684. if ((var->sync & FB_SYNC_VERT_HIGH_ACT) == 0)
  685. control |= SM501_DC_PANEL_CONTROL_VSP;
  686. smc501_writel(control, fbi->regs + SM501_DC_PANEL_CONTROL);
  687. sm501fb_sync_regs(fbi);
  688. /* ensure the panel interface is not tristated at this point */
  689. sm501_modify_reg(fbi->dev->parent, SM501_SYSTEM_CONTROL,
  690. 0, SM501_SYSCTRL_PANEL_TRISTATE);
  691. /* power the panel up */
  692. sm501fb_panel_power(fbi, 1);
  693. return 0;
  694. }
  695. /* chan_to_field
  696. *
  697. * convert a colour value into a field position
  698. *
  699. * from pxafb.c
  700. */
  701. static inline unsigned int chan_to_field(unsigned int chan,
  702. struct fb_bitfield *bf)
  703. {
  704. chan &= 0xffff;
  705. chan >>= 16 - bf->length;
  706. return chan << bf->offset;
  707. }
  708. /* sm501fb_setcolreg
  709. *
  710. * set the colour mapping for modes that support palettised data
  711. */
  712. static int sm501fb_setcolreg(unsigned regno,
  713. unsigned red, unsigned green, unsigned blue,
  714. unsigned transp, struct fb_info *info)
  715. {
  716. struct sm501fb_par *par = info->par;
  717. struct sm501fb_info *fbi = par->info;
  718. void __iomem *base = fbi->regs;
  719. unsigned int val;
  720. if (par->head == HEAD_CRT)
  721. base += SM501_DC_CRT_PALETTE;
  722. else
  723. base += SM501_DC_PANEL_PALETTE;
  724. switch (info->fix.visual) {
  725. case FB_VISUAL_TRUECOLOR:
  726. /* true-colour, use pseuo-palette */
  727. if (regno < 16) {
  728. u32 *pal = par->pseudo_palette;
  729. val = chan_to_field(red, &info->var.red);
  730. val |= chan_to_field(green, &info->var.green);
  731. val |= chan_to_field(blue, &info->var.blue);
  732. pal[regno] = val;
  733. }
  734. break;
  735. case FB_VISUAL_PSEUDOCOLOR:
  736. if (regno < 256) {
  737. val = (red >> 8) << 16;
  738. val |= (green >> 8) << 8;
  739. val |= blue >> 8;
  740. smc501_writel(val, base + (regno * 4));
  741. }
  742. break;
  743. default:
  744. return 1; /* unknown type */
  745. }
  746. return 0;
  747. }
  748. /* sm501fb_blank_pnl
  749. *
  750. * Blank or un-blank the panel interface
  751. */
  752. static int sm501fb_blank_pnl(int blank_mode, struct fb_info *info)
  753. {
  754. struct sm501fb_par *par = info->par;
  755. struct sm501fb_info *fbi = par->info;
  756. dev_dbg(fbi->dev, "%s(mode=%d, %p)\n", __func__, blank_mode, info);
  757. switch (blank_mode) {
  758. case FB_BLANK_POWERDOWN:
  759. sm501fb_panel_power(fbi, 0);
  760. break;
  761. case FB_BLANK_UNBLANK:
  762. sm501fb_panel_power(fbi, 1);
  763. break;
  764. case FB_BLANK_NORMAL:
  765. case FB_BLANK_VSYNC_SUSPEND:
  766. case FB_BLANK_HSYNC_SUSPEND:
  767. default:
  768. return 1;
  769. }
  770. return 0;
  771. }
  772. /* sm501fb_blank_crt
  773. *
  774. * Blank or un-blank the crt interface
  775. */
  776. static int sm501fb_blank_crt(int blank_mode, struct fb_info *info)
  777. {
  778. struct sm501fb_par *par = info->par;
  779. struct sm501fb_info *fbi = par->info;
  780. unsigned long ctrl;
  781. dev_dbg(fbi->dev, "%s(mode=%d, %p)\n", __func__, blank_mode, info);
  782. ctrl = smc501_readl(fbi->regs + SM501_DC_CRT_CONTROL);
  783. switch (blank_mode) {
  784. case FB_BLANK_POWERDOWN:
  785. ctrl &= ~SM501_DC_CRT_CONTROL_ENABLE;
  786. sm501_misc_control(fbi->dev->parent, SM501_MISC_DAC_POWER, 0);
  787. fallthrough;
  788. case FB_BLANK_NORMAL:
  789. ctrl |= SM501_DC_CRT_CONTROL_BLANK;
  790. break;
  791. case FB_BLANK_UNBLANK:
  792. ctrl &= ~SM501_DC_CRT_CONTROL_BLANK;
  793. ctrl |= SM501_DC_CRT_CONTROL_ENABLE;
  794. sm501_misc_control(fbi->dev->parent, 0, SM501_MISC_DAC_POWER);
  795. break;
  796. case FB_BLANK_VSYNC_SUSPEND:
  797. case FB_BLANK_HSYNC_SUSPEND:
  798. default:
  799. return 1;
  800. }
  801. smc501_writel(ctrl, fbi->regs + SM501_DC_CRT_CONTROL);
  802. sm501fb_sync_regs(fbi);
  803. return 0;
  804. }
  805. /* sm501fb_cursor
  806. *
  807. * set or change the hardware cursor parameters
  808. */
  809. static int sm501fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
  810. {
  811. struct sm501fb_par *par = info->par;
  812. struct sm501fb_info *fbi = par->info;
  813. void __iomem *base = fbi->regs;
  814. unsigned long hwc_addr;
  815. unsigned long fg, bg;
  816. dev_dbg(fbi->dev, "%s(%p,%p)\n", __func__, info, cursor);
  817. if (par->head == HEAD_CRT)
  818. base += SM501_DC_CRT_HWC_BASE;
  819. else
  820. base += SM501_DC_PANEL_HWC_BASE;
  821. /* check not being asked to exceed capabilities */
  822. if (cursor->image.width > 64)
  823. return -EINVAL;
  824. if (cursor->image.height > 64)
  825. return -EINVAL;
  826. if (cursor->image.depth > 1)
  827. return -EINVAL;
  828. hwc_addr = smc501_readl(base + SM501_OFF_HWC_ADDR);
  829. if (cursor->enable)
  830. smc501_writel(hwc_addr | SM501_HWC_EN,
  831. base + SM501_OFF_HWC_ADDR);
  832. else
  833. smc501_writel(hwc_addr & ~SM501_HWC_EN,
  834. base + SM501_OFF_HWC_ADDR);
  835. /* set data */
  836. if (cursor->set & FB_CUR_SETPOS) {
  837. unsigned int x = cursor->image.dx;
  838. unsigned int y = cursor->image.dy;
  839. if (x >= 2048 || y >= 2048 )
  840. return -EINVAL;
  841. dev_dbg(fbi->dev, "set position %d,%d\n", x, y);
  842. //y += cursor->image.height;
  843. smc501_writel(x | (y << 16), base + SM501_OFF_HWC_LOC);
  844. }
  845. if (cursor->set & FB_CUR_SETCMAP) {
  846. unsigned int bg_col = cursor->image.bg_color;
  847. unsigned int fg_col = cursor->image.fg_color;
  848. dev_dbg(fbi->dev, "%s: update cmap (%08x,%08x)\n",
  849. __func__, bg_col, fg_col);
  850. bg = ((info->cmap.red[bg_col] & 0xF8) << 8) |
  851. ((info->cmap.green[bg_col] & 0xFC) << 3) |
  852. ((info->cmap.blue[bg_col] & 0xF8) >> 3);
  853. fg = ((info->cmap.red[fg_col] & 0xF8) << 8) |
  854. ((info->cmap.green[fg_col] & 0xFC) << 3) |
  855. ((info->cmap.blue[fg_col] & 0xF8) >> 3);
  856. dev_dbg(fbi->dev, "fgcol %08lx, bgcol %08lx\n", fg, bg);
  857. smc501_writel(bg, base + SM501_OFF_HWC_COLOR_1_2);
  858. smc501_writel(fg, base + SM501_OFF_HWC_COLOR_3);
  859. }
  860. if (cursor->set & FB_CUR_SETSIZE ||
  861. cursor->set & (FB_CUR_SETIMAGE | FB_CUR_SETSHAPE)) {
  862. /* SM501 cursor is a two bpp 64x64 bitmap this routine
  863. * clears it to transparent then combines the cursor
  864. * shape plane with the colour plane to set the
  865. * cursor */
  866. int x, y;
  867. const unsigned char *pcol = cursor->image.data;
  868. const unsigned char *pmsk = cursor->mask;
  869. void __iomem *dst = par->cursor.k_addr;
  870. unsigned char dcol = 0;
  871. unsigned char dmsk = 0;
  872. unsigned int op;
  873. dev_dbg(fbi->dev, "%s: setting shape (%d,%d)\n",
  874. __func__, cursor->image.width, cursor->image.height);
  875. for (op = 0; op < (64*64*2)/8; op+=4)
  876. smc501_writel(0x0, dst + op);
  877. for (y = 0; y < cursor->image.height; y++) {
  878. for (x = 0; x < cursor->image.width; x++) {
  879. if ((x % 8) == 0) {
  880. dcol = *pcol++;
  881. dmsk = *pmsk++;
  882. } else {
  883. dcol >>= 1;
  884. dmsk >>= 1;
  885. }
  886. if (dmsk & 1) {
  887. op = (dcol & 1) ? 1 : 3;
  888. op <<= ((x % 4) * 2);
  889. op |= readb(dst + (x / 4));
  890. writeb(op, dst + (x / 4));
  891. }
  892. }
  893. dst += (64*2)/8;
  894. }
  895. }
  896. sm501fb_sync_regs(fbi); /* ensure cursor data flushed */
  897. return 0;
  898. }
  899. /* sm501fb_crtsrc_show
  900. *
  901. * device attribute code to show where the crt output is sourced from
  902. */
  903. static ssize_t sm501fb_crtsrc_show(struct device *dev,
  904. struct device_attribute *attr, char *buf)
  905. {
  906. struct sm501fb_info *info = dev_get_drvdata(dev);
  907. unsigned long ctrl;
  908. ctrl = smc501_readl(info->regs + SM501_DC_CRT_CONTROL);
  909. ctrl &= SM501_DC_CRT_CONTROL_SEL;
  910. return sysfs_emit(buf, "%s\n", ctrl ? "crt" : "panel");
  911. }
  912. /* sm501fb_crtsrc_show
  913. *
  914. * device attribute code to set where the crt output is sourced from
  915. */
  916. static ssize_t sm501fb_crtsrc_store(struct device *dev,
  917. struct device_attribute *attr,
  918. const char *buf, size_t len)
  919. {
  920. struct sm501fb_info *info = dev_get_drvdata(dev);
  921. enum sm501_controller head;
  922. unsigned long ctrl;
  923. if (len < 1)
  924. return -EINVAL;
  925. if (strncasecmp(buf, "crt", 3) == 0)
  926. head = HEAD_CRT;
  927. else if (strncasecmp(buf, "panel", 5) == 0)
  928. head = HEAD_PANEL;
  929. else
  930. return -EINVAL;
  931. dev_info(dev, "setting crt source to head %d\n", head);
  932. ctrl = smc501_readl(info->regs + SM501_DC_CRT_CONTROL);
  933. if (head == HEAD_CRT) {
  934. ctrl |= SM501_DC_CRT_CONTROL_SEL;
  935. ctrl |= SM501_DC_CRT_CONTROL_ENABLE;
  936. ctrl |= SM501_DC_CRT_CONTROL_TE;
  937. } else {
  938. ctrl &= ~SM501_DC_CRT_CONTROL_SEL;
  939. ctrl &= ~SM501_DC_CRT_CONTROL_ENABLE;
  940. ctrl &= ~SM501_DC_CRT_CONTROL_TE;
  941. }
  942. smc501_writel(ctrl, info->regs + SM501_DC_CRT_CONTROL);
  943. sm501fb_sync_regs(info);
  944. return len;
  945. }
  946. /* Prepare the device_attr for registration with sysfs later */
  947. static DEVICE_ATTR(crt_src, 0664, sm501fb_crtsrc_show, sm501fb_crtsrc_store);
  948. /* sm501fb_show_regs
  949. *
  950. * show the primary sm501 registers
  951. */
  952. static int sm501fb_show_regs(struct sm501fb_info *info, char *ptr,
  953. unsigned int start, unsigned int len)
  954. {
  955. void __iomem *mem = info->regs;
  956. char *buf = ptr;
  957. unsigned int reg;
  958. for (reg = start; reg < (len + start); reg += 4)
  959. ptr += sprintf(ptr, "%08x = %08x\n", reg,
  960. smc501_readl(mem + reg));
  961. return ptr - buf;
  962. }
  963. /* sm501fb_debug_show_crt
  964. *
  965. * show the crt control and cursor registers
  966. */
  967. static ssize_t sm501fb_debug_show_crt(struct device *dev,
  968. struct device_attribute *attr, char *buf)
  969. {
  970. struct sm501fb_info *info = dev_get_drvdata(dev);
  971. char *ptr = buf;
  972. ptr += sm501fb_show_regs(info, ptr, SM501_DC_CRT_CONTROL, 0x40);
  973. ptr += sm501fb_show_regs(info, ptr, SM501_DC_CRT_HWC_BASE, 0x10);
  974. return ptr - buf;
  975. }
  976. static DEVICE_ATTR(fbregs_crt, 0444, sm501fb_debug_show_crt, NULL);
  977. /* sm501fb_debug_show_pnl
  978. *
  979. * show the panel control and cursor registers
  980. */
  981. static ssize_t sm501fb_debug_show_pnl(struct device *dev,
  982. struct device_attribute *attr, char *buf)
  983. {
  984. struct sm501fb_info *info = dev_get_drvdata(dev);
  985. char *ptr = buf;
  986. ptr += sm501fb_show_regs(info, ptr, 0x0, 0x40);
  987. ptr += sm501fb_show_regs(info, ptr, SM501_DC_PANEL_HWC_BASE, 0x10);
  988. return ptr - buf;
  989. }
  990. static DEVICE_ATTR(fbregs_pnl, 0444, sm501fb_debug_show_pnl, NULL);
  991. static struct attribute *sm501fb_attrs[] = {
  992. &dev_attr_crt_src.attr,
  993. &dev_attr_fbregs_pnl.attr,
  994. &dev_attr_fbregs_crt.attr,
  995. NULL,
  996. };
  997. ATTRIBUTE_GROUPS(sm501fb);
  998. /* acceleration operations */
  999. static int sm501fb_sync(struct fb_info *info)
  1000. {
  1001. int count = 1000000;
  1002. struct sm501fb_par *par = info->par;
  1003. struct sm501fb_info *fbi = par->info;
  1004. /* wait for the 2d engine to be ready */
  1005. while ((count > 0) &&
  1006. (smc501_readl(fbi->regs + SM501_SYSTEM_CONTROL) &
  1007. SM501_SYSCTRL_2D_ENGINE_STATUS) != 0)
  1008. count--;
  1009. if (count <= 0) {
  1010. dev_err(info->dev, "Timeout waiting for 2d engine sync\n");
  1011. return 1;
  1012. }
  1013. return 0;
  1014. }
  1015. static void sm501fb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
  1016. {
  1017. struct sm501fb_par *par = info->par;
  1018. struct sm501fb_info *fbi = par->info;
  1019. int width = area->width;
  1020. int height = area->height;
  1021. int sx = area->sx;
  1022. int sy = area->sy;
  1023. int dx = area->dx;
  1024. int dy = area->dy;
  1025. unsigned long rtl = 0;
  1026. /* source clip */
  1027. if ((sx >= info->var.xres_virtual) ||
  1028. (sy >= info->var.yres_virtual))
  1029. /* source Area not within virtual screen, skipping */
  1030. return;
  1031. if ((sx + width) >= info->var.xres_virtual)
  1032. width = info->var.xres_virtual - sx - 1;
  1033. if ((sy + height) >= info->var.yres_virtual)
  1034. height = info->var.yres_virtual - sy - 1;
  1035. /* dest clip */
  1036. if ((dx >= info->var.xres_virtual) ||
  1037. (dy >= info->var.yres_virtual))
  1038. /* Destination Area not within virtual screen, skipping */
  1039. return;
  1040. if ((dx + width) >= info->var.xres_virtual)
  1041. width = info->var.xres_virtual - dx - 1;
  1042. if ((dy + height) >= info->var.yres_virtual)
  1043. height = info->var.yres_virtual - dy - 1;
  1044. if ((sx < dx) || (sy < dy)) {
  1045. rtl = 1 << 27;
  1046. sx += width - 1;
  1047. dx += width - 1;
  1048. sy += height - 1;
  1049. dy += height - 1;
  1050. }
  1051. if (sm501fb_sync(info))
  1052. return;
  1053. /* set the base addresses */
  1054. smc501_writel(par->screen.sm_addr, fbi->regs2d + SM501_2D_SOURCE_BASE);
  1055. smc501_writel(par->screen.sm_addr,
  1056. fbi->regs2d + SM501_2D_DESTINATION_BASE);
  1057. /* set the window width */
  1058. smc501_writel((info->var.xres << 16) | info->var.xres,
  1059. fbi->regs2d + SM501_2D_WINDOW_WIDTH);
  1060. /* set window stride */
  1061. smc501_writel((info->var.xres_virtual << 16) | info->var.xres_virtual,
  1062. fbi->regs2d + SM501_2D_PITCH);
  1063. /* set data format */
  1064. switch (info->var.bits_per_pixel) {
  1065. case 8:
  1066. smc501_writel(0, fbi->regs2d + SM501_2D_STRETCH);
  1067. break;
  1068. case 16:
  1069. smc501_writel(0x00100000, fbi->regs2d + SM501_2D_STRETCH);
  1070. break;
  1071. case 32:
  1072. smc501_writel(0x00200000, fbi->regs2d + SM501_2D_STRETCH);
  1073. break;
  1074. }
  1075. /* 2d compare mask */
  1076. smc501_writel(0xffffffff, fbi->regs2d + SM501_2D_COLOR_COMPARE_MASK);
  1077. /* 2d mask */
  1078. smc501_writel(0xffffffff, fbi->regs2d + SM501_2D_MASK);
  1079. /* source and destination x y */
  1080. smc501_writel((sx << 16) | sy, fbi->regs2d + SM501_2D_SOURCE);
  1081. smc501_writel((dx << 16) | dy, fbi->regs2d + SM501_2D_DESTINATION);
  1082. /* w/h */
  1083. smc501_writel((width << 16) | height, fbi->regs2d + SM501_2D_DIMENSION);
  1084. /* do area move */
  1085. smc501_writel(0x800000cc | rtl, fbi->regs2d + SM501_2D_CONTROL);
  1086. }
  1087. static void sm501fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
  1088. {
  1089. struct sm501fb_par *par = info->par;
  1090. struct sm501fb_info *fbi = par->info;
  1091. int width = rect->width, height = rect->height;
  1092. if ((rect->dx >= info->var.xres_virtual) ||
  1093. (rect->dy >= info->var.yres_virtual))
  1094. /* Rectangle not within virtual screen, skipping */
  1095. return;
  1096. if ((rect->dx + width) >= info->var.xres_virtual)
  1097. width = info->var.xres_virtual - rect->dx - 1;
  1098. if ((rect->dy + height) >= info->var.yres_virtual)
  1099. height = info->var.yres_virtual - rect->dy - 1;
  1100. if (sm501fb_sync(info))
  1101. return;
  1102. /* set the base addresses */
  1103. smc501_writel(par->screen.sm_addr, fbi->regs2d + SM501_2D_SOURCE_BASE);
  1104. smc501_writel(par->screen.sm_addr,
  1105. fbi->regs2d + SM501_2D_DESTINATION_BASE);
  1106. /* set the window width */
  1107. smc501_writel((info->var.xres << 16) | info->var.xres,
  1108. fbi->regs2d + SM501_2D_WINDOW_WIDTH);
  1109. /* set window stride */
  1110. smc501_writel((info->var.xres_virtual << 16) | info->var.xres_virtual,
  1111. fbi->regs2d + SM501_2D_PITCH);
  1112. /* set data format */
  1113. switch (info->var.bits_per_pixel) {
  1114. case 8:
  1115. smc501_writel(0, fbi->regs2d + SM501_2D_STRETCH);
  1116. break;
  1117. case 16:
  1118. smc501_writel(0x00100000, fbi->regs2d + SM501_2D_STRETCH);
  1119. break;
  1120. case 32:
  1121. smc501_writel(0x00200000, fbi->regs2d + SM501_2D_STRETCH);
  1122. break;
  1123. }
  1124. /* 2d compare mask */
  1125. smc501_writel(0xffffffff, fbi->regs2d + SM501_2D_COLOR_COMPARE_MASK);
  1126. /* 2d mask */
  1127. smc501_writel(0xffffffff, fbi->regs2d + SM501_2D_MASK);
  1128. /* colour */
  1129. smc501_writel(rect->color, fbi->regs2d + SM501_2D_FOREGROUND);
  1130. /* x y */
  1131. smc501_writel((rect->dx << 16) | rect->dy,
  1132. fbi->regs2d + SM501_2D_DESTINATION);
  1133. /* w/h */
  1134. smc501_writel((width << 16) | height, fbi->regs2d + SM501_2D_DIMENSION);
  1135. /* do rectangle fill */
  1136. smc501_writel(0x800100cc, fbi->regs2d + SM501_2D_CONTROL);
  1137. }
  1138. static struct fb_ops sm501fb_ops_crt = {
  1139. .owner = THIS_MODULE,
  1140. .fb_check_var = sm501fb_check_var_crt,
  1141. .fb_set_par = sm501fb_set_par_crt,
  1142. .fb_blank = sm501fb_blank_crt,
  1143. .fb_setcolreg = sm501fb_setcolreg,
  1144. .fb_pan_display = sm501fb_pan_crt,
  1145. .fb_cursor = sm501fb_cursor,
  1146. .fb_fillrect = sm501fb_fillrect,
  1147. .fb_copyarea = sm501fb_copyarea,
  1148. .fb_imageblit = cfb_imageblit,
  1149. .fb_sync = sm501fb_sync,
  1150. };
  1151. static struct fb_ops sm501fb_ops_pnl = {
  1152. .owner = THIS_MODULE,
  1153. .fb_check_var = sm501fb_check_var_pnl,
  1154. .fb_set_par = sm501fb_set_par_pnl,
  1155. .fb_pan_display = sm501fb_pan_pnl,
  1156. .fb_blank = sm501fb_blank_pnl,
  1157. .fb_setcolreg = sm501fb_setcolreg,
  1158. .fb_cursor = sm501fb_cursor,
  1159. .fb_fillrect = sm501fb_fillrect,
  1160. .fb_copyarea = sm501fb_copyarea,
  1161. .fb_imageblit = cfb_imageblit,
  1162. .fb_sync = sm501fb_sync,
  1163. };
  1164. /* sm501_init_cursor
  1165. *
  1166. * initialise hw cursor parameters
  1167. */
  1168. static int sm501_init_cursor(struct fb_info *fbi, unsigned int reg_base)
  1169. {
  1170. struct sm501fb_par *par;
  1171. struct sm501fb_info *info;
  1172. int ret;
  1173. if (fbi == NULL)
  1174. return 0;
  1175. par = fbi->par;
  1176. info = par->info;
  1177. par->cursor_regs = info->regs + reg_base;
  1178. ret = sm501_alloc_mem(info, &par->cursor, SM501_MEMF_CURSOR, 1024,
  1179. fbi->fix.smem_len);
  1180. if (ret < 0)
  1181. return ret;
  1182. /* initialise the colour registers */
  1183. smc501_writel(par->cursor.sm_addr,
  1184. par->cursor_regs + SM501_OFF_HWC_ADDR);
  1185. smc501_writel(0x00, par->cursor_regs + SM501_OFF_HWC_LOC);
  1186. smc501_writel(0x00, par->cursor_regs + SM501_OFF_HWC_COLOR_1_2);
  1187. smc501_writel(0x00, par->cursor_regs + SM501_OFF_HWC_COLOR_3);
  1188. sm501fb_sync_regs(info);
  1189. return 0;
  1190. }
  1191. /* sm501fb_info_start
  1192. *
  1193. * fills the par structure claiming resources and remapping etc.
  1194. */
  1195. static int sm501fb_start(struct sm501fb_info *info,
  1196. struct platform_device *pdev)
  1197. {
  1198. struct resource *res;
  1199. struct device *dev = &pdev->dev;
  1200. int k;
  1201. int ret;
  1202. info->irq = ret = platform_get_irq(pdev, 0);
  1203. if (ret < 0) {
  1204. /* we currently do not use the IRQ */
  1205. dev_warn(dev, "no irq for device\n");
  1206. }
  1207. /* allocate, reserve and remap resources for display
  1208. * controller registers */
  1209. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1210. if (res == NULL) {
  1211. dev_err(dev, "no resource definition for registers\n");
  1212. ret = -ENOENT;
  1213. goto err_release;
  1214. }
  1215. info->regs_res = request_mem_region(res->start,
  1216. resource_size(res),
  1217. pdev->name);
  1218. if (info->regs_res == NULL) {
  1219. dev_err(dev, "cannot claim registers\n");
  1220. ret = -ENXIO;
  1221. goto err_release;
  1222. }
  1223. info->regs = ioremap(res->start, resource_size(res));
  1224. if (info->regs == NULL) {
  1225. dev_err(dev, "cannot remap registers\n");
  1226. ret = -ENXIO;
  1227. goto err_regs_res;
  1228. }
  1229. /* allocate, reserve and remap resources for 2d
  1230. * controller registers */
  1231. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  1232. if (res == NULL) {
  1233. dev_err(dev, "no resource definition for 2d registers\n");
  1234. ret = -ENOENT;
  1235. goto err_regs_map;
  1236. }
  1237. info->regs2d_res = request_mem_region(res->start,
  1238. resource_size(res),
  1239. pdev->name);
  1240. if (info->regs2d_res == NULL) {
  1241. dev_err(dev, "cannot claim registers\n");
  1242. ret = -ENXIO;
  1243. goto err_regs_map;
  1244. }
  1245. info->regs2d = ioremap(res->start, resource_size(res));
  1246. if (info->regs2d == NULL) {
  1247. dev_err(dev, "cannot remap registers\n");
  1248. ret = -ENXIO;
  1249. goto err_regs2d_res;
  1250. }
  1251. /* allocate, reserve resources for framebuffer */
  1252. res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
  1253. if (res == NULL) {
  1254. dev_err(dev, "no memory resource defined\n");
  1255. ret = -ENXIO;
  1256. goto err_regs2d_map;
  1257. }
  1258. info->fbmem_res = request_mem_region(res->start,
  1259. resource_size(res),
  1260. pdev->name);
  1261. if (info->fbmem_res == NULL) {
  1262. dev_err(dev, "cannot claim framebuffer\n");
  1263. ret = -ENXIO;
  1264. goto err_regs2d_map;
  1265. }
  1266. info->fbmem = ioremap(res->start, resource_size(res));
  1267. if (info->fbmem == NULL) {
  1268. dev_err(dev, "cannot remap framebuffer\n");
  1269. ret = -ENXIO;
  1270. goto err_mem_res;
  1271. }
  1272. info->fbmem_len = resource_size(res);
  1273. /* clear framebuffer memory - avoids garbage data on unused fb */
  1274. memset_io(info->fbmem, 0, info->fbmem_len);
  1275. /* clear palette ram - undefined at power on */
  1276. for (k = 0; k < (256 * 3); k++)
  1277. smc501_writel(0, info->regs + SM501_DC_PANEL_PALETTE + (k * 4));
  1278. /* enable display controller */
  1279. sm501_unit_power(dev->parent, SM501_GATE_DISPLAY, 1);
  1280. /* enable 2d controller */
  1281. sm501_unit_power(dev->parent, SM501_GATE_2D_ENGINE, 1);
  1282. /* setup cursors */
  1283. sm501_init_cursor(info->fb[HEAD_CRT], SM501_DC_CRT_HWC_ADDR);
  1284. sm501_init_cursor(info->fb[HEAD_PANEL], SM501_DC_PANEL_HWC_ADDR);
  1285. return 0; /* everything is setup */
  1286. err_mem_res:
  1287. release_mem_region(info->fbmem_res->start,
  1288. resource_size(info->fbmem_res));
  1289. err_regs2d_map:
  1290. iounmap(info->regs2d);
  1291. err_regs2d_res:
  1292. release_mem_region(info->regs2d_res->start,
  1293. resource_size(info->regs2d_res));
  1294. err_regs_map:
  1295. iounmap(info->regs);
  1296. err_regs_res:
  1297. release_mem_region(info->regs_res->start,
  1298. resource_size(info->regs_res));
  1299. err_release:
  1300. return ret;
  1301. }
  1302. static void sm501fb_stop(struct sm501fb_info *info)
  1303. {
  1304. /* disable display controller */
  1305. sm501_unit_power(info->dev->parent, SM501_GATE_DISPLAY, 0);
  1306. iounmap(info->fbmem);
  1307. release_mem_region(info->fbmem_res->start,
  1308. resource_size(info->fbmem_res));
  1309. iounmap(info->regs2d);
  1310. release_mem_region(info->regs2d_res->start,
  1311. resource_size(info->regs2d_res));
  1312. iounmap(info->regs);
  1313. release_mem_region(info->regs_res->start,
  1314. resource_size(info->regs_res));
  1315. }
  1316. static int sm501fb_init_fb(struct fb_info *fb, enum sm501_controller head,
  1317. const char *fbname)
  1318. {
  1319. struct sm501_platdata_fbsub *pd;
  1320. struct sm501fb_par *par = fb->par;
  1321. struct sm501fb_info *info = par->info;
  1322. unsigned long ctrl;
  1323. unsigned int enable;
  1324. int ret;
  1325. switch (head) {
  1326. case HEAD_CRT:
  1327. pd = info->pdata->fb_crt;
  1328. ctrl = smc501_readl(info->regs + SM501_DC_CRT_CONTROL);
  1329. enable = (ctrl & SM501_DC_CRT_CONTROL_ENABLE) ? 1 : 0;
  1330. /* ensure we set the correct source register */
  1331. if (info->pdata->fb_route != SM501_FB_CRT_PANEL) {
  1332. ctrl |= SM501_DC_CRT_CONTROL_SEL;
  1333. smc501_writel(ctrl, info->regs + SM501_DC_CRT_CONTROL);
  1334. }
  1335. break;
  1336. case HEAD_PANEL:
  1337. pd = info->pdata->fb_pnl;
  1338. ctrl = smc501_readl(info->regs + SM501_DC_PANEL_CONTROL);
  1339. enable = (ctrl & SM501_DC_PANEL_CONTROL_EN) ? 1 : 0;
  1340. break;
  1341. default:
  1342. pd = NULL; /* stop compiler warnings */
  1343. ctrl = 0;
  1344. enable = 0;
  1345. BUG();
  1346. }
  1347. dev_info(info->dev, "fb %s %sabled at start\n",
  1348. fbname, enable ? "en" : "dis");
  1349. /* check to see if our routing allows this */
  1350. if (head == HEAD_CRT && info->pdata->fb_route == SM501_FB_CRT_PANEL) {
  1351. ctrl &= ~SM501_DC_CRT_CONTROL_SEL;
  1352. smc501_writel(ctrl, info->regs + SM501_DC_CRT_CONTROL);
  1353. enable = 0;
  1354. }
  1355. strscpy(fb->fix.id, fbname, sizeof(fb->fix.id));
  1356. memcpy(&par->ops,
  1357. (head == HEAD_CRT) ? &sm501fb_ops_crt : &sm501fb_ops_pnl,
  1358. sizeof(struct fb_ops));
  1359. /* update ops dependent on what we've been passed */
  1360. if ((pd->flags & SM501FB_FLAG_USE_HWCURSOR) == 0)
  1361. par->ops.fb_cursor = NULL;
  1362. fb->fbops = &par->ops;
  1363. fb->flags = FBINFO_FLAG_DEFAULT | FBINFO_READS_FAST |
  1364. FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT |
  1365. FBINFO_HWACCEL_XPAN | FBINFO_HWACCEL_YPAN;
  1366. #if defined(CONFIG_OF)
  1367. #ifdef __BIG_ENDIAN
  1368. if (of_get_property(info->dev->parent->of_node, "little-endian", NULL))
  1369. fb->flags |= FBINFO_FOREIGN_ENDIAN;
  1370. #else
  1371. if (of_get_property(info->dev->parent->of_node, "big-endian", NULL))
  1372. fb->flags |= FBINFO_FOREIGN_ENDIAN;
  1373. #endif
  1374. #endif
  1375. /* fixed data */
  1376. fb->fix.type = FB_TYPE_PACKED_PIXELS;
  1377. fb->fix.type_aux = 0;
  1378. fb->fix.xpanstep = 1;
  1379. fb->fix.ypanstep = 1;
  1380. fb->fix.ywrapstep = 0;
  1381. fb->fix.accel = FB_ACCEL_NONE;
  1382. /* screenmode */
  1383. fb->var.nonstd = 0;
  1384. fb->var.activate = FB_ACTIVATE_NOW;
  1385. fb->var.accel_flags = 0;
  1386. fb->var.vmode = FB_VMODE_NONINTERLACED;
  1387. fb->var.bits_per_pixel = 16;
  1388. if (info->edid_data) {
  1389. /* Now build modedb from EDID */
  1390. fb_edid_to_monspecs(info->edid_data, &fb->monspecs);
  1391. fb_videomode_to_modelist(fb->monspecs.modedb,
  1392. fb->monspecs.modedb_len,
  1393. &fb->modelist);
  1394. }
  1395. if (enable && (pd->flags & SM501FB_FLAG_USE_INIT_MODE) && 0) {
  1396. /* TODO read the mode from the current display */
  1397. } else {
  1398. if (pd->def_mode) {
  1399. dev_info(info->dev, "using supplied mode\n");
  1400. fb_videomode_to_var(&fb->var, pd->def_mode);
  1401. fb->var.bits_per_pixel = pd->def_bpp ? pd->def_bpp : 8;
  1402. fb->var.xres_virtual = fb->var.xres;
  1403. fb->var.yres_virtual = fb->var.yres;
  1404. } else {
  1405. if (info->edid_data) {
  1406. ret = fb_find_mode(&fb->var, fb, fb_mode,
  1407. fb->monspecs.modedb,
  1408. fb->monspecs.modedb_len,
  1409. &sm501_default_mode, default_bpp);
  1410. /* edid_data is no longer needed, free it */
  1411. kfree(info->edid_data);
  1412. } else {
  1413. ret = fb_find_mode(&fb->var, fb,
  1414. NULL, NULL, 0, NULL, 8);
  1415. }
  1416. switch (ret) {
  1417. case 1:
  1418. dev_info(info->dev, "using mode specified in "
  1419. "@mode\n");
  1420. break;
  1421. case 2:
  1422. dev_info(info->dev, "using mode specified in "
  1423. "@mode with ignored refresh rate\n");
  1424. break;
  1425. case 3:
  1426. dev_info(info->dev, "using mode default "
  1427. "mode\n");
  1428. break;
  1429. case 4:
  1430. dev_info(info->dev, "using mode from list\n");
  1431. break;
  1432. default:
  1433. dev_info(info->dev, "ret = %d\n", ret);
  1434. dev_info(info->dev, "failed to find mode\n");
  1435. return -EINVAL;
  1436. }
  1437. }
  1438. }
  1439. /* initialise and set the palette */
  1440. if (fb_alloc_cmap(&fb->cmap, NR_PALETTE, 0)) {
  1441. dev_err(info->dev, "failed to allocate cmap memory\n");
  1442. return -ENOMEM;
  1443. }
  1444. fb_set_cmap(&fb->cmap, fb);
  1445. ret = (fb->fbops->fb_check_var)(&fb->var, fb);
  1446. if (ret)
  1447. dev_err(info->dev, "check_var() failed on initial setup?\n");
  1448. return 0;
  1449. }
  1450. /* default platform data if none is supplied (ie, PCI device) */
  1451. static struct sm501_platdata_fbsub sm501fb_pdata_crt = {
  1452. .flags = (SM501FB_FLAG_USE_INIT_MODE |
  1453. SM501FB_FLAG_USE_HWCURSOR |
  1454. SM501FB_FLAG_USE_HWACCEL |
  1455. SM501FB_FLAG_DISABLE_AT_EXIT),
  1456. };
  1457. static struct sm501_platdata_fbsub sm501fb_pdata_pnl = {
  1458. .flags = (SM501FB_FLAG_USE_INIT_MODE |
  1459. SM501FB_FLAG_USE_HWCURSOR |
  1460. SM501FB_FLAG_USE_HWACCEL |
  1461. SM501FB_FLAG_DISABLE_AT_EXIT),
  1462. };
  1463. static struct sm501_platdata_fb sm501fb_def_pdata = {
  1464. .fb_route = SM501_FB_OWN,
  1465. .fb_crt = &sm501fb_pdata_crt,
  1466. .fb_pnl = &sm501fb_pdata_pnl,
  1467. };
  1468. static char driver_name_crt[] = "sm501fb-crt";
  1469. static char driver_name_pnl[] = "sm501fb-panel";
  1470. static int sm501fb_probe_one(struct sm501fb_info *info,
  1471. enum sm501_controller head)
  1472. {
  1473. unsigned char *name = (head == HEAD_CRT) ? "crt" : "panel";
  1474. struct sm501_platdata_fbsub *pd;
  1475. struct sm501fb_par *par;
  1476. struct fb_info *fbi;
  1477. pd = (head == HEAD_CRT) ? info->pdata->fb_crt : info->pdata->fb_pnl;
  1478. /* Do not initialise if we've not been given any platform data */
  1479. if (pd == NULL) {
  1480. dev_info(info->dev, "no data for fb %s (disabled)\n", name);
  1481. return 0;
  1482. }
  1483. fbi = framebuffer_alloc(sizeof(struct sm501fb_par), info->dev);
  1484. if (!fbi)
  1485. return -ENOMEM;
  1486. par = fbi->par;
  1487. par->info = info;
  1488. par->head = head;
  1489. fbi->pseudo_palette = &par->pseudo_palette;
  1490. info->fb[head] = fbi;
  1491. return 0;
  1492. }
  1493. /* Free up anything allocated by sm501fb_init_fb */
  1494. static void sm501_free_init_fb(struct sm501fb_info *info,
  1495. enum sm501_controller head)
  1496. {
  1497. struct fb_info *fbi = info->fb[head];
  1498. if (!fbi)
  1499. return;
  1500. fb_dealloc_cmap(&fbi->cmap);
  1501. }
  1502. static int sm501fb_start_one(struct sm501fb_info *info,
  1503. enum sm501_controller head, const char *drvname)
  1504. {
  1505. struct fb_info *fbi = info->fb[head];
  1506. int ret;
  1507. if (!fbi)
  1508. return 0;
  1509. mutex_init(&info->fb[head]->mm_lock);
  1510. ret = sm501fb_init_fb(info->fb[head], head, drvname);
  1511. if (ret) {
  1512. dev_err(info->dev, "cannot initialise fb %s\n", drvname);
  1513. return ret;
  1514. }
  1515. ret = register_framebuffer(info->fb[head]);
  1516. if (ret) {
  1517. dev_err(info->dev, "failed to register fb %s\n", drvname);
  1518. sm501_free_init_fb(info, head);
  1519. return ret;
  1520. }
  1521. dev_info(info->dev, "fb%d: %s frame buffer\n", fbi->node, fbi->fix.id);
  1522. return 0;
  1523. }
  1524. static int sm501fb_probe(struct platform_device *pdev)
  1525. {
  1526. struct sm501fb_info *info;
  1527. struct device *dev = &pdev->dev;
  1528. int ret;
  1529. /* allocate our framebuffers */
  1530. info = kzalloc(sizeof(*info), GFP_KERNEL);
  1531. if (!info) {
  1532. dev_err(dev, "failed to allocate state\n");
  1533. return -ENOMEM;
  1534. }
  1535. info->dev = dev = &pdev->dev;
  1536. platform_set_drvdata(pdev, info);
  1537. if (dev->parent->platform_data) {
  1538. struct sm501_platdata *pd = dev->parent->platform_data;
  1539. info->pdata = pd->fb;
  1540. }
  1541. if (info->pdata == NULL) {
  1542. int found = 0;
  1543. #if defined(CONFIG_OF)
  1544. struct device_node *np = pdev->dev.parent->of_node;
  1545. const u8 *prop;
  1546. const char *cp;
  1547. int len;
  1548. info->pdata = &sm501fb_def_pdata;
  1549. if (np) {
  1550. /* Get EDID */
  1551. cp = of_get_property(np, "mode", &len);
  1552. if (cp)
  1553. strcpy(fb_mode, cp);
  1554. prop = of_get_property(np, "edid", &len);
  1555. if (prop && len == EDID_LENGTH) {
  1556. info->edid_data = kmemdup(prop, EDID_LENGTH,
  1557. GFP_KERNEL);
  1558. if (info->edid_data)
  1559. found = 1;
  1560. }
  1561. }
  1562. #endif
  1563. if (!found) {
  1564. dev_info(dev, "using default configuration data\n");
  1565. info->pdata = &sm501fb_def_pdata;
  1566. }
  1567. }
  1568. /* probe for the presence of each panel */
  1569. ret = sm501fb_probe_one(info, HEAD_CRT);
  1570. if (ret < 0) {
  1571. dev_err(dev, "failed to probe CRT\n");
  1572. goto err_alloc;
  1573. }
  1574. ret = sm501fb_probe_one(info, HEAD_PANEL);
  1575. if (ret < 0) {
  1576. dev_err(dev, "failed to probe PANEL\n");
  1577. goto err_probed_crt;
  1578. }
  1579. if (info->fb[HEAD_PANEL] == NULL &&
  1580. info->fb[HEAD_CRT] == NULL) {
  1581. dev_err(dev, "no framebuffers found\n");
  1582. ret = -ENODEV;
  1583. goto err_alloc;
  1584. }
  1585. /* get the resources for both of the framebuffers */
  1586. ret = sm501fb_start(info, pdev);
  1587. if (ret) {
  1588. dev_err(dev, "cannot initialise SM501\n");
  1589. goto err_probed_panel;
  1590. }
  1591. ret = sm501fb_start_one(info, HEAD_CRT, driver_name_crt);
  1592. if (ret) {
  1593. dev_err(dev, "failed to start CRT\n");
  1594. goto err_started;
  1595. }
  1596. ret = sm501fb_start_one(info, HEAD_PANEL, driver_name_pnl);
  1597. if (ret) {
  1598. dev_err(dev, "failed to start Panel\n");
  1599. goto err_started_crt;
  1600. }
  1601. /* we registered, return ok */
  1602. return 0;
  1603. err_started_crt:
  1604. unregister_framebuffer(info->fb[HEAD_CRT]);
  1605. sm501_free_init_fb(info, HEAD_CRT);
  1606. err_started:
  1607. sm501fb_stop(info);
  1608. err_probed_panel:
  1609. framebuffer_release(info->fb[HEAD_PANEL]);
  1610. err_probed_crt:
  1611. framebuffer_release(info->fb[HEAD_CRT]);
  1612. err_alloc:
  1613. kfree(info);
  1614. return ret;
  1615. }
  1616. /*
  1617. * Cleanup
  1618. */
  1619. static int sm501fb_remove(struct platform_device *pdev)
  1620. {
  1621. struct sm501fb_info *info = platform_get_drvdata(pdev);
  1622. struct fb_info *fbinfo_crt = info->fb[0];
  1623. struct fb_info *fbinfo_pnl = info->fb[1];
  1624. sm501_free_init_fb(info, HEAD_CRT);
  1625. sm501_free_init_fb(info, HEAD_PANEL);
  1626. if (fbinfo_crt)
  1627. unregister_framebuffer(fbinfo_crt);
  1628. if (fbinfo_pnl)
  1629. unregister_framebuffer(fbinfo_pnl);
  1630. sm501fb_stop(info);
  1631. kfree(info);
  1632. framebuffer_release(fbinfo_pnl);
  1633. framebuffer_release(fbinfo_crt);
  1634. return 0;
  1635. }
  1636. #ifdef CONFIG_PM
  1637. static int sm501fb_suspend_fb(struct sm501fb_info *info,
  1638. enum sm501_controller head)
  1639. {
  1640. struct fb_info *fbi = info->fb[head];
  1641. struct sm501fb_par *par;
  1642. if (!fbi)
  1643. return 0;
  1644. par = fbi->par;
  1645. if (par->screen.size == 0)
  1646. return 0;
  1647. /* blank the relevant interface to ensure unit power minimised */
  1648. (par->ops.fb_blank)(FB_BLANK_POWERDOWN, fbi);
  1649. /* tell console/fb driver we are suspending */
  1650. console_lock();
  1651. fb_set_suspend(fbi, 1);
  1652. console_unlock();
  1653. /* backup copies in case chip is powered down over suspend */
  1654. par->store_fb = vmalloc(par->screen.size);
  1655. if (par->store_fb == NULL) {
  1656. dev_err(info->dev, "no memory to store screen\n");
  1657. return -ENOMEM;
  1658. }
  1659. par->store_cursor = vmalloc(par->cursor.size);
  1660. if (par->store_cursor == NULL) {
  1661. dev_err(info->dev, "no memory to store cursor\n");
  1662. goto err_nocursor;
  1663. }
  1664. dev_dbg(info->dev, "suspending screen to %p\n", par->store_fb);
  1665. dev_dbg(info->dev, "suspending cursor to %p\n", par->store_cursor);
  1666. memcpy_fromio(par->store_fb, par->screen.k_addr, par->screen.size);
  1667. memcpy_fromio(par->store_cursor, par->cursor.k_addr, par->cursor.size);
  1668. return 0;
  1669. err_nocursor:
  1670. vfree(par->store_fb);
  1671. par->store_fb = NULL;
  1672. return -ENOMEM;
  1673. }
  1674. static void sm501fb_resume_fb(struct sm501fb_info *info,
  1675. enum sm501_controller head)
  1676. {
  1677. struct fb_info *fbi = info->fb[head];
  1678. struct sm501fb_par *par;
  1679. if (!fbi)
  1680. return;
  1681. par = fbi->par;
  1682. if (par->screen.size == 0)
  1683. return;
  1684. /* re-activate the configuration */
  1685. (par->ops.fb_set_par)(fbi);
  1686. /* restore the data */
  1687. dev_dbg(info->dev, "restoring screen from %p\n", par->store_fb);
  1688. dev_dbg(info->dev, "restoring cursor from %p\n", par->store_cursor);
  1689. if (par->store_fb)
  1690. memcpy_toio(par->screen.k_addr, par->store_fb,
  1691. par->screen.size);
  1692. if (par->store_cursor)
  1693. memcpy_toio(par->cursor.k_addr, par->store_cursor,
  1694. par->cursor.size);
  1695. console_lock();
  1696. fb_set_suspend(fbi, 0);
  1697. console_unlock();
  1698. vfree(par->store_fb);
  1699. vfree(par->store_cursor);
  1700. }
  1701. /* suspend and resume support */
  1702. static int sm501fb_suspend(struct platform_device *pdev, pm_message_t state)
  1703. {
  1704. struct sm501fb_info *info = platform_get_drvdata(pdev);
  1705. /* store crt control to resume with */
  1706. info->pm_crt_ctrl = smc501_readl(info->regs + SM501_DC_CRT_CONTROL);
  1707. sm501fb_suspend_fb(info, HEAD_CRT);
  1708. sm501fb_suspend_fb(info, HEAD_PANEL);
  1709. /* turn off the clocks, in case the device is not powered down */
  1710. sm501_unit_power(info->dev->parent, SM501_GATE_DISPLAY, 0);
  1711. return 0;
  1712. }
  1713. #define SM501_CRT_CTRL_SAVE (SM501_DC_CRT_CONTROL_TVP | \
  1714. SM501_DC_CRT_CONTROL_SEL)
  1715. static int sm501fb_resume(struct platform_device *pdev)
  1716. {
  1717. struct sm501fb_info *info = platform_get_drvdata(pdev);
  1718. unsigned long crt_ctrl;
  1719. sm501_unit_power(info->dev->parent, SM501_GATE_DISPLAY, 1);
  1720. /* restore the items we want to be saved for crt control */
  1721. crt_ctrl = smc501_readl(info->regs + SM501_DC_CRT_CONTROL);
  1722. crt_ctrl &= ~SM501_CRT_CTRL_SAVE;
  1723. crt_ctrl |= info->pm_crt_ctrl & SM501_CRT_CTRL_SAVE;
  1724. smc501_writel(crt_ctrl, info->regs + SM501_DC_CRT_CONTROL);
  1725. sm501fb_resume_fb(info, HEAD_CRT);
  1726. sm501fb_resume_fb(info, HEAD_PANEL);
  1727. return 0;
  1728. }
  1729. #else
  1730. #define sm501fb_suspend NULL
  1731. #define sm501fb_resume NULL
  1732. #endif
  1733. static struct platform_driver sm501fb_driver = {
  1734. .probe = sm501fb_probe,
  1735. .remove = sm501fb_remove,
  1736. .suspend = sm501fb_suspend,
  1737. .resume = sm501fb_resume,
  1738. .driver = {
  1739. .name = "sm501-fb",
  1740. .dev_groups = sm501fb_groups,
  1741. },
  1742. };
  1743. module_platform_driver(sm501fb_driver);
  1744. module_param_named(mode, fb_mode, charp, 0);
  1745. MODULE_PARM_DESC(mode,
  1746. "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
  1747. module_param_named(bpp, default_bpp, ulong, 0);
  1748. MODULE_PARM_DESC(bpp, "Specify bit-per-pixel if not specified mode");
  1749. MODULE_AUTHOR("Ben Dooks, Vincent Sanders");
  1750. MODULE_DESCRIPTION("SM501 Framebuffer driver");
  1751. MODULE_LICENSE("GPL v2");