Home Explore Help
Sign In
samsung-sm8650
/
android_kernel_samsung_sm8650_ksu
2
0
Fork 0
Files Issues 0 Pull Requests 0 Wiki
Tree: 9e449c3f83
Branches Tags
android_kernel_...
/
drivers
/
video
/
fbdev
/
s3c2410fb-regs-lcd.h

s3c2410fb-regs-lcd.h 4.4 KB
History Raw

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143 
  1. /* SPDX-License-Identifier: GPL-2.0 */
    2. 

  2. /*
    3. 

  3.  * Copyright (c) 2003 Simtec Electronics <[email protected]>
    4. 

  4.  *		      http://www.simtec.co.uk/products/SWLINUX/
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef ___ASM_ARCH_REGS_LCD_H
    8. 

  8. #define ___ASM_ARCH_REGS_LCD_H
    9. 

  9. 

  10. /*
    11. 

  11.  * a couple of values are used as platform data in
    12. 

  12.  * include/linux/platform_data/fb-s3c2410.h and not
    13. 

  13.  * duplicated here.
    14. 

  14.  */
    15. 

  15. #include <linux/platform_data/fb-s3c2410.h>
    16. 

  16. 

  17. #define S3C2410_LCDREG(x)	(x)
    18. 

  18. 

  19. /* LCD control registers */
    20. 

  20. #define S3C2410_LCDCON1	    S3C2410_LCDREG(0x00)
    21. 

  21. #define S3C2410_LCDCON2	    S3C2410_LCDREG(0x04)
    22. 

  22. #define S3C2410_LCDCON3	    S3C2410_LCDREG(0x08)
    23. 

  23. #define S3C2410_LCDCON4	    S3C2410_LCDREG(0x0C)
    24. 

  24. #define S3C2410_LCDCON5	    S3C2410_LCDREG(0x10)
    25. 

  25. 

  26. #define S3C2410_LCDCON1_CLKVAL(x)  ((x) << 8)
    27. 

  27. #define S3C2410_LCDCON1_MMODE	   (1<<7)
    28. 

  28. #define S3C2410_LCDCON1_DSCAN4	   (0<<5)
    29. 

  29. #define S3C2410_LCDCON1_STN4	   (1<<5)
    30. 

  30. #define S3C2410_LCDCON1_STN8	   (2<<5)
    31. 

  31. #define S3C2410_LCDCON1_TFT	   (3<<5)
    32. 

  32. 

  33. #define S3C2410_LCDCON1_STN1BPP	   (0<<1)
    34. 

  34. #define S3C2410_LCDCON1_STN2GREY   (1<<1)
    35. 

  35. #define S3C2410_LCDCON1_STN4GREY   (2<<1)
    36. 

  36. #define S3C2410_LCDCON1_STN8BPP	   (3<<1)
    37. 

  37. #define S3C2410_LCDCON1_STN12BPP   (4<<1)
    38. 

  38. 

  39. #define S3C2410_LCDCON1_ENVID	   (1)
    40. 

  40. 

  41. #define S3C2410_LCDCON1_MODEMASK    0x1E
    42. 

  42. 

  43. #define S3C2410_LCDCON2_VBPD(x)	    ((x) << 24)
    44. 

  44. #define S3C2410_LCDCON2_LINEVAL(x)  ((x) << 14)
    45. 

  45. #define S3C2410_LCDCON2_VFPD(x)	    ((x) << 6)
    46. 

  46. #define S3C2410_LCDCON2_VSPW(x)	    ((x) << 0)
    47. 

  47. 

  48. #define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF)
    49. 

  49. #define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >>  6) & 0xFF)
    50. 

  50. #define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >>  0) & 0x3F)
    51. 

  51. 

  52. #define S3C2410_LCDCON3_HBPD(x)	    ((x) << 19)
    53. 

  53. #define S3C2410_LCDCON3_WDLY(x)	    ((x) << 19)
    54. 

  54. #define S3C2410_LCDCON3_HOZVAL(x)   ((x) << 8)
    55. 

  55. #define S3C2410_LCDCON3_HFPD(x)	    ((x) << 0)
    56. 

  56. #define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0)
    57. 

  57. 

  58. #define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F)
    59. 

  59. #define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >>  0) & 0xFF)
    60. 

  60. 

  61. /* LDCCON4 changes for STN mode on the S3C2412 */
    62. 

  62. 

  63. #define S3C2410_LCDCON4_MVAL(x)	    ((x) << 8)
    64. 

  64. #define S3C2410_LCDCON4_HSPW(x)	    ((x) << 0)
    65. 

  65. #define S3C2410_LCDCON4_WLH(x)	    ((x) << 0)
    66. 

  66. 

  67. #define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >>  0) & 0xFF)
    68. 

  68. 

  69. /* framebuffer start addressed */
    70. 

  70. #define S3C2410_LCDSADDR1   S3C2410_LCDREG(0x14)
    71. 

  71. #define S3C2410_LCDSADDR2   S3C2410_LCDREG(0x18)
    72. 

  72. #define S3C2410_LCDSADDR3   S3C2410_LCDREG(0x1C)
    73. 

  73. 

  74. #define S3C2410_LCDBANK(x)	((x) << 21)
    75. 

  75. #define S3C2410_LCDBASEU(x)	(x)
    76. 

  76. 

  77. #define S3C2410_OFFSIZE(x)	((x) << 11)
    78. 

  78. #define S3C2410_PAGEWIDTH(x)	(x)
    79. 

  79. 

  80. /* colour lookup and miscellaneous controls */
    81. 

  81. 

  82. #define S3C2410_REDLUT	   S3C2410_LCDREG(0x20)
    83. 

  83. #define S3C2410_GREENLUT   S3C2410_LCDREG(0x24)
    84. 

  84. #define S3C2410_BLUELUT	   S3C2410_LCDREG(0x28)
    85. 

  85. 

  86. #define S3C2410_DITHMODE   S3C2410_LCDREG(0x4C)
    87. 

  87. #define S3C2410_TPAL	   S3C2410_LCDREG(0x50)
    88. 

  88. 

  89. #define S3C2410_TPAL_EN		(1<<24)
    90. 

  90. 

  91. /* interrupt info */
    92. 

  92. #define S3C2410_LCDINTPND  S3C2410_LCDREG(0x54)
    93. 

  93. #define S3C2410_LCDSRCPND  S3C2410_LCDREG(0x58)
    94. 

  94. #define S3C2410_LCDINTMSK  S3C2410_LCDREG(0x5C)
    95. 

  95. #define S3C2410_LCDINT_FIWSEL	(1<<2)
    96. 

  96. #define	S3C2410_LCDINT_FRSYNC	(1<<1)
    97. 

  97. #define S3C2410_LCDINT_FICNT	(1<<0)
    98. 

  98. 

  99. /* s3c2442 extra stn registers */
    100. 

  100. 

  101. #define S3C2442_REDLUT		S3C2410_LCDREG(0x20)
    102. 

  102. #define S3C2442_GREENLUT	S3C2410_LCDREG(0x24)
    103. 

  103. #define S3C2442_BLUELUT		S3C2410_LCDREG(0x28)
    104. 

  104. #define S3C2442_DITHMODE	S3C2410_LCDREG(0x20)
    105. 

  105. 

  106. #define S3C2410_LPCSEL	   S3C2410_LCDREG(0x60)
    107. 

  107. 

  108. #define S3C2410_TFTPAL(x)  S3C2410_LCDREG((0x400 + (x)*4))
    109. 

  109. 

  110. /* S3C2412 registers */
    111. 

  111. 

  112. #define S3C2412_TPAL		S3C2410_LCDREG(0x20)
    113. 

  113. 

  114. #define S3C2412_LCDINTPND	S3C2410_LCDREG(0x24)
    115. 

  115. #define S3C2412_LCDSRCPND	S3C2410_LCDREG(0x28)
    116. 

  116. #define S3C2412_LCDINTMSK	S3C2410_LCDREG(0x2C)
    117. 

  117. 

  118. #define S3C2412_TCONSEL		S3C2410_LCDREG(0x30)
    119. 

  119. 

  120. #define S3C2412_LCDCON6		S3C2410_LCDREG(0x34)
    121. 

  121. #define S3C2412_LCDCON7		S3C2410_LCDREG(0x38)
    122. 

  122. #define S3C2412_LCDCON8		S3C2410_LCDREG(0x3C)
    123. 

  123. #define S3C2412_LCDCON9		S3C2410_LCDREG(0x40)
    124. 

  124. 

  125. #define S3C2412_REDLUT(x)	S3C2410_LCDREG(0x44 + ((x)*4))
    126. 

  126. #define S3C2412_GREENLUT(x)	S3C2410_LCDREG(0x60 + ((x)*4))
    127. 

  127. #define S3C2412_BLUELUT(x)	S3C2410_LCDREG(0x98 + ((x)*4))
    128. 

  128. 

  129. #define S3C2412_FRCPAT(x)	S3C2410_LCDREG(0xB4 + ((x)*4))
    130. 

  130. 

  131. /* general registers */
    132. 

  132. 

  133. /* base of the LCD registers, where INTPND, INTSRC and then INTMSK
    134. 

  134.  * are available. */
    135. 

  135. 

  136. #define S3C2410_LCDINTBASE	S3C2410_LCDREG(0x54)
    137. 

  137. #define S3C2412_LCDINTBASE	S3C2410_LCDREG(0x24)
    138. 

  138. 

  139. #define S3C24XX_LCDINTPND	(0x00)
    140. 

  140. #define S3C24XX_LCDSRCPND	(0x04)
    141. 

  141. #define S3C24XX_LCDINTMSK	(0x08)
    142. 

  142. 

  143. #endif /* ___ASM_ARCH_REGS_LCD_H */
    144.