offb.c 20 KB

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  1. /*
  2. * linux/drivers/video/offb.c -- Open Firmware based frame buffer device
  3. *
  4. * Copyright (C) 1997 Geert Uytterhoeven
  5. *
  6. * This driver is partly based on the PowerMac console driver:
  7. *
  8. * Copyright (C) 1996 Paul Mackerras
  9. *
  10. * This file is subject to the terms and conditions of the GNU General Public
  11. * License. See the file COPYING in the main directory of this archive for
  12. * more details.
  13. */
  14. #include <linux/module.h>
  15. #include <linux/kernel.h>
  16. #include <linux/errno.h>
  17. #include <linux/string.h>
  18. #include <linux/mm.h>
  19. #include <linux/vmalloc.h>
  20. #include <linux/delay.h>
  21. #include <linux/of.h>
  22. #include <linux/of_address.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/fb.h>
  25. #include <linux/init.h>
  26. #include <linux/ioport.h>
  27. #include <linux/pci.h>
  28. #include <linux/platform_device.h>
  29. #include <asm/io.h>
  30. #ifdef CONFIG_PPC32
  31. #include <asm/bootx.h>
  32. #endif
  33. #include "macmodes.h"
  34. /* Supported palette hacks */
  35. enum {
  36. cmap_unknown,
  37. cmap_simple, /* ATI Mach64 */
  38. cmap_r128, /* ATI Rage128 */
  39. cmap_M3A, /* ATI Rage Mobility M3 Head A */
  40. cmap_M3B, /* ATI Rage Mobility M3 Head B */
  41. cmap_radeon, /* ATI Radeon */
  42. cmap_gxt2000, /* IBM GXT2000 */
  43. cmap_avivo, /* ATI R5xx */
  44. cmap_qemu, /* qemu vga */
  45. };
  46. struct offb_par {
  47. volatile void __iomem *cmap_adr;
  48. volatile void __iomem *cmap_data;
  49. int cmap_type;
  50. int blanked;
  51. };
  52. struct offb_par default_par;
  53. #ifdef CONFIG_PPC32
  54. extern boot_infos_t *boot_infos;
  55. #endif
  56. /* Definitions used by the Avivo palette hack */
  57. #define AVIVO_DC_LUT_RW_SELECT 0x6480
  58. #define AVIVO_DC_LUT_RW_MODE 0x6484
  59. #define AVIVO_DC_LUT_RW_INDEX 0x6488
  60. #define AVIVO_DC_LUT_SEQ_COLOR 0x648c
  61. #define AVIVO_DC_LUT_PWL_DATA 0x6490
  62. #define AVIVO_DC_LUT_30_COLOR 0x6494
  63. #define AVIVO_DC_LUT_READ_PIPE_SELECT 0x6498
  64. #define AVIVO_DC_LUT_WRITE_EN_MASK 0x649c
  65. #define AVIVO_DC_LUT_AUTOFILL 0x64a0
  66. #define AVIVO_DC_LUTA_CONTROL 0x64c0
  67. #define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE 0x64c4
  68. #define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN 0x64c8
  69. #define AVIVO_DC_LUTA_BLACK_OFFSET_RED 0x64cc
  70. #define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE 0x64d0
  71. #define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4
  72. #define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8
  73. #define AVIVO_DC_LUTB_CONTROL 0x6cc0
  74. #define AVIVO_DC_LUTB_BLACK_OFFSET_BLUE 0x6cc4
  75. #define AVIVO_DC_LUTB_BLACK_OFFSET_GREEN 0x6cc8
  76. #define AVIVO_DC_LUTB_BLACK_OFFSET_RED 0x6ccc
  77. #define AVIVO_DC_LUTB_WHITE_OFFSET_BLUE 0x6cd0
  78. #define AVIVO_DC_LUTB_WHITE_OFFSET_GREEN 0x6cd4
  79. #define AVIVO_DC_LUTB_WHITE_OFFSET_RED 0x6cd8
  80. /*
  81. * Set a single color register. The values supplied are already
  82. * rounded down to the hardware's capabilities (according to the
  83. * entries in the var structure). Return != 0 for invalid regno.
  84. */
  85. static int offb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
  86. u_int transp, struct fb_info *info)
  87. {
  88. struct offb_par *par = (struct offb_par *) info->par;
  89. if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
  90. u32 *pal = info->pseudo_palette;
  91. u32 cr = red >> (16 - info->var.red.length);
  92. u32 cg = green >> (16 - info->var.green.length);
  93. u32 cb = blue >> (16 - info->var.blue.length);
  94. u32 value;
  95. if (regno >= 16)
  96. return -EINVAL;
  97. value = (cr << info->var.red.offset) |
  98. (cg << info->var.green.offset) |
  99. (cb << info->var.blue.offset);
  100. if (info->var.transp.length > 0) {
  101. u32 mask = (1 << info->var.transp.length) - 1;
  102. mask <<= info->var.transp.offset;
  103. value |= mask;
  104. }
  105. pal[regno] = value;
  106. return 0;
  107. }
  108. if (regno > 255)
  109. return -EINVAL;
  110. red >>= 8;
  111. green >>= 8;
  112. blue >>= 8;
  113. if (!par->cmap_adr)
  114. return 0;
  115. switch (par->cmap_type) {
  116. case cmap_simple:
  117. writeb(regno, par->cmap_adr);
  118. writeb(red, par->cmap_data);
  119. writeb(green, par->cmap_data);
  120. writeb(blue, par->cmap_data);
  121. break;
  122. case cmap_M3A:
  123. /* Clear PALETTE_ACCESS_CNTL in DAC_CNTL */
  124. out_le32(par->cmap_adr + 0x58,
  125. in_le32(par->cmap_adr + 0x58) & ~0x20);
  126. fallthrough;
  127. case cmap_r128:
  128. /* Set palette index & data */
  129. out_8(par->cmap_adr + 0xb0, regno);
  130. out_le32(par->cmap_adr + 0xb4,
  131. (red << 16 | green << 8 | blue));
  132. break;
  133. case cmap_M3B:
  134. /* Set PALETTE_ACCESS_CNTL in DAC_CNTL */
  135. out_le32(par->cmap_adr + 0x58,
  136. in_le32(par->cmap_adr + 0x58) | 0x20);
  137. /* Set palette index & data */
  138. out_8(par->cmap_adr + 0xb0, regno);
  139. out_le32(par->cmap_adr + 0xb4, (red << 16 | green << 8 | blue));
  140. break;
  141. case cmap_radeon:
  142. /* Set palette index & data (could be smarter) */
  143. out_8(par->cmap_adr + 0xb0, regno);
  144. out_le32(par->cmap_adr + 0xb4, (red << 16 | green << 8 | blue));
  145. break;
  146. case cmap_gxt2000:
  147. out_le32(((unsigned __iomem *) par->cmap_adr) + regno,
  148. (red << 16 | green << 8 | blue));
  149. break;
  150. case cmap_avivo:
  151. /* Write to both LUTs for now */
  152. writel(1, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT);
  153. writeb(regno, par->cmap_adr + AVIVO_DC_LUT_RW_INDEX);
  154. writel(((red) << 22) | ((green) << 12) | ((blue) << 2),
  155. par->cmap_adr + AVIVO_DC_LUT_30_COLOR);
  156. writel(0, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT);
  157. writeb(regno, par->cmap_adr + AVIVO_DC_LUT_RW_INDEX);
  158. writel(((red) << 22) | ((green) << 12) | ((blue) << 2),
  159. par->cmap_adr + AVIVO_DC_LUT_30_COLOR);
  160. break;
  161. }
  162. return 0;
  163. }
  164. /*
  165. * Blank the display.
  166. */
  167. static int offb_blank(int blank, struct fb_info *info)
  168. {
  169. struct offb_par *par = (struct offb_par *) info->par;
  170. int i, j;
  171. if (!par->cmap_adr)
  172. return 0;
  173. if (!par->blanked)
  174. if (!blank)
  175. return 0;
  176. par->blanked = blank;
  177. if (blank)
  178. for (i = 0; i < 256; i++) {
  179. switch (par->cmap_type) {
  180. case cmap_simple:
  181. writeb(i, par->cmap_adr);
  182. for (j = 0; j < 3; j++)
  183. writeb(0, par->cmap_data);
  184. break;
  185. case cmap_M3A:
  186. /* Clear PALETTE_ACCESS_CNTL in DAC_CNTL */
  187. out_le32(par->cmap_adr + 0x58,
  188. in_le32(par->cmap_adr + 0x58) & ~0x20);
  189. fallthrough;
  190. case cmap_r128:
  191. /* Set palette index & data */
  192. out_8(par->cmap_adr + 0xb0, i);
  193. out_le32(par->cmap_adr + 0xb4, 0);
  194. break;
  195. case cmap_M3B:
  196. /* Set PALETTE_ACCESS_CNTL in DAC_CNTL */
  197. out_le32(par->cmap_adr + 0x58,
  198. in_le32(par->cmap_adr + 0x58) | 0x20);
  199. /* Set palette index & data */
  200. out_8(par->cmap_adr + 0xb0, i);
  201. out_le32(par->cmap_adr + 0xb4, 0);
  202. break;
  203. case cmap_radeon:
  204. out_8(par->cmap_adr + 0xb0, i);
  205. out_le32(par->cmap_adr + 0xb4, 0);
  206. break;
  207. case cmap_gxt2000:
  208. out_le32(((unsigned __iomem *) par->cmap_adr) + i,
  209. 0);
  210. break;
  211. case cmap_avivo:
  212. writel(1, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT);
  213. writeb(i, par->cmap_adr + AVIVO_DC_LUT_RW_INDEX);
  214. writel(0, par->cmap_adr + AVIVO_DC_LUT_30_COLOR);
  215. writel(0, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT);
  216. writeb(i, par->cmap_adr + AVIVO_DC_LUT_RW_INDEX);
  217. writel(0, par->cmap_adr + AVIVO_DC_LUT_30_COLOR);
  218. break;
  219. }
  220. } else
  221. fb_set_cmap(&info->cmap, info);
  222. return 0;
  223. }
  224. static int offb_set_par(struct fb_info *info)
  225. {
  226. struct offb_par *par = (struct offb_par *) info->par;
  227. /* On avivo, initialize palette control */
  228. if (par->cmap_type == cmap_avivo) {
  229. writel(0, par->cmap_adr + AVIVO_DC_LUTA_CONTROL);
  230. writel(0, par->cmap_adr + AVIVO_DC_LUTA_BLACK_OFFSET_BLUE);
  231. writel(0, par->cmap_adr + AVIVO_DC_LUTA_BLACK_OFFSET_GREEN);
  232. writel(0, par->cmap_adr + AVIVO_DC_LUTA_BLACK_OFFSET_RED);
  233. writel(0x0000ffff, par->cmap_adr + AVIVO_DC_LUTA_WHITE_OFFSET_BLUE);
  234. writel(0x0000ffff, par->cmap_adr + AVIVO_DC_LUTA_WHITE_OFFSET_GREEN);
  235. writel(0x0000ffff, par->cmap_adr + AVIVO_DC_LUTA_WHITE_OFFSET_RED);
  236. writel(0, par->cmap_adr + AVIVO_DC_LUTB_CONTROL);
  237. writel(0, par->cmap_adr + AVIVO_DC_LUTB_BLACK_OFFSET_BLUE);
  238. writel(0, par->cmap_adr + AVIVO_DC_LUTB_BLACK_OFFSET_GREEN);
  239. writel(0, par->cmap_adr + AVIVO_DC_LUTB_BLACK_OFFSET_RED);
  240. writel(0x0000ffff, par->cmap_adr + AVIVO_DC_LUTB_WHITE_OFFSET_BLUE);
  241. writel(0x0000ffff, par->cmap_adr + AVIVO_DC_LUTB_WHITE_OFFSET_GREEN);
  242. writel(0x0000ffff, par->cmap_adr + AVIVO_DC_LUTB_WHITE_OFFSET_RED);
  243. writel(1, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT);
  244. writel(0, par->cmap_adr + AVIVO_DC_LUT_RW_MODE);
  245. writel(0x0000003f, par->cmap_adr + AVIVO_DC_LUT_WRITE_EN_MASK);
  246. writel(0, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT);
  247. writel(0, par->cmap_adr + AVIVO_DC_LUT_RW_MODE);
  248. writel(0x0000003f, par->cmap_adr + AVIVO_DC_LUT_WRITE_EN_MASK);
  249. }
  250. return 0;
  251. }
  252. static void offb_destroy(struct fb_info *info)
  253. {
  254. if (info->screen_base)
  255. iounmap(info->screen_base);
  256. release_mem_region(info->apertures->ranges[0].base, info->apertures->ranges[0].size);
  257. fb_dealloc_cmap(&info->cmap);
  258. framebuffer_release(info);
  259. }
  260. static const struct fb_ops offb_ops = {
  261. .owner = THIS_MODULE,
  262. .fb_destroy = offb_destroy,
  263. .fb_setcolreg = offb_setcolreg,
  264. .fb_set_par = offb_set_par,
  265. .fb_blank = offb_blank,
  266. .fb_fillrect = cfb_fillrect,
  267. .fb_copyarea = cfb_copyarea,
  268. .fb_imageblit = cfb_imageblit,
  269. };
  270. static void __iomem *offb_map_reg(struct device_node *np, int index,
  271. unsigned long offset, unsigned long size)
  272. {
  273. const __be32 *addrp;
  274. u64 asize, taddr;
  275. unsigned int flags;
  276. addrp = of_get_pci_address(np, index, &asize, &flags);
  277. if (addrp == NULL)
  278. addrp = of_get_address(np, index, &asize, &flags);
  279. if (addrp == NULL)
  280. return NULL;
  281. if ((flags & (IORESOURCE_IO | IORESOURCE_MEM)) == 0)
  282. return NULL;
  283. if ((offset + size) > asize)
  284. return NULL;
  285. taddr = of_translate_address(np, addrp);
  286. if (taddr == OF_BAD_ADDR)
  287. return NULL;
  288. return ioremap(taddr + offset, size);
  289. }
  290. static void offb_init_palette_hacks(struct fb_info *info, struct device_node *dp,
  291. unsigned long address)
  292. {
  293. struct offb_par *par = (struct offb_par *) info->par;
  294. if (of_node_name_prefix(dp, "ATY,Rage128")) {
  295. par->cmap_adr = offb_map_reg(dp, 2, 0, 0x1fff);
  296. if (par->cmap_adr)
  297. par->cmap_type = cmap_r128;
  298. } else if (of_node_name_prefix(dp, "ATY,RageM3pA") ||
  299. of_node_name_prefix(dp, "ATY,RageM3p12A")) {
  300. par->cmap_adr = offb_map_reg(dp, 2, 0, 0x1fff);
  301. if (par->cmap_adr)
  302. par->cmap_type = cmap_M3A;
  303. } else if (of_node_name_prefix(dp, "ATY,RageM3pB")) {
  304. par->cmap_adr = offb_map_reg(dp, 2, 0, 0x1fff);
  305. if (par->cmap_adr)
  306. par->cmap_type = cmap_M3B;
  307. } else if (of_node_name_prefix(dp, "ATY,Rage6")) {
  308. par->cmap_adr = offb_map_reg(dp, 1, 0, 0x1fff);
  309. if (par->cmap_adr)
  310. par->cmap_type = cmap_radeon;
  311. } else if (of_node_name_prefix(dp, "ATY,")) {
  312. unsigned long base = address & 0xff000000UL;
  313. par->cmap_adr =
  314. ioremap(base + 0x7ff000, 0x1000) + 0xcc0;
  315. par->cmap_data = par->cmap_adr + 1;
  316. par->cmap_type = cmap_simple;
  317. } else if (dp && (of_device_is_compatible(dp, "pci1014,b7") ||
  318. of_device_is_compatible(dp, "pci1014,21c"))) {
  319. par->cmap_adr = offb_map_reg(dp, 0, 0x6000, 0x1000);
  320. if (par->cmap_adr)
  321. par->cmap_type = cmap_gxt2000;
  322. } else if (of_node_name_prefix(dp, "vga,Display-")) {
  323. /* Look for AVIVO initialized by SLOF */
  324. struct device_node *pciparent = of_get_parent(dp);
  325. const u32 *vid, *did;
  326. vid = of_get_property(pciparent, "vendor-id", NULL);
  327. did = of_get_property(pciparent, "device-id", NULL);
  328. /* This will match most R5xx */
  329. if (vid && did && *vid == 0x1002 &&
  330. ((*did >= 0x7100 && *did < 0x7800) ||
  331. (*did >= 0x9400))) {
  332. par->cmap_adr = offb_map_reg(pciparent, 2, 0, 0x10000);
  333. if (par->cmap_adr)
  334. par->cmap_type = cmap_avivo;
  335. }
  336. of_node_put(pciparent);
  337. } else if (dp && of_device_is_compatible(dp, "qemu,std-vga")) {
  338. #ifdef __BIG_ENDIAN
  339. const __be32 io_of_addr[3] = { 0x01000000, 0x0, 0x0 };
  340. #else
  341. const __be32 io_of_addr[3] = { 0x00000001, 0x0, 0x0 };
  342. #endif
  343. u64 io_addr = of_translate_address(dp, io_of_addr);
  344. if (io_addr != OF_BAD_ADDR) {
  345. par->cmap_adr = ioremap(io_addr + 0x3c8, 2);
  346. if (par->cmap_adr) {
  347. par->cmap_type = cmap_simple;
  348. par->cmap_data = par->cmap_adr + 1;
  349. }
  350. }
  351. }
  352. info->fix.visual = (par->cmap_type != cmap_unknown) ?
  353. FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_STATIC_PSEUDOCOLOR;
  354. }
  355. static void offb_init_fb(struct platform_device *parent, const char *name,
  356. int width, int height, int depth,
  357. int pitch, unsigned long address,
  358. int foreign_endian, struct device_node *dp)
  359. {
  360. unsigned long res_size = pitch * height;
  361. struct offb_par *par = &default_par;
  362. unsigned long res_start = address;
  363. struct fb_fix_screeninfo *fix;
  364. struct fb_var_screeninfo *var;
  365. struct fb_info *info;
  366. if (!request_mem_region(res_start, res_size, "offb"))
  367. return;
  368. printk(KERN_INFO
  369. "Using unsupported %dx%d %s at %lx, depth=%d, pitch=%d\n",
  370. width, height, name, address, depth, pitch);
  371. if (depth != 8 && depth != 15 && depth != 16 && depth != 32) {
  372. printk(KERN_ERR "%pOF: can't use depth = %d\n", dp, depth);
  373. release_mem_region(res_start, res_size);
  374. return;
  375. }
  376. info = framebuffer_alloc(sizeof(u32) * 16, &parent->dev);
  377. if (!info) {
  378. release_mem_region(res_start, res_size);
  379. return;
  380. }
  381. platform_set_drvdata(parent, info);
  382. fix = &info->fix;
  383. var = &info->var;
  384. info->par = par;
  385. if (name) {
  386. strcpy(fix->id, "OFfb ");
  387. strncat(fix->id, name, sizeof(fix->id) - sizeof("OFfb "));
  388. fix->id[sizeof(fix->id) - 1] = '\0';
  389. } else
  390. snprintf(fix->id, sizeof(fix->id), "OFfb %pOFn", dp);
  391. var->xres = var->xres_virtual = width;
  392. var->yres = var->yres_virtual = height;
  393. fix->line_length = pitch;
  394. fix->smem_start = address;
  395. fix->smem_len = pitch * height;
  396. fix->type = FB_TYPE_PACKED_PIXELS;
  397. fix->type_aux = 0;
  398. par->cmap_type = cmap_unknown;
  399. if (depth == 8)
  400. offb_init_palette_hacks(info, dp, address);
  401. else
  402. fix->visual = FB_VISUAL_TRUECOLOR;
  403. var->xoffset = var->yoffset = 0;
  404. switch (depth) {
  405. case 8:
  406. var->bits_per_pixel = 8;
  407. var->red.offset = 0;
  408. var->red.length = 8;
  409. var->green.offset = 0;
  410. var->green.length = 8;
  411. var->blue.offset = 0;
  412. var->blue.length = 8;
  413. var->transp.offset = 0;
  414. var->transp.length = 0;
  415. break;
  416. case 15: /* RGB 555 */
  417. var->bits_per_pixel = 16;
  418. var->red.offset = 10;
  419. var->red.length = 5;
  420. var->green.offset = 5;
  421. var->green.length = 5;
  422. var->blue.offset = 0;
  423. var->blue.length = 5;
  424. var->transp.offset = 0;
  425. var->transp.length = 0;
  426. break;
  427. case 16: /* RGB 565 */
  428. var->bits_per_pixel = 16;
  429. var->red.offset = 11;
  430. var->red.length = 5;
  431. var->green.offset = 5;
  432. var->green.length = 6;
  433. var->blue.offset = 0;
  434. var->blue.length = 5;
  435. var->transp.offset = 0;
  436. var->transp.length = 0;
  437. break;
  438. case 32: /* RGB 888 */
  439. var->bits_per_pixel = 32;
  440. var->red.offset = 16;
  441. var->red.length = 8;
  442. var->green.offset = 8;
  443. var->green.length = 8;
  444. var->blue.offset = 0;
  445. var->blue.length = 8;
  446. var->transp.offset = 24;
  447. var->transp.length = 8;
  448. break;
  449. }
  450. var->red.msb_right = var->green.msb_right = var->blue.msb_right =
  451. var->transp.msb_right = 0;
  452. var->grayscale = 0;
  453. var->nonstd = 0;
  454. var->activate = 0;
  455. var->height = var->width = -1;
  456. var->pixclock = 10000;
  457. var->left_margin = var->right_margin = 16;
  458. var->upper_margin = var->lower_margin = 16;
  459. var->hsync_len = var->vsync_len = 8;
  460. var->sync = 0;
  461. var->vmode = FB_VMODE_NONINTERLACED;
  462. /* set offb aperture size for generic probing */
  463. info->apertures = alloc_apertures(1);
  464. if (!info->apertures)
  465. goto out_aper;
  466. info->apertures->ranges[0].base = address;
  467. info->apertures->ranges[0].size = fix->smem_len;
  468. info->fbops = &offb_ops;
  469. info->screen_base = ioremap(address, fix->smem_len);
  470. info->pseudo_palette = (void *) (info + 1);
  471. info->flags = FBINFO_DEFAULT | FBINFO_MISC_FIRMWARE | foreign_endian;
  472. fb_alloc_cmap(&info->cmap, 256, 0);
  473. if (register_framebuffer(info) < 0)
  474. goto out_err;
  475. fb_info(info, "Open Firmware frame buffer device on %pOF\n", dp);
  476. return;
  477. out_err:
  478. fb_dealloc_cmap(&info->cmap);
  479. iounmap(info->screen_base);
  480. out_aper:
  481. iounmap(par->cmap_adr);
  482. par->cmap_adr = NULL;
  483. framebuffer_release(info);
  484. release_mem_region(res_start, res_size);
  485. }
  486. static void offb_init_nodriver(struct platform_device *parent, struct device_node *dp,
  487. int no_real_node)
  488. {
  489. unsigned int len;
  490. int i, width = 640, height = 480, depth = 8, pitch = 640;
  491. unsigned int flags, rsize, addr_prop = 0;
  492. unsigned long max_size = 0;
  493. u64 rstart, address = OF_BAD_ADDR;
  494. const __be32 *pp, *addrp, *up;
  495. u64 asize;
  496. int foreign_endian = 0;
  497. #ifdef __BIG_ENDIAN
  498. if (of_get_property(dp, "little-endian", NULL))
  499. foreign_endian = FBINFO_FOREIGN_ENDIAN;
  500. #else
  501. if (of_get_property(dp, "big-endian", NULL))
  502. foreign_endian = FBINFO_FOREIGN_ENDIAN;
  503. #endif
  504. pp = of_get_property(dp, "linux,bootx-depth", &len);
  505. if (pp == NULL)
  506. pp = of_get_property(dp, "depth", &len);
  507. if (pp && len == sizeof(u32))
  508. depth = be32_to_cpup(pp);
  509. pp = of_get_property(dp, "linux,bootx-width", &len);
  510. if (pp == NULL)
  511. pp = of_get_property(dp, "width", &len);
  512. if (pp && len == sizeof(u32))
  513. width = be32_to_cpup(pp);
  514. pp = of_get_property(dp, "linux,bootx-height", &len);
  515. if (pp == NULL)
  516. pp = of_get_property(dp, "height", &len);
  517. if (pp && len == sizeof(u32))
  518. height = be32_to_cpup(pp);
  519. pp = of_get_property(dp, "linux,bootx-linebytes", &len);
  520. if (pp == NULL)
  521. pp = of_get_property(dp, "linebytes", &len);
  522. if (pp && len == sizeof(u32) && (*pp != 0xffffffffu))
  523. pitch = be32_to_cpup(pp);
  524. else
  525. pitch = width * ((depth + 7) / 8);
  526. rsize = (unsigned long)pitch * (unsigned long)height;
  527. /* Ok, now we try to figure out the address of the framebuffer.
  528. *
  529. * Unfortunately, Open Firmware doesn't provide a standard way to do
  530. * so. All we can do is a dodgy heuristic that happens to work in
  531. * practice. On most machines, the "address" property contains what
  532. * we need, though not on Matrox cards found in IBM machines. What I've
  533. * found that appears to give good results is to go through the PCI
  534. * ranges and pick one that is both big enough and if possible encloses
  535. * the "address" property. If none match, we pick the biggest
  536. */
  537. up = of_get_property(dp, "linux,bootx-addr", &len);
  538. if (up == NULL)
  539. up = of_get_property(dp, "address", &len);
  540. if (up && len == sizeof(u32))
  541. addr_prop = *up;
  542. /* Hack for when BootX is passing us */
  543. if (no_real_node)
  544. goto skip_addr;
  545. for (i = 0; (addrp = of_get_address(dp, i, &asize, &flags))
  546. != NULL; i++) {
  547. int match_addrp = 0;
  548. if (!(flags & IORESOURCE_MEM))
  549. continue;
  550. if (asize < rsize)
  551. continue;
  552. rstart = of_translate_address(dp, addrp);
  553. if (rstart == OF_BAD_ADDR)
  554. continue;
  555. if (addr_prop && (rstart <= addr_prop) &&
  556. ((rstart + asize) >= (addr_prop + rsize)))
  557. match_addrp = 1;
  558. if (match_addrp) {
  559. address = addr_prop;
  560. break;
  561. }
  562. if (rsize > max_size) {
  563. max_size = rsize;
  564. address = OF_BAD_ADDR;
  565. }
  566. if (address == OF_BAD_ADDR)
  567. address = rstart;
  568. }
  569. skip_addr:
  570. if (address == OF_BAD_ADDR && addr_prop)
  571. address = (u64)addr_prop;
  572. if (address != OF_BAD_ADDR) {
  573. #ifdef CONFIG_PCI
  574. const __be32 *vidp, *didp;
  575. u32 vid, did;
  576. struct pci_dev *pdev;
  577. vidp = of_get_property(dp, "vendor-id", NULL);
  578. didp = of_get_property(dp, "device-id", NULL);
  579. if (vidp && didp) {
  580. vid = be32_to_cpup(vidp);
  581. did = be32_to_cpup(didp);
  582. pdev = pci_get_device(vid, did, NULL);
  583. if (!pdev || pci_enable_device(pdev))
  584. return;
  585. }
  586. #endif
  587. /* kludge for valkyrie */
  588. if (of_node_name_eq(dp, "valkyrie"))
  589. address += 0x1000;
  590. offb_init_fb(parent, no_real_node ? "bootx" : NULL,
  591. width, height, depth, pitch, address,
  592. foreign_endian, no_real_node ? NULL : dp);
  593. }
  594. }
  595. static int offb_remove(struct platform_device *pdev)
  596. {
  597. struct fb_info *info = platform_get_drvdata(pdev);
  598. if (info)
  599. unregister_framebuffer(info);
  600. return 0;
  601. }
  602. static int offb_probe_bootx_noscreen(struct platform_device *pdev)
  603. {
  604. offb_init_nodriver(pdev, of_chosen, 1);
  605. return 0;
  606. }
  607. static struct platform_driver offb_driver_bootx_noscreen = {
  608. .driver = {
  609. .name = "bootx-noscreen",
  610. },
  611. .probe = offb_probe_bootx_noscreen,
  612. .remove = offb_remove,
  613. };
  614. static int offb_probe_display(struct platform_device *pdev)
  615. {
  616. offb_init_nodriver(pdev, pdev->dev.of_node, 0);
  617. return 0;
  618. }
  619. static const struct of_device_id offb_of_match_display[] = {
  620. { .compatible = "display", },
  621. { },
  622. };
  623. MODULE_DEVICE_TABLE(of, offb_of_match_display);
  624. static struct platform_driver offb_driver_display = {
  625. .driver = {
  626. .name = "of-display",
  627. .of_match_table = offb_of_match_display,
  628. },
  629. .probe = offb_probe_display,
  630. .remove = offb_remove,
  631. };
  632. static int __init offb_init(void)
  633. {
  634. if (fb_get_options("offb", NULL))
  635. return -ENODEV;
  636. platform_driver_register(&offb_driver_bootx_noscreen);
  637. platform_driver_register(&offb_driver_display);
  638. return 0;
  639. }
  640. module_init(offb_init);
  641. static void __exit offb_exit(void)
  642. {
  643. platform_driver_unregister(&offb_driver_display);
  644. platform_driver_unregister(&offb_driver_bootx_noscreen);
  645. }
  646. module_exit(offb_exit);
  647. MODULE_LICENSE("GPL");