gxt4500.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Frame buffer device for IBM GXT4500P/6500P and GXT4000P/6000P
  4. * display adaptors
  5. *
  6. * Copyright (C) 2006 Paul Mackerras, IBM Corp. <[email protected]>
  7. */
  8. #include <linux/aperture.h>
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/fb.h>
  12. #include <linux/console.h>
  13. #include <linux/pci.h>
  14. #include <linux/pci_ids.h>
  15. #include <linux/delay.h>
  16. #include <linux/string.h>
  17. #define PCI_DEVICE_ID_IBM_GXT4500P 0x21c
  18. #define PCI_DEVICE_ID_IBM_GXT6500P 0x21b
  19. #define PCI_DEVICE_ID_IBM_GXT4000P 0x16e
  20. #define PCI_DEVICE_ID_IBM_GXT6000P 0x170
  21. /* GXT4500P registers */
  22. /* Registers in PCI config space */
  23. #define CFG_ENDIAN0 0x40
  24. /* Misc control/status registers */
  25. #define STATUS 0x1000
  26. #define CTRL_REG0 0x1004
  27. #define CR0_HALT_DMA 0x4
  28. #define CR0_RASTER_RESET 0x8
  29. #define CR0_GEOM_RESET 0x10
  30. #define CR0_MEM_CTRLER_RESET 0x20
  31. /* Framebuffer control registers */
  32. #define FB_AB_CTRL 0x1100
  33. #define FB_CD_CTRL 0x1104
  34. #define FB_WID_CTRL 0x1108
  35. #define FB_Z_CTRL 0x110c
  36. #define FB_VGA_CTRL 0x1110
  37. #define REFRESH_AB_CTRL 0x1114
  38. #define REFRESH_CD_CTRL 0x1118
  39. #define FB_OVL_CTRL 0x111c
  40. #define FB_CTRL_TYPE 0x80000000
  41. #define FB_CTRL_WIDTH_MASK 0x007f0000
  42. #define FB_CTRL_WIDTH_SHIFT 16
  43. #define FB_CTRL_START_SEG_MASK 0x00003fff
  44. #define REFRESH_START 0x1098
  45. #define REFRESH_SIZE 0x109c
  46. /* "Direct" framebuffer access registers */
  47. #define DFA_FB_A 0x11e0
  48. #define DFA_FB_B 0x11e4
  49. #define DFA_FB_C 0x11e8
  50. #define DFA_FB_D 0x11ec
  51. #define DFA_FB_ENABLE 0x80000000
  52. #define DFA_FB_BASE_MASK 0x03f00000
  53. #define DFA_FB_STRIDE_1k 0x00000000
  54. #define DFA_FB_STRIDE_2k 0x00000010
  55. #define DFA_FB_STRIDE_4k 0x00000020
  56. #define DFA_PIX_8BIT 0x00000000
  57. #define DFA_PIX_16BIT_565 0x00000001
  58. #define DFA_PIX_16BIT_1555 0x00000002
  59. #define DFA_PIX_24BIT 0x00000004
  60. #define DFA_PIX_32BIT 0x00000005
  61. /* maps DFA_PIX_* to pixel size in bytes */
  62. static const unsigned char pixsize[] = {
  63. 1, 2, 2, 2, 4, 4
  64. };
  65. /* Display timing generator registers */
  66. #define DTG_CONTROL 0x1900
  67. #define DTG_CTL_SCREEN_REFRESH 2
  68. #define DTG_CTL_ENABLE 1
  69. #define DTG_HORIZ_EXTENT 0x1904
  70. #define DTG_HORIZ_DISPLAY 0x1908
  71. #define DTG_HSYNC_START 0x190c
  72. #define DTG_HSYNC_END 0x1910
  73. #define DTG_HSYNC_END_COMP 0x1914
  74. #define DTG_VERT_EXTENT 0x1918
  75. #define DTG_VERT_DISPLAY 0x191c
  76. #define DTG_VSYNC_START 0x1920
  77. #define DTG_VSYNC_END 0x1924
  78. #define DTG_VERT_SHORT 0x1928
  79. /* PLL/RAMDAC registers */
  80. #define DISP_CTL 0x402c
  81. #define DISP_CTL_OFF 2
  82. #define SYNC_CTL 0x4034
  83. #define SYNC_CTL_SYNC_ON_RGB 1
  84. #define SYNC_CTL_SYNC_OFF 2
  85. #define SYNC_CTL_HSYNC_INV 8
  86. #define SYNC_CTL_VSYNC_INV 0x10
  87. #define SYNC_CTL_HSYNC_OFF 0x20
  88. #define SYNC_CTL_VSYNC_OFF 0x40
  89. #define PLL_M 0x4040
  90. #define PLL_N 0x4044
  91. #define PLL_POSTDIV 0x4048
  92. #define PLL_C 0x404c
  93. /* Hardware cursor */
  94. #define CURSOR_X 0x4078
  95. #define CURSOR_Y 0x407c
  96. #define CURSOR_HOTSPOT 0x4080
  97. #define CURSOR_MODE 0x4084
  98. #define CURSOR_MODE_OFF 0
  99. #define CURSOR_MODE_4BPP 1
  100. #define CURSOR_PIXMAP 0x5000
  101. #define CURSOR_CMAP 0x7400
  102. /* Window attribute table */
  103. #define WAT_FMT 0x4100
  104. #define WAT_FMT_24BIT 0
  105. #define WAT_FMT_16BIT_565 1
  106. #define WAT_FMT_16BIT_1555 2
  107. #define WAT_FMT_32BIT 3 /* 0 vs. 3 is a guess */
  108. #define WAT_FMT_8BIT_332 9
  109. #define WAT_FMT_8BIT 0xa
  110. #define WAT_FMT_NO_CMAP 4 /* ORd in to other values */
  111. #define WAT_CMAP_OFFSET 0x4104 /* 4-bit value gets << 6 */
  112. #define WAT_CTRL 0x4108
  113. #define WAT_CTRL_SEL_B 1 /* select B buffer if 1 */
  114. #define WAT_CTRL_NO_INC 2
  115. #define WAT_GAMMA_CTRL 0x410c
  116. #define WAT_GAMMA_DISABLE 1 /* disables gamma cmap */
  117. #define WAT_OVL_CTRL 0x430c /* controls overlay */
  118. /* Indexed by DFA_PIX_* values */
  119. static const unsigned char watfmt[] = {
  120. WAT_FMT_8BIT, WAT_FMT_16BIT_565, WAT_FMT_16BIT_1555, 0,
  121. WAT_FMT_24BIT, WAT_FMT_32BIT
  122. };
  123. /* Colormap array; 1k entries of 4 bytes each */
  124. #define CMAP 0x6000
  125. #define readreg(par, reg) readl((par)->regs + (reg))
  126. #define writereg(par, reg, val) writel((val), (par)->regs + (reg))
  127. struct gxt4500_par {
  128. void __iomem *regs;
  129. int wc_cookie;
  130. int pixfmt; /* pixel format, see DFA_PIX_* values */
  131. /* PLL parameters */
  132. int refclk_ps; /* ref clock period in picoseconds */
  133. int pll_m; /* ref clock divisor */
  134. int pll_n; /* VCO divisor */
  135. int pll_pd1; /* first post-divisor */
  136. int pll_pd2; /* second post-divisor */
  137. u32 pseudo_palette[16]; /* used in color blits */
  138. };
  139. /* mode requested by user */
  140. static char *mode_option;
  141. /* default mode: 1280x1024 @ 60 Hz, 8 bpp */
  142. static const struct fb_videomode defaultmode = {
  143. .refresh = 60,
  144. .xres = 1280,
  145. .yres = 1024,
  146. .pixclock = 9295,
  147. .left_margin = 248,
  148. .right_margin = 48,
  149. .upper_margin = 38,
  150. .lower_margin = 1,
  151. .hsync_len = 112,
  152. .vsync_len = 3,
  153. .vmode = FB_VMODE_NONINTERLACED
  154. };
  155. /* List of supported cards */
  156. enum gxt_cards {
  157. GXT4500P,
  158. GXT6500P,
  159. GXT4000P,
  160. GXT6000P
  161. };
  162. /* Card-specific information */
  163. static const struct cardinfo {
  164. int refclk_ps; /* period of PLL reference clock in ps */
  165. const char *cardname;
  166. } cardinfo[] = {
  167. [GXT4500P] = { .refclk_ps = 9259, .cardname = "IBM GXT4500P" },
  168. [GXT6500P] = { .refclk_ps = 9259, .cardname = "IBM GXT6500P" },
  169. [GXT4000P] = { .refclk_ps = 40000, .cardname = "IBM GXT4000P" },
  170. [GXT6000P] = { .refclk_ps = 40000, .cardname = "IBM GXT6000P" },
  171. };
  172. /*
  173. * The refclk and VCO dividers appear to use a linear feedback shift
  174. * register, which gets reloaded when it reaches a terminal value, at
  175. * which point the divider output is toggled. Thus one can obtain
  176. * whatever divisor is required by putting the appropriate value into
  177. * the reload register. For a divisor of N, one puts the value from
  178. * the LFSR sequence that comes N-1 places before the terminal value
  179. * into the reload register.
  180. */
  181. static const unsigned char mdivtab[] = {
  182. /* 1 */ 0x3f, 0x00, 0x20, 0x10, 0x28, 0x14, 0x2a, 0x15, 0x0a,
  183. /* 10 */ 0x25, 0x32, 0x19, 0x0c, 0x26, 0x13, 0x09, 0x04, 0x22, 0x11,
  184. /* 20 */ 0x08, 0x24, 0x12, 0x29, 0x34, 0x1a, 0x2d, 0x36, 0x1b, 0x0d,
  185. /* 30 */ 0x06, 0x23, 0x31, 0x38, 0x1c, 0x2e, 0x17, 0x0b, 0x05, 0x02,
  186. /* 40 */ 0x21, 0x30, 0x18, 0x2c, 0x16, 0x2b, 0x35, 0x3a, 0x1d, 0x0e,
  187. /* 50 */ 0x27, 0x33, 0x39, 0x3c, 0x1e, 0x2f, 0x37, 0x3b, 0x3d, 0x3e,
  188. /* 60 */ 0x1f, 0x0f, 0x07, 0x03, 0x01,
  189. };
  190. static const unsigned char ndivtab[] = {
  191. /* 2 */ 0x00, 0x80, 0xc0, 0xe0, 0xf0, 0x78, 0xbc, 0x5e,
  192. /* 10 */ 0x2f, 0x17, 0x0b, 0x85, 0xc2, 0xe1, 0x70, 0x38, 0x9c, 0x4e,
  193. /* 20 */ 0xa7, 0xd3, 0xe9, 0xf4, 0xfa, 0xfd, 0xfe, 0x7f, 0xbf, 0xdf,
  194. /* 30 */ 0xef, 0x77, 0x3b, 0x1d, 0x8e, 0xc7, 0xe3, 0x71, 0xb8, 0xdc,
  195. /* 40 */ 0x6e, 0xb7, 0x5b, 0x2d, 0x16, 0x8b, 0xc5, 0xe2, 0xf1, 0xf8,
  196. /* 50 */ 0xfc, 0x7e, 0x3f, 0x9f, 0xcf, 0x67, 0xb3, 0xd9, 0x6c, 0xb6,
  197. /* 60 */ 0xdb, 0x6d, 0x36, 0x9b, 0x4d, 0x26, 0x13, 0x89, 0xc4, 0x62,
  198. /* 70 */ 0xb1, 0xd8, 0xec, 0xf6, 0xfb, 0x7d, 0xbe, 0x5f, 0xaf, 0x57,
  199. /* 80 */ 0x2b, 0x95, 0x4a, 0x25, 0x92, 0x49, 0xa4, 0x52, 0x29, 0x94,
  200. /* 90 */ 0xca, 0x65, 0xb2, 0x59, 0x2c, 0x96, 0xcb, 0xe5, 0xf2, 0x79,
  201. /* 100 */ 0x3c, 0x1e, 0x0f, 0x07, 0x83, 0x41, 0x20, 0x90, 0x48, 0x24,
  202. /* 110 */ 0x12, 0x09, 0x84, 0x42, 0xa1, 0x50, 0x28, 0x14, 0x8a, 0x45,
  203. /* 120 */ 0xa2, 0xd1, 0xe8, 0x74, 0xba, 0xdd, 0xee, 0xf7, 0x7b, 0x3d,
  204. /* 130 */ 0x9e, 0x4f, 0x27, 0x93, 0xc9, 0xe4, 0x72, 0x39, 0x1c, 0x0e,
  205. /* 140 */ 0x87, 0xc3, 0x61, 0x30, 0x18, 0x8c, 0xc6, 0x63, 0x31, 0x98,
  206. /* 150 */ 0xcc, 0xe6, 0x73, 0xb9, 0x5c, 0x2e, 0x97, 0x4b, 0xa5, 0xd2,
  207. /* 160 */ 0x69,
  208. };
  209. static int calc_pll(int period_ps, struct gxt4500_par *par)
  210. {
  211. int m, n, pdiv1, pdiv2, postdiv;
  212. int pll_period, best_error, t, intf;
  213. /* only deal with range 5MHz - 300MHz */
  214. if (period_ps < 3333 || period_ps > 200000)
  215. return -1;
  216. best_error = 1000000;
  217. for (pdiv1 = 1; pdiv1 <= 8; ++pdiv1) {
  218. for (pdiv2 = 1; pdiv2 <= pdiv1; ++pdiv2) {
  219. postdiv = pdiv1 * pdiv2;
  220. pll_period = DIV_ROUND_UP(period_ps, postdiv);
  221. /* keep pll in range 350..600 MHz */
  222. if (pll_period < 1666 || pll_period > 2857)
  223. continue;
  224. for (m = 1; m <= 64; ++m) {
  225. intf = m * par->refclk_ps;
  226. if (intf > 500000)
  227. break;
  228. n = intf * postdiv / period_ps;
  229. if (n < 3 || n > 160)
  230. continue;
  231. t = par->refclk_ps * m * postdiv / n;
  232. t -= period_ps;
  233. if (t >= 0 && t < best_error) {
  234. par->pll_m = m;
  235. par->pll_n = n;
  236. par->pll_pd1 = pdiv1;
  237. par->pll_pd2 = pdiv2;
  238. best_error = t;
  239. }
  240. }
  241. }
  242. }
  243. if (best_error == 1000000)
  244. return -1;
  245. return 0;
  246. }
  247. static int calc_pixclock(struct gxt4500_par *par)
  248. {
  249. return par->refclk_ps * par->pll_m * par->pll_pd1 * par->pll_pd2
  250. / par->pll_n;
  251. }
  252. static int gxt4500_var_to_par(struct fb_var_screeninfo *var,
  253. struct gxt4500_par *par)
  254. {
  255. if (var->xres + var->xoffset > var->xres_virtual ||
  256. var->yres + var->yoffset > var->yres_virtual ||
  257. var->xres_virtual > 4096)
  258. return -EINVAL;
  259. if ((var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
  260. return -EINVAL;
  261. if (calc_pll(var->pixclock, par) < 0)
  262. return -EINVAL;
  263. switch (var->bits_per_pixel) {
  264. case 32:
  265. if (var->transp.length)
  266. par->pixfmt = DFA_PIX_32BIT;
  267. else
  268. par->pixfmt = DFA_PIX_24BIT;
  269. break;
  270. case 24:
  271. par->pixfmt = DFA_PIX_24BIT;
  272. break;
  273. case 16:
  274. if (var->green.length == 5)
  275. par->pixfmt = DFA_PIX_16BIT_1555;
  276. else
  277. par->pixfmt = DFA_PIX_16BIT_565;
  278. break;
  279. case 8:
  280. par->pixfmt = DFA_PIX_8BIT;
  281. break;
  282. default:
  283. return -EINVAL;
  284. }
  285. return 0;
  286. }
  287. static const struct fb_bitfield eightbits = {0, 8};
  288. static const struct fb_bitfield nobits = {0, 0};
  289. static void gxt4500_unpack_pixfmt(struct fb_var_screeninfo *var,
  290. int pixfmt)
  291. {
  292. var->bits_per_pixel = pixsize[pixfmt] * 8;
  293. var->red = eightbits;
  294. var->green = eightbits;
  295. var->blue = eightbits;
  296. var->transp = nobits;
  297. switch (pixfmt) {
  298. case DFA_PIX_16BIT_565:
  299. var->red.length = 5;
  300. var->green.length = 6;
  301. var->blue.length = 5;
  302. break;
  303. case DFA_PIX_16BIT_1555:
  304. var->red.length = 5;
  305. var->green.length = 5;
  306. var->blue.length = 5;
  307. var->transp.length = 1;
  308. break;
  309. case DFA_PIX_32BIT:
  310. var->transp.length = 8;
  311. break;
  312. }
  313. if (pixfmt != DFA_PIX_8BIT) {
  314. var->blue.offset = 0;
  315. var->green.offset = var->blue.length;
  316. var->red.offset = var->green.offset + var->green.length;
  317. if (var->transp.length)
  318. var->transp.offset =
  319. var->red.offset + var->red.length;
  320. }
  321. }
  322. static int gxt4500_check_var(struct fb_var_screeninfo *var,
  323. struct fb_info *info)
  324. {
  325. struct gxt4500_par par;
  326. int err;
  327. par = *(struct gxt4500_par *)info->par;
  328. err = gxt4500_var_to_par(var, &par);
  329. if (!err) {
  330. var->pixclock = calc_pixclock(&par);
  331. gxt4500_unpack_pixfmt(var, par.pixfmt);
  332. }
  333. return err;
  334. }
  335. static int gxt4500_set_par(struct fb_info *info)
  336. {
  337. struct gxt4500_par *par = info->par;
  338. struct fb_var_screeninfo *var = &info->var;
  339. int err;
  340. u32 ctrlreg, tmp;
  341. unsigned int dfa_ctl, pixfmt, stride;
  342. unsigned int wid_tiles, i;
  343. unsigned int prefetch_pix, htot;
  344. struct gxt4500_par save_par;
  345. save_par = *par;
  346. err = gxt4500_var_to_par(var, par);
  347. if (err) {
  348. *par = save_par;
  349. return err;
  350. }
  351. /* turn off DTG for now */
  352. ctrlreg = readreg(par, DTG_CONTROL);
  353. ctrlreg &= ~(DTG_CTL_ENABLE | DTG_CTL_SCREEN_REFRESH);
  354. writereg(par, DTG_CONTROL, ctrlreg);
  355. /* set PLL registers */
  356. tmp = readreg(par, PLL_C) & ~0x7f;
  357. if (par->pll_n < 38)
  358. tmp |= 0x29;
  359. if (par->pll_n < 69)
  360. tmp |= 0x35;
  361. else if (par->pll_n < 100)
  362. tmp |= 0x76;
  363. else
  364. tmp |= 0x7e;
  365. writereg(par, PLL_C, tmp);
  366. writereg(par, PLL_M, mdivtab[par->pll_m - 1]);
  367. writereg(par, PLL_N, ndivtab[par->pll_n - 2]);
  368. tmp = ((8 - par->pll_pd2) << 3) | (8 - par->pll_pd1);
  369. if (par->pll_pd1 == 8 || par->pll_pd2 == 8) {
  370. /* work around erratum */
  371. writereg(par, PLL_POSTDIV, tmp | 0x9);
  372. udelay(1);
  373. }
  374. writereg(par, PLL_POSTDIV, tmp);
  375. msleep(20);
  376. /* turn off hardware cursor */
  377. writereg(par, CURSOR_MODE, CURSOR_MODE_OFF);
  378. /* reset raster engine */
  379. writereg(par, CTRL_REG0, CR0_RASTER_RESET | (CR0_RASTER_RESET << 16));
  380. udelay(10);
  381. writereg(par, CTRL_REG0, CR0_RASTER_RESET << 16);
  382. /* set display timing generator registers */
  383. htot = var->xres + var->left_margin + var->right_margin +
  384. var->hsync_len;
  385. writereg(par, DTG_HORIZ_EXTENT, htot - 1);
  386. writereg(par, DTG_HORIZ_DISPLAY, var->xres - 1);
  387. writereg(par, DTG_HSYNC_START, var->xres + var->right_margin - 1);
  388. writereg(par, DTG_HSYNC_END,
  389. var->xres + var->right_margin + var->hsync_len - 1);
  390. writereg(par, DTG_HSYNC_END_COMP,
  391. var->xres + var->right_margin + var->hsync_len - 1);
  392. writereg(par, DTG_VERT_EXTENT,
  393. var->yres + var->upper_margin + var->lower_margin +
  394. var->vsync_len - 1);
  395. writereg(par, DTG_VERT_DISPLAY, var->yres - 1);
  396. writereg(par, DTG_VSYNC_START, var->yres + var->lower_margin - 1);
  397. writereg(par, DTG_VSYNC_END,
  398. var->yres + var->lower_margin + var->vsync_len - 1);
  399. prefetch_pix = 3300000 / var->pixclock;
  400. if (prefetch_pix >= htot)
  401. prefetch_pix = htot - 1;
  402. writereg(par, DTG_VERT_SHORT, htot - prefetch_pix - 1);
  403. ctrlreg |= DTG_CTL_ENABLE | DTG_CTL_SCREEN_REFRESH;
  404. writereg(par, DTG_CONTROL, ctrlreg);
  405. /* calculate stride in DFA aperture */
  406. if (var->xres_virtual > 2048) {
  407. stride = 4096;
  408. dfa_ctl = DFA_FB_STRIDE_4k;
  409. } else if (var->xres_virtual > 1024) {
  410. stride = 2048;
  411. dfa_ctl = DFA_FB_STRIDE_2k;
  412. } else {
  413. stride = 1024;
  414. dfa_ctl = DFA_FB_STRIDE_1k;
  415. }
  416. /* Set up framebuffer definition */
  417. wid_tiles = (var->xres_virtual + 63) >> 6;
  418. /* XXX add proper FB allocation here someday */
  419. writereg(par, FB_AB_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0);
  420. writereg(par, REFRESH_AB_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0);
  421. writereg(par, FB_CD_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0);
  422. writereg(par, REFRESH_CD_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0);
  423. writereg(par, REFRESH_START, (var->xoffset << 16) | var->yoffset);
  424. writereg(par, REFRESH_SIZE, (var->xres << 16) | var->yres);
  425. /* Set up framebuffer access by CPU */
  426. pixfmt = par->pixfmt;
  427. dfa_ctl |= DFA_FB_ENABLE | pixfmt;
  428. writereg(par, DFA_FB_A, dfa_ctl);
  429. /*
  430. * Set up window attribute table.
  431. * We set all WAT entries the same so it doesn't matter what the
  432. * window ID (WID) plane contains.
  433. */
  434. for (i = 0; i < 32; ++i) {
  435. writereg(par, WAT_FMT + (i << 4), watfmt[pixfmt]);
  436. writereg(par, WAT_CMAP_OFFSET + (i << 4), 0);
  437. writereg(par, WAT_CTRL + (i << 4), 0);
  438. writereg(par, WAT_GAMMA_CTRL + (i << 4), WAT_GAMMA_DISABLE);
  439. }
  440. /* Set sync polarity etc. */
  441. ctrlreg = readreg(par, SYNC_CTL) &
  442. ~(SYNC_CTL_SYNC_ON_RGB | SYNC_CTL_HSYNC_INV |
  443. SYNC_CTL_VSYNC_INV);
  444. if (var->sync & FB_SYNC_ON_GREEN)
  445. ctrlreg |= SYNC_CTL_SYNC_ON_RGB;
  446. if (!(var->sync & FB_SYNC_HOR_HIGH_ACT))
  447. ctrlreg |= SYNC_CTL_HSYNC_INV;
  448. if (!(var->sync & FB_SYNC_VERT_HIGH_ACT))
  449. ctrlreg |= SYNC_CTL_VSYNC_INV;
  450. writereg(par, SYNC_CTL, ctrlreg);
  451. info->fix.line_length = stride * pixsize[pixfmt];
  452. info->fix.visual = (pixfmt == DFA_PIX_8BIT)? FB_VISUAL_PSEUDOCOLOR:
  453. FB_VISUAL_DIRECTCOLOR;
  454. return 0;
  455. }
  456. static int gxt4500_setcolreg(unsigned int reg, unsigned int red,
  457. unsigned int green, unsigned int blue,
  458. unsigned int transp, struct fb_info *info)
  459. {
  460. u32 cmap_entry;
  461. struct gxt4500_par *par = info->par;
  462. if (reg > 1023)
  463. return 1;
  464. cmap_entry = ((transp & 0xff00) << 16) | ((red & 0xff00) << 8) |
  465. (green & 0xff00) | (blue >> 8);
  466. writereg(par, CMAP + reg * 4, cmap_entry);
  467. if (reg < 16 && par->pixfmt != DFA_PIX_8BIT) {
  468. u32 *pal = info->pseudo_palette;
  469. u32 val = reg;
  470. switch (par->pixfmt) {
  471. case DFA_PIX_16BIT_565:
  472. val |= (reg << 11) | (reg << 5);
  473. break;
  474. case DFA_PIX_16BIT_1555:
  475. val |= (reg << 10) | (reg << 5);
  476. break;
  477. case DFA_PIX_32BIT:
  478. val |= (reg << 24);
  479. fallthrough;
  480. case DFA_PIX_24BIT:
  481. val |= (reg << 16) | (reg << 8);
  482. break;
  483. }
  484. pal[reg] = val;
  485. }
  486. return 0;
  487. }
  488. static int gxt4500_pan_display(struct fb_var_screeninfo *var,
  489. struct fb_info *info)
  490. {
  491. struct gxt4500_par *par = info->par;
  492. if (var->xoffset & 7)
  493. return -EINVAL;
  494. if (var->xoffset + info->var.xres > info->var.xres_virtual ||
  495. var->yoffset + info->var.yres > info->var.yres_virtual)
  496. return -EINVAL;
  497. writereg(par, REFRESH_START, (var->xoffset << 16) | var->yoffset);
  498. return 0;
  499. }
  500. static int gxt4500_blank(int blank, struct fb_info *info)
  501. {
  502. struct gxt4500_par *par = info->par;
  503. int ctrl, dctl;
  504. ctrl = readreg(par, SYNC_CTL);
  505. ctrl &= ~(SYNC_CTL_SYNC_OFF | SYNC_CTL_HSYNC_OFF | SYNC_CTL_VSYNC_OFF);
  506. dctl = readreg(par, DISP_CTL);
  507. dctl |= DISP_CTL_OFF;
  508. switch (blank) {
  509. case FB_BLANK_UNBLANK:
  510. dctl &= ~DISP_CTL_OFF;
  511. break;
  512. case FB_BLANK_POWERDOWN:
  513. ctrl |= SYNC_CTL_SYNC_OFF;
  514. break;
  515. case FB_BLANK_HSYNC_SUSPEND:
  516. ctrl |= SYNC_CTL_HSYNC_OFF;
  517. break;
  518. case FB_BLANK_VSYNC_SUSPEND:
  519. ctrl |= SYNC_CTL_VSYNC_OFF;
  520. break;
  521. default: ;
  522. }
  523. writereg(par, SYNC_CTL, ctrl);
  524. writereg(par, DISP_CTL, dctl);
  525. return 0;
  526. }
  527. static const struct fb_fix_screeninfo gxt4500_fix = {
  528. .id = "IBM GXT4500P",
  529. .type = FB_TYPE_PACKED_PIXELS,
  530. .visual = FB_VISUAL_PSEUDOCOLOR,
  531. .xpanstep = 8,
  532. .ypanstep = 1,
  533. .mmio_len = 0x20000,
  534. };
  535. static const struct fb_ops gxt4500_ops = {
  536. .owner = THIS_MODULE,
  537. .fb_check_var = gxt4500_check_var,
  538. .fb_set_par = gxt4500_set_par,
  539. .fb_setcolreg = gxt4500_setcolreg,
  540. .fb_pan_display = gxt4500_pan_display,
  541. .fb_blank = gxt4500_blank,
  542. .fb_fillrect = cfb_fillrect,
  543. .fb_copyarea = cfb_copyarea,
  544. .fb_imageblit = cfb_imageblit,
  545. };
  546. /* PCI functions */
  547. static int gxt4500_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  548. {
  549. int err;
  550. unsigned long reg_phys, fb_phys;
  551. struct gxt4500_par *par;
  552. struct fb_info *info;
  553. struct fb_var_screeninfo var;
  554. enum gxt_cards cardtype;
  555. err = aperture_remove_conflicting_pci_devices(pdev, "gxt4500fb");
  556. if (err)
  557. return err;
  558. err = pci_enable_device(pdev);
  559. if (err) {
  560. dev_err(&pdev->dev, "gxt4500: cannot enable PCI device: %d\n",
  561. err);
  562. return err;
  563. }
  564. reg_phys = pci_resource_start(pdev, 0);
  565. if (!request_mem_region(reg_phys, pci_resource_len(pdev, 0),
  566. "gxt4500 regs")) {
  567. dev_err(&pdev->dev, "gxt4500: cannot get registers\n");
  568. goto err_nodev;
  569. }
  570. fb_phys = pci_resource_start(pdev, 1);
  571. if (!request_mem_region(fb_phys, pci_resource_len(pdev, 1),
  572. "gxt4500 FB")) {
  573. dev_err(&pdev->dev, "gxt4500: cannot get framebuffer\n");
  574. goto err_free_regs;
  575. }
  576. info = framebuffer_alloc(sizeof(struct gxt4500_par), &pdev->dev);
  577. if (!info)
  578. goto err_free_fb;
  579. par = info->par;
  580. cardtype = ent->driver_data;
  581. par->refclk_ps = cardinfo[cardtype].refclk_ps;
  582. info->fix = gxt4500_fix;
  583. strscpy(info->fix.id, cardinfo[cardtype].cardname,
  584. sizeof(info->fix.id));
  585. info->pseudo_palette = par->pseudo_palette;
  586. info->fix.mmio_start = reg_phys;
  587. par->regs = pci_ioremap_bar(pdev, 0);
  588. if (!par->regs) {
  589. dev_err(&pdev->dev, "gxt4500: cannot map registers\n");
  590. goto err_free_all;
  591. }
  592. info->fix.smem_start = fb_phys;
  593. info->fix.smem_len = pci_resource_len(pdev, 1);
  594. info->screen_base = pci_ioremap_wc_bar(pdev, 1);
  595. if (!info->screen_base) {
  596. dev_err(&pdev->dev, "gxt4500: cannot map framebuffer\n");
  597. goto err_unmap_regs;
  598. }
  599. pci_set_drvdata(pdev, info);
  600. par->wc_cookie = arch_phys_wc_add(info->fix.smem_start,
  601. info->fix.smem_len);
  602. #ifdef __BIG_ENDIAN
  603. /* Set byte-swapping for DFA aperture for all pixel sizes */
  604. pci_write_config_dword(pdev, CFG_ENDIAN0, 0x333300);
  605. #else /* __LITTLE_ENDIAN */
  606. /* not sure what this means but fgl23 driver does that */
  607. pci_write_config_dword(pdev, CFG_ENDIAN0, 0x2300);
  608. /* pci_write_config_dword(pdev, CFG_ENDIAN0 + 4, 0x400000);*/
  609. pci_write_config_dword(pdev, CFG_ENDIAN0 + 8, 0x98530000);
  610. #endif
  611. info->fbops = &gxt4500_ops;
  612. info->flags = FBINFO_FLAG_DEFAULT | FBINFO_HWACCEL_XPAN |
  613. FBINFO_HWACCEL_YPAN;
  614. err = fb_alloc_cmap(&info->cmap, 256, 0);
  615. if (err) {
  616. dev_err(&pdev->dev, "gxt4500: cannot allocate cmap\n");
  617. goto err_unmap_all;
  618. }
  619. gxt4500_blank(FB_BLANK_UNBLANK, info);
  620. if (!fb_find_mode(&var, info, mode_option, NULL, 0, &defaultmode, 8)) {
  621. dev_err(&pdev->dev, "gxt4500: cannot find valid video mode\n");
  622. goto err_free_cmap;
  623. }
  624. info->var = var;
  625. if (gxt4500_set_par(info)) {
  626. printk(KERN_ERR "gxt4500: cannot set video mode\n");
  627. goto err_free_cmap;
  628. }
  629. if (register_framebuffer(info) < 0) {
  630. dev_err(&pdev->dev, "gxt4500: cannot register framebuffer\n");
  631. goto err_free_cmap;
  632. }
  633. fb_info(info, "%s frame buffer device\n", info->fix.id);
  634. return 0;
  635. err_free_cmap:
  636. fb_dealloc_cmap(&info->cmap);
  637. err_unmap_all:
  638. iounmap(info->screen_base);
  639. err_unmap_regs:
  640. iounmap(par->regs);
  641. err_free_all:
  642. framebuffer_release(info);
  643. err_free_fb:
  644. release_mem_region(fb_phys, pci_resource_len(pdev, 1));
  645. err_free_regs:
  646. release_mem_region(reg_phys, pci_resource_len(pdev, 0));
  647. err_nodev:
  648. return -ENODEV;
  649. }
  650. static void gxt4500_remove(struct pci_dev *pdev)
  651. {
  652. struct fb_info *info = pci_get_drvdata(pdev);
  653. struct gxt4500_par *par;
  654. if (!info)
  655. return;
  656. par = info->par;
  657. unregister_framebuffer(info);
  658. arch_phys_wc_del(par->wc_cookie);
  659. fb_dealloc_cmap(&info->cmap);
  660. iounmap(par->regs);
  661. iounmap(info->screen_base);
  662. release_mem_region(pci_resource_start(pdev, 0),
  663. pci_resource_len(pdev, 0));
  664. release_mem_region(pci_resource_start(pdev, 1),
  665. pci_resource_len(pdev, 1));
  666. framebuffer_release(info);
  667. }
  668. /* supported chipsets */
  669. static const struct pci_device_id gxt4500_pci_tbl[] = {
  670. { PCI_DEVICE(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_GXT4500P),
  671. .driver_data = GXT4500P },
  672. { PCI_DEVICE(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_GXT6500P),
  673. .driver_data = GXT6500P },
  674. { PCI_DEVICE(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_GXT4000P),
  675. .driver_data = GXT4000P },
  676. { PCI_DEVICE(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_GXT6000P),
  677. .driver_data = GXT6000P },
  678. { 0 }
  679. };
  680. MODULE_DEVICE_TABLE(pci, gxt4500_pci_tbl);
  681. static struct pci_driver gxt4500_driver = {
  682. .name = "gxt4500",
  683. .id_table = gxt4500_pci_tbl,
  684. .probe = gxt4500_probe,
  685. .remove = gxt4500_remove,
  686. };
  687. static int gxt4500_init(void)
  688. {
  689. #ifndef MODULE
  690. if (fb_get_options("gxt4500", &mode_option))
  691. return -ENODEV;
  692. #endif
  693. return pci_register_driver(&gxt4500_driver);
  694. }
  695. module_init(gxt4500_init);
  696. static void __exit gxt4500_exit(void)
  697. {
  698. pci_unregister_driver(&gxt4500_driver);
  699. }
  700. module_exit(gxt4500_exit);
  701. MODULE_AUTHOR("Paul Mackerras <[email protected]>");
  702. MODULE_DESCRIPTION("FBDev driver for IBM GXT4500P/6500P and GXT4000P/6000P");
  703. MODULE_LICENSE("GPL");
  704. module_param(mode_option, charp, 0);
  705. MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\"");