display_gx1.h 4.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * drivers/video/geode/display_gx1.h
  4. * -- Geode GX1 display controller
  5. *
  6. * Copyright (C) 2005 Arcom Control Systems Ltd.
  7. *
  8. * Based on AMD's original 2.4 driver:
  9. * Copyright (C) 2004 Advanced Micro Devices, Inc.
  10. */
  11. #ifndef __DISPLAY_GX1_H__
  12. #define __DISPLAY_GX1_H__
  13. unsigned gx1_gx_base(void);
  14. int gx1_frame_buffer_size(void);
  15. extern const struct geode_dc_ops gx1_dc_ops;
  16. /* GX1 configuration I/O registers */
  17. #define CONFIG_CCR3 0xc3
  18. # define CONFIG_CCR3_MAPEN 0x10
  19. #define CONFIG_GCR 0xb8
  20. /* Memory controller registers */
  21. #define MC_BANK_CFG 0x08
  22. # define MC_BCFG_DIMM0_SZ_MASK 0x00000700
  23. # define MC_BCFG_DIMM0_PG_SZ_MASK 0x00000070
  24. # define MC_BCFG_DIMM0_PG_SZ_NO_DIMM 0x00000070
  25. #define MC_GBASE_ADD 0x14
  26. # define MC_GADD_GBADD_MASK 0x000003ff
  27. /* Display controller registers */
  28. #define DC_PAL_ADDRESS 0x70
  29. #define DC_PAL_DATA 0x74
  30. #define DC_UNLOCK 0x00
  31. # define DC_UNLOCK_CODE 0x00004758
  32. #define DC_GENERAL_CFG 0x04
  33. # define DC_GCFG_DFLE 0x00000001
  34. # define DC_GCFG_CURE 0x00000002
  35. # define DC_GCFG_VCLK_DIV 0x00000004
  36. # define DC_GCFG_PLNO 0x00000004
  37. # define DC_GCFG_PPC 0x00000008
  38. # define DC_GCFG_CMPE 0x00000010
  39. # define DC_GCFG_DECE 0x00000020
  40. # define DC_GCFG_DCLK_MASK 0x000000C0
  41. # define DC_GCFG_DCLK_DIV_1 0x00000080
  42. # define DC_GCFG_DFHPSL_MASK 0x00000F00
  43. # define DC_GCFG_DFHPSL_POS 8
  44. # define DC_GCFG_DFHPEL_MASK 0x0000F000
  45. # define DC_GCFG_DFHPEL_POS 12
  46. # define DC_GCFG_CIM_MASK 0x00030000
  47. # define DC_GCFG_CIM_POS 16
  48. # define DC_GCFG_FDTY 0x00040000
  49. # define DC_GCFG_RTPM 0x00080000
  50. # define DC_GCFG_DAC_RS_MASK 0x00700000
  51. # define DC_GCFG_DAC_RS_POS 20
  52. # define DC_GCFG_CKWR 0x00800000
  53. # define DC_GCFG_LDBL 0x01000000
  54. # define DC_GCFG_DIAG 0x02000000
  55. # define DC_GCFG_CH4S 0x04000000
  56. # define DC_GCFG_SSLC 0x08000000
  57. # define DC_GCFG_VIDE 0x10000000
  58. # define DC_GCFG_VRDY 0x20000000
  59. # define DC_GCFG_DPCK 0x40000000
  60. # define DC_GCFG_DDCK 0x80000000
  61. #define DC_TIMING_CFG 0x08
  62. # define DC_TCFG_FPPE 0x00000001
  63. # define DC_TCFG_HSYE 0x00000002
  64. # define DC_TCFG_VSYE 0x00000004
  65. # define DC_TCFG_BLKE 0x00000008
  66. # define DC_TCFG_DDCK 0x00000010
  67. # define DC_TCFG_TGEN 0x00000020
  68. # define DC_TCFG_VIEN 0x00000040
  69. # define DC_TCFG_BLNK 0x00000080
  70. # define DC_TCFG_CHSP 0x00000100
  71. # define DC_TCFG_CVSP 0x00000200
  72. # define DC_TCFG_FHSP 0x00000400
  73. # define DC_TCFG_FVSP 0x00000800
  74. # define DC_TCFG_FCEN 0x00001000
  75. # define DC_TCFG_CDCE 0x00002000
  76. # define DC_TCFG_PLNR 0x00002000
  77. # define DC_TCFG_INTL 0x00004000
  78. # define DC_TCFG_PXDB 0x00008000
  79. # define DC_TCFG_BKRT 0x00010000
  80. # define DC_TCFG_PSD_MASK 0x000E0000
  81. # define DC_TCFG_PSD_POS 17
  82. # define DC_TCFG_DDCI 0x08000000
  83. # define DC_TCFG_SENS 0x10000000
  84. # define DC_TCFG_DNA 0x20000000
  85. # define DC_TCFG_VNA 0x40000000
  86. # define DC_TCFG_VINT 0x80000000
  87. #define DC_OUTPUT_CFG 0x0C
  88. # define DC_OCFG_8BPP 0x00000001
  89. # define DC_OCFG_555 0x00000002
  90. # define DC_OCFG_PCKE 0x00000004
  91. # define DC_OCFG_FRME 0x00000008
  92. # define DC_OCFG_DITE 0x00000010
  93. # define DC_OCFG_2PXE 0x00000020
  94. # define DC_OCFG_2XCK 0x00000040
  95. # define DC_OCFG_2IND 0x00000080
  96. # define DC_OCFG_34ADD 0x00000100
  97. # define DC_OCFG_FRMS 0x00000200
  98. # define DC_OCFG_CKSL 0x00000400
  99. # define DC_OCFG_PRMP 0x00000800
  100. # define DC_OCFG_PDEL 0x00001000
  101. # define DC_OCFG_PDEH 0x00002000
  102. # define DC_OCFG_CFRW 0x00004000
  103. # define DC_OCFG_DIAG 0x00008000
  104. #define DC_FB_ST_OFFSET 0x10
  105. #define DC_CB_ST_OFFSET 0x14
  106. #define DC_CURS_ST_OFFSET 0x18
  107. #define DC_ICON_ST_OFFSET 0x1C
  108. #define DC_VID_ST_OFFSET 0x20
  109. #define DC_LINE_DELTA 0x24
  110. #define DC_BUF_SIZE 0x28
  111. #define DC_H_TIMING_1 0x30
  112. #define DC_H_TIMING_2 0x34
  113. #define DC_H_TIMING_3 0x38
  114. #define DC_FP_H_TIMING 0x3C
  115. #define DC_V_TIMING_1 0x40
  116. #define DC_V_TIMING_2 0x44
  117. #define DC_V_TIMING_3 0x48
  118. #define DC_FP_V_TIMING 0x4C
  119. #define DC_CURSOR_X 0x50
  120. #define DC_ICON_X 0x54
  121. #define DC_V_LINE_CNT 0x54
  122. #define DC_CURSOR_Y 0x58
  123. #define DC_ICON_Y 0x5C
  124. #define DC_SS_LINE_CMP 0x5C
  125. #define DC_CURSOR_COLOR 0x60
  126. #define DC_ICON_COLOR 0x64
  127. #define DC_BORDER_COLOR 0x68
  128. #define DC_PAL_ADDRESS 0x70
  129. #define DC_PAL_DATA 0x74
  130. #define DC_DFIFO_DIAG 0x78
  131. #define DC_CFIFO_DIAG 0x7C
  132. #endif /* !__DISPLAY_GX1_H__ */