phy-qcom-emu.c 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2014-2018, 2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/platform_device.h>
  8. #include <linux/slab.h>
  9. #include <linux/io.h>
  10. #include <linux/of.h>
  11. #include <linux/delay.h>
  12. #include <linux/usb/phy.h>
  13. /* QSCRATCH registers */
  14. #define HS_PHY_CTRL_REG 0x10
  15. #define SW_SESSVLD_SEL BIT(28)
  16. /* HSPHY registers */
  17. #define HS2_LOCAL_RESET_REG_ADDR 0x04
  18. #define HS2_CLK_STATUS_ADDR 0x10
  19. #define HS2_CLK_STATUS_SEL_ADDR 0x14
  20. #define HS2_USB30_CTRL_ADDR 0x34
  21. #define HS2_USB30_PHY_POWER_OFF BIT(25)
  22. struct qcusb_emu_phy {
  23. struct usb_phy phy;
  24. struct device *dev;
  25. void __iomem *base;
  26. void __iomem *qscratch_base;
  27. int *emu_init_seq;
  28. int emu_init_seq_len;
  29. };
  30. static int qcusb_emu_phy_init(struct usb_phy *phy)
  31. {
  32. struct qcusb_emu_phy *qphy = container_of(phy,
  33. struct qcusb_emu_phy, phy);
  34. u32 tmp;
  35. int i;
  36. /* reset everything */
  37. writel_relaxed(0xffffffff, qphy->base + HS2_LOCAL_RESET_REG_ADDR);
  38. usleep_range(10000, 12000);
  39. /* power down HS phy */
  40. tmp = readl_relaxed(qphy->base + HS2_USB30_CTRL_ADDR) |
  41. HS2_USB30_PHY_POWER_OFF;
  42. writel_relaxed(tmp, qphy->base + HS2_USB30_CTRL_ADDR);
  43. usleep_range(10000, 12000);
  44. /* power up HS phy */
  45. tmp = readl_relaxed(qphy->base + HS2_USB30_CTRL_ADDR) &
  46. (~HS2_USB30_PHY_POWER_OFF);
  47. writel_relaxed(tmp, qphy->base + HS2_USB30_CTRL_ADDR);
  48. usleep_range(10000, 12000);
  49. writel_relaxed(0xfffffff3, qphy->base + HS2_LOCAL_RESET_REG_ADDR);
  50. usleep_range(10000, 12000);
  51. /* put phy out of reset */
  52. writel_relaxed(0xfffffff0, qphy->base + HS2_LOCAL_RESET_REG_ADDR);
  53. usleep_range(10000, 12000);
  54. /* selection of HS phy clock MMCM value */
  55. for (i = 0; i < qphy->emu_init_seq_len; i = i+2) {
  56. dev_dbg(phy->dev, "write 0x%02x to 0x%02x\n",
  57. qphy->emu_init_seq[i], qphy->emu_init_seq[i+1]);
  58. writel_relaxed(qphy->emu_init_seq[i],
  59. qphy->base + qphy->emu_init_seq[i+1]);
  60. /* 10ms to ensure write propagates across bus */
  61. usleep_range(10000, 12000);
  62. }
  63. /* clear other reset */
  64. writel_relaxed(0x0, qphy->base + HS2_LOCAL_RESET_REG_ADDR);
  65. usleep_range(10000, 12000);
  66. /* clock select to read UTMI/ULPI clock */
  67. writel_relaxed(0x9, qphy->base + HS2_CLK_STATUS_SEL_ADDR);
  68. usleep_range(10000, 12000);
  69. dev_info(phy->dev, "PHY UTMI/ULPI CLK frequency:%d MHz\n",
  70. (readl_relaxed(qphy->base + HS2_CLK_STATUS_ADDR) / 1000));
  71. if (qphy->qscratch_base) {
  72. /* Use UTMI VBUS signal from HW */
  73. tmp = readl_relaxed(qphy->qscratch_base + HS_PHY_CTRL_REG);
  74. tmp &= ~SW_SESSVLD_SEL;
  75. writel_relaxed(tmp, qphy->qscratch_base + HS_PHY_CTRL_REG);
  76. }
  77. return 0;
  78. }
  79. static int qcusb_emu_phy_probe(struct platform_device *pdev)
  80. {
  81. struct device *dev = &pdev->dev;
  82. struct qcusb_emu_phy *qphy;
  83. struct resource *res;
  84. int ret, size;
  85. qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
  86. if (!qphy)
  87. return -ENOMEM;
  88. qphy->phy.dev = dev;
  89. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  90. qphy->base = devm_ioremap_resource(dev, res);
  91. if (IS_ERR(qphy->base))
  92. return PTR_ERR(qphy->base);
  93. of_get_property(dev->of_node, "qcom,emu-init-seq", &size);
  94. if (!size) {
  95. dev_err(dev, "emu-init-seq not specified\n");
  96. return -EINVAL;
  97. }
  98. qphy->emu_init_seq = devm_kzalloc(dev, size, GFP_KERNEL);
  99. if (!qphy->emu_init_seq)
  100. return -ENOMEM;
  101. qphy->emu_init_seq_len = (size / sizeof(*qphy->emu_init_seq));
  102. if (qphy->emu_init_seq_len % 2) {
  103. dev_err(dev, "invalid emu_init_seq_len, must be in <data,addr> pairs\n");
  104. return -EINVAL;
  105. }
  106. ret = of_property_read_u32_array(dev->of_node, "qcom,emu-init-seq",
  107. qphy->emu_init_seq, qphy->emu_init_seq_len);
  108. if (ret) {
  109. dev_err(dev, "could not read emu-init-seq, returned %d\n", ret);
  110. return ret;
  111. }
  112. platform_set_drvdata(pdev, qphy);
  113. qphy->phy.label = "qcom-usb-emu-phy";
  114. qphy->phy.init = qcusb_emu_phy_init;
  115. qphy->phy.type = USB_PHY_TYPE_USB2;
  116. ret = usb_add_phy_dev(&qphy->phy);
  117. if (ret)
  118. return ret;
  119. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  120. "qscratch_base");
  121. if (res) {
  122. qphy->qscratch_base = devm_ioremap(dev, res->start,
  123. resource_size(res));
  124. if (IS_ERR(qphy->qscratch_base)) {
  125. dev_dbg(dev, "error mapping qscratch\n");
  126. qphy->qscratch_base = NULL;
  127. }
  128. }
  129. return 0;
  130. }
  131. static int qcusb_emu_phy_remove(struct platform_device *pdev)
  132. {
  133. struct qcusb_emu_phy *qcphy = platform_get_drvdata(pdev);
  134. usb_remove_phy(&qcphy->phy);
  135. return 0;
  136. }
  137. static const struct of_device_id emu_phy_dt_ids[] = {
  138. { .compatible = "qcom,usb-emu-phy" },
  139. { }
  140. };
  141. MODULE_DEVICE_TABLE(of, emu_phy_dt_ids);
  142. static struct platform_driver qcusb_emu_phy_driver = {
  143. .probe = qcusb_emu_phy_probe,
  144. .remove = qcusb_emu_phy_remove,
  145. .driver = {
  146. .name = "usb_emu_phy",
  147. .of_match_table = emu_phy_dt_ids,
  148. },
  149. };
  150. module_platform_driver(qcusb_emu_phy_driver);
  151. MODULE_DESCRIPTION("Qualcomm Technologies, Inc. USB Emulation PHY driver");
  152. MODULE_LICENSE("GPL v2");