eeprom.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Thunderbolt driver - eeprom access
  4. *
  5. * Copyright (c) 2014 Andreas Noever <[email protected]>
  6. * Copyright (C) 2018, Intel Corporation
  7. */
  8. #include <linux/crc32.h>
  9. #include <linux/delay.h>
  10. #include <linux/property.h>
  11. #include <linux/slab.h>
  12. #include "tb.h"
  13. /*
  14. * tb_eeprom_ctl_write() - write control word
  15. */
  16. static int tb_eeprom_ctl_write(struct tb_switch *sw, struct tb_eeprom_ctl *ctl)
  17. {
  18. return tb_sw_write(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + ROUTER_CS_4, 1);
  19. }
  20. /*
  21. * tb_eeprom_ctl_write() - read control word
  22. */
  23. static int tb_eeprom_ctl_read(struct tb_switch *sw, struct tb_eeprom_ctl *ctl)
  24. {
  25. return tb_sw_read(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + ROUTER_CS_4, 1);
  26. }
  27. enum tb_eeprom_transfer {
  28. TB_EEPROM_IN,
  29. TB_EEPROM_OUT,
  30. };
  31. /*
  32. * tb_eeprom_active - enable rom access
  33. *
  34. * WARNING: Always disable access after usage. Otherwise the controller will
  35. * fail to reprobe.
  36. */
  37. static int tb_eeprom_active(struct tb_switch *sw, bool enable)
  38. {
  39. struct tb_eeprom_ctl ctl;
  40. int res = tb_eeprom_ctl_read(sw, &ctl);
  41. if (res)
  42. return res;
  43. if (enable) {
  44. ctl.bit_banging_enable = 1;
  45. res = tb_eeprom_ctl_write(sw, &ctl);
  46. if (res)
  47. return res;
  48. ctl.fl_cs = 0;
  49. return tb_eeprom_ctl_write(sw, &ctl);
  50. } else {
  51. ctl.fl_cs = 1;
  52. res = tb_eeprom_ctl_write(sw, &ctl);
  53. if (res)
  54. return res;
  55. ctl.bit_banging_enable = 0;
  56. return tb_eeprom_ctl_write(sw, &ctl);
  57. }
  58. }
  59. /*
  60. * tb_eeprom_transfer - transfer one bit
  61. *
  62. * If TB_EEPROM_IN is passed, then the bit can be retrieved from ctl->fl_do.
  63. * If TB_EEPROM_OUT is passed, then ctl->fl_di will be written.
  64. */
  65. static int tb_eeprom_transfer(struct tb_switch *sw, struct tb_eeprom_ctl *ctl,
  66. enum tb_eeprom_transfer direction)
  67. {
  68. int res;
  69. if (direction == TB_EEPROM_OUT) {
  70. res = tb_eeprom_ctl_write(sw, ctl);
  71. if (res)
  72. return res;
  73. }
  74. ctl->fl_sk = 1;
  75. res = tb_eeprom_ctl_write(sw, ctl);
  76. if (res)
  77. return res;
  78. if (direction == TB_EEPROM_IN) {
  79. res = tb_eeprom_ctl_read(sw, ctl);
  80. if (res)
  81. return res;
  82. }
  83. ctl->fl_sk = 0;
  84. return tb_eeprom_ctl_write(sw, ctl);
  85. }
  86. /*
  87. * tb_eeprom_out - write one byte to the bus
  88. */
  89. static int tb_eeprom_out(struct tb_switch *sw, u8 val)
  90. {
  91. struct tb_eeprom_ctl ctl;
  92. int i;
  93. int res = tb_eeprom_ctl_read(sw, &ctl);
  94. if (res)
  95. return res;
  96. for (i = 0; i < 8; i++) {
  97. ctl.fl_di = val & 0x80;
  98. res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_OUT);
  99. if (res)
  100. return res;
  101. val <<= 1;
  102. }
  103. return 0;
  104. }
  105. /*
  106. * tb_eeprom_in - read one byte from the bus
  107. */
  108. static int tb_eeprom_in(struct tb_switch *sw, u8 *val)
  109. {
  110. struct tb_eeprom_ctl ctl;
  111. int i;
  112. int res = tb_eeprom_ctl_read(sw, &ctl);
  113. if (res)
  114. return res;
  115. *val = 0;
  116. for (i = 0; i < 8; i++) {
  117. *val <<= 1;
  118. res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_IN);
  119. if (res)
  120. return res;
  121. *val |= ctl.fl_do;
  122. }
  123. return 0;
  124. }
  125. /*
  126. * tb_eeprom_get_drom_offset - get drom offset within eeprom
  127. */
  128. static int tb_eeprom_get_drom_offset(struct tb_switch *sw, u16 *offset)
  129. {
  130. struct tb_cap_plug_events cap;
  131. int res;
  132. if (!sw->cap_plug_events) {
  133. tb_sw_warn(sw, "no TB_CAP_PLUG_EVENTS, cannot read eeprom\n");
  134. return -ENODEV;
  135. }
  136. res = tb_sw_read(sw, &cap, TB_CFG_SWITCH, sw->cap_plug_events,
  137. sizeof(cap) / 4);
  138. if (res)
  139. return res;
  140. if (!cap.eeprom_ctl.present || cap.eeprom_ctl.not_present) {
  141. tb_sw_warn(sw, "no NVM\n");
  142. return -ENODEV;
  143. }
  144. if (cap.drom_offset > 0xffff) {
  145. tb_sw_warn(sw, "drom offset is larger than 0xffff: %#x\n",
  146. cap.drom_offset);
  147. return -ENXIO;
  148. }
  149. *offset = cap.drom_offset;
  150. return 0;
  151. }
  152. /*
  153. * tb_eeprom_read_n - read count bytes from offset into val
  154. */
  155. static int tb_eeprom_read_n(struct tb_switch *sw, u16 offset, u8 *val,
  156. size_t count)
  157. {
  158. u16 drom_offset;
  159. int i, res;
  160. res = tb_eeprom_get_drom_offset(sw, &drom_offset);
  161. if (res)
  162. return res;
  163. offset += drom_offset;
  164. res = tb_eeprom_active(sw, true);
  165. if (res)
  166. return res;
  167. res = tb_eeprom_out(sw, 3);
  168. if (res)
  169. return res;
  170. res = tb_eeprom_out(sw, offset >> 8);
  171. if (res)
  172. return res;
  173. res = tb_eeprom_out(sw, offset);
  174. if (res)
  175. return res;
  176. for (i = 0; i < count; i++) {
  177. res = tb_eeprom_in(sw, val + i);
  178. if (res)
  179. return res;
  180. }
  181. return tb_eeprom_active(sw, false);
  182. }
  183. static u8 tb_crc8(u8 *data, int len)
  184. {
  185. int i, j;
  186. u8 val = 0xff;
  187. for (i = 0; i < len; i++) {
  188. val ^= data[i];
  189. for (j = 0; j < 8; j++)
  190. val = (val << 1) ^ ((val & 0x80) ? 7 : 0);
  191. }
  192. return val;
  193. }
  194. static u32 tb_crc32(void *data, size_t len)
  195. {
  196. return ~__crc32c_le(~0, data, len);
  197. }
  198. #define TB_DROM_DATA_START 13
  199. #define TB_DROM_HEADER_SIZE 22
  200. #define USB4_DROM_HEADER_SIZE 16
  201. struct tb_drom_header {
  202. /* BYTE 0 */
  203. u8 uid_crc8; /* checksum for uid */
  204. /* BYTES 1-8 */
  205. u64 uid;
  206. /* BYTES 9-12 */
  207. u32 data_crc32; /* checksum for data_len bytes starting at byte 13 */
  208. /* BYTE 13 */
  209. u8 device_rom_revision; /* should be <= 1 */
  210. u16 data_len:12;
  211. u8 reserved:4;
  212. /* BYTES 16-21 - Only for TBT DROM, nonexistent in USB4 DROM */
  213. u16 vendor_id;
  214. u16 model_id;
  215. u8 model_rev;
  216. u8 eeprom_rev;
  217. } __packed;
  218. enum tb_drom_entry_type {
  219. /* force unsigned to prevent "one-bit signed bitfield" warning */
  220. TB_DROM_ENTRY_GENERIC = 0U,
  221. TB_DROM_ENTRY_PORT,
  222. };
  223. struct tb_drom_entry_header {
  224. u8 len;
  225. u8 index:6;
  226. bool port_disabled:1; /* only valid if type is TB_DROM_ENTRY_PORT */
  227. enum tb_drom_entry_type type:1;
  228. } __packed;
  229. struct tb_drom_entry_generic {
  230. struct tb_drom_entry_header header;
  231. u8 data[];
  232. } __packed;
  233. struct tb_drom_entry_port {
  234. /* BYTES 0-1 */
  235. struct tb_drom_entry_header header;
  236. /* BYTE 2 */
  237. u8 dual_link_port_rid:4;
  238. u8 link_nr:1;
  239. u8 unknown1:2;
  240. bool has_dual_link_port:1;
  241. /* BYTE 3 */
  242. u8 dual_link_port_nr:6;
  243. u8 unknown2:2;
  244. /* BYTES 4 - 5 TODO decode */
  245. u8 micro2:4;
  246. u8 micro1:4;
  247. u8 micro3;
  248. /* BYTES 6-7, TODO: verify (find hardware that has these set) */
  249. u8 peer_port_rid:4;
  250. u8 unknown3:3;
  251. bool has_peer_port:1;
  252. u8 peer_port_nr:6;
  253. u8 unknown4:2;
  254. } __packed;
  255. /* USB4 product descriptor */
  256. struct tb_drom_entry_desc {
  257. struct tb_drom_entry_header header;
  258. u16 bcdUSBSpec;
  259. u16 idVendor;
  260. u16 idProduct;
  261. u16 bcdProductFWRevision;
  262. u32 TID;
  263. u8 productHWRevision;
  264. };
  265. /**
  266. * tb_drom_read_uid_only() - Read UID directly from DROM
  267. * @sw: Router whose UID to read
  268. * @uid: UID is placed here
  269. *
  270. * Does not use the cached copy in sw->drom. Used during resume to check switch
  271. * identity.
  272. */
  273. int tb_drom_read_uid_only(struct tb_switch *sw, u64 *uid)
  274. {
  275. u8 data[9];
  276. u8 crc;
  277. int res;
  278. /* read uid */
  279. res = tb_eeprom_read_n(sw, 0, data, 9);
  280. if (res)
  281. return res;
  282. crc = tb_crc8(data + 1, 8);
  283. if (crc != data[0]) {
  284. tb_sw_warn(sw, "uid crc8 mismatch (expected: %#x, got: %#x)\n",
  285. data[0], crc);
  286. return -EIO;
  287. }
  288. *uid = *(u64 *)(data+1);
  289. return 0;
  290. }
  291. static int tb_drom_parse_entry_generic(struct tb_switch *sw,
  292. struct tb_drom_entry_header *header)
  293. {
  294. const struct tb_drom_entry_generic *entry =
  295. (const struct tb_drom_entry_generic *)header;
  296. switch (header->index) {
  297. case 1:
  298. /* Length includes 2 bytes header so remove it before copy */
  299. sw->vendor_name = kstrndup(entry->data,
  300. header->len - sizeof(*header), GFP_KERNEL);
  301. if (!sw->vendor_name)
  302. return -ENOMEM;
  303. break;
  304. case 2:
  305. sw->device_name = kstrndup(entry->data,
  306. header->len - sizeof(*header), GFP_KERNEL);
  307. if (!sw->device_name)
  308. return -ENOMEM;
  309. break;
  310. case 9: {
  311. const struct tb_drom_entry_desc *desc =
  312. (const struct tb_drom_entry_desc *)entry;
  313. if (!sw->vendor && !sw->device) {
  314. sw->vendor = desc->idVendor;
  315. sw->device = desc->idProduct;
  316. }
  317. break;
  318. }
  319. }
  320. return 0;
  321. }
  322. static int tb_drom_parse_entry_port(struct tb_switch *sw,
  323. struct tb_drom_entry_header *header)
  324. {
  325. struct tb_port *port;
  326. int res;
  327. enum tb_port_type type;
  328. /*
  329. * Some DROMs list more ports than the controller actually has
  330. * so we skip those but allow the parser to continue.
  331. */
  332. if (header->index > sw->config.max_port_number) {
  333. dev_info_once(&sw->dev, "ignoring unnecessary extra entries in DROM\n");
  334. return 0;
  335. }
  336. port = &sw->ports[header->index];
  337. port->disabled = header->port_disabled;
  338. if (port->disabled)
  339. return 0;
  340. res = tb_port_read(port, &type, TB_CFG_PORT, 2, 1);
  341. if (res)
  342. return res;
  343. type &= 0xffffff;
  344. if (type == TB_TYPE_PORT) {
  345. struct tb_drom_entry_port *entry = (void *) header;
  346. if (header->len != sizeof(*entry)) {
  347. tb_sw_warn(sw,
  348. "port entry has size %#x (expected %#zx)\n",
  349. header->len, sizeof(struct tb_drom_entry_port));
  350. return -EIO;
  351. }
  352. port->link_nr = entry->link_nr;
  353. if (entry->has_dual_link_port)
  354. port->dual_link_port =
  355. &port->sw->ports[entry->dual_link_port_nr];
  356. }
  357. return 0;
  358. }
  359. /*
  360. * tb_drom_parse_entries - parse the linked list of drom entries
  361. *
  362. * Drom must have been copied to sw->drom.
  363. */
  364. static int tb_drom_parse_entries(struct tb_switch *sw, size_t header_size)
  365. {
  366. struct tb_drom_header *header = (void *) sw->drom;
  367. u16 pos = header_size;
  368. u16 drom_size = header->data_len + TB_DROM_DATA_START;
  369. int res;
  370. while (pos < drom_size) {
  371. struct tb_drom_entry_header *entry = (void *) (sw->drom + pos);
  372. if (pos + 1 == drom_size || pos + entry->len > drom_size
  373. || !entry->len) {
  374. tb_sw_warn(sw, "DROM buffer overrun\n");
  375. return -EILSEQ;
  376. }
  377. switch (entry->type) {
  378. case TB_DROM_ENTRY_GENERIC:
  379. res = tb_drom_parse_entry_generic(sw, entry);
  380. break;
  381. case TB_DROM_ENTRY_PORT:
  382. res = tb_drom_parse_entry_port(sw, entry);
  383. break;
  384. }
  385. if (res)
  386. return res;
  387. pos += entry->len;
  388. }
  389. return 0;
  390. }
  391. /*
  392. * tb_drom_copy_efi - copy drom supplied by EFI to sw->drom if present
  393. */
  394. static int tb_drom_copy_efi(struct tb_switch *sw, u16 *size)
  395. {
  396. struct device *dev = &sw->tb->nhi->pdev->dev;
  397. int len, res;
  398. len = device_property_count_u8(dev, "ThunderboltDROM");
  399. if (len < 0 || len < sizeof(struct tb_drom_header))
  400. return -EINVAL;
  401. sw->drom = kmalloc(len, GFP_KERNEL);
  402. if (!sw->drom)
  403. return -ENOMEM;
  404. res = device_property_read_u8_array(dev, "ThunderboltDROM", sw->drom,
  405. len);
  406. if (res)
  407. goto err;
  408. *size = ((struct tb_drom_header *)sw->drom)->data_len +
  409. TB_DROM_DATA_START;
  410. if (*size > len)
  411. goto err;
  412. return 0;
  413. err:
  414. kfree(sw->drom);
  415. sw->drom = NULL;
  416. return -EINVAL;
  417. }
  418. static int tb_drom_copy_nvm(struct tb_switch *sw, u16 *size)
  419. {
  420. u32 drom_offset;
  421. int ret;
  422. if (!sw->dma_port)
  423. return -ENODEV;
  424. ret = tb_sw_read(sw, &drom_offset, TB_CFG_SWITCH,
  425. sw->cap_plug_events + 12, 1);
  426. if (ret)
  427. return ret;
  428. if (!drom_offset)
  429. return -ENODEV;
  430. ret = dma_port_flash_read(sw->dma_port, drom_offset + 14, size,
  431. sizeof(*size));
  432. if (ret)
  433. return ret;
  434. /* Size includes CRC8 + UID + CRC32 */
  435. *size += 1 + 8 + 4;
  436. sw->drom = kzalloc(*size, GFP_KERNEL);
  437. if (!sw->drom)
  438. return -ENOMEM;
  439. ret = dma_port_flash_read(sw->dma_port, drom_offset, sw->drom, *size);
  440. if (ret)
  441. goto err_free;
  442. /*
  443. * Read UID from the minimal DROM because the one in NVM is just
  444. * a placeholder.
  445. */
  446. tb_drom_read_uid_only(sw, &sw->uid);
  447. return 0;
  448. err_free:
  449. kfree(sw->drom);
  450. sw->drom = NULL;
  451. return ret;
  452. }
  453. static int usb4_copy_host_drom(struct tb_switch *sw, u16 *size)
  454. {
  455. int ret;
  456. ret = usb4_switch_drom_read(sw, 14, size, sizeof(*size));
  457. if (ret)
  458. return ret;
  459. /* Size includes CRC8 + UID + CRC32 */
  460. *size += 1 + 8 + 4;
  461. sw->drom = kzalloc(*size, GFP_KERNEL);
  462. if (!sw->drom)
  463. return -ENOMEM;
  464. ret = usb4_switch_drom_read(sw, 0, sw->drom, *size);
  465. if (ret) {
  466. kfree(sw->drom);
  467. sw->drom = NULL;
  468. }
  469. return ret;
  470. }
  471. static int tb_drom_read_n(struct tb_switch *sw, u16 offset, u8 *val,
  472. size_t count)
  473. {
  474. if (tb_switch_is_usb4(sw))
  475. return usb4_switch_drom_read(sw, offset, val, count);
  476. return tb_eeprom_read_n(sw, offset, val, count);
  477. }
  478. static int tb_drom_parse(struct tb_switch *sw)
  479. {
  480. const struct tb_drom_header *header =
  481. (const struct tb_drom_header *)sw->drom;
  482. u32 crc;
  483. crc = tb_crc8((u8 *) &header->uid, 8);
  484. if (crc != header->uid_crc8) {
  485. tb_sw_warn(sw,
  486. "DROM UID CRC8 mismatch (expected: %#x, got: %#x)\n",
  487. header->uid_crc8, crc);
  488. return -EILSEQ;
  489. }
  490. if (!sw->uid)
  491. sw->uid = header->uid;
  492. sw->vendor = header->vendor_id;
  493. sw->device = header->model_id;
  494. crc = tb_crc32(sw->drom + TB_DROM_DATA_START, header->data_len);
  495. if (crc != header->data_crc32) {
  496. tb_sw_warn(sw,
  497. "DROM data CRC32 mismatch (expected: %#x, got: %#x), continuing\n",
  498. header->data_crc32, crc);
  499. }
  500. return tb_drom_parse_entries(sw, TB_DROM_HEADER_SIZE);
  501. }
  502. static int usb4_drom_parse(struct tb_switch *sw)
  503. {
  504. const struct tb_drom_header *header =
  505. (const struct tb_drom_header *)sw->drom;
  506. u32 crc;
  507. crc = tb_crc32(sw->drom + TB_DROM_DATA_START, header->data_len);
  508. if (crc != header->data_crc32) {
  509. tb_sw_warn(sw,
  510. "DROM data CRC32 mismatch (expected: %#x, got: %#x), aborting\n",
  511. header->data_crc32, crc);
  512. return -EINVAL;
  513. }
  514. return tb_drom_parse_entries(sw, USB4_DROM_HEADER_SIZE);
  515. }
  516. /**
  517. * tb_drom_read() - Copy DROM to sw->drom and parse it
  518. * @sw: Router whose DROM to read and parse
  519. *
  520. * This function reads router DROM and if successful parses the entries and
  521. * populates the fields in @sw accordingly. Can be called for any router
  522. * generation.
  523. *
  524. * Returns %0 in case of success and negative errno otherwise.
  525. */
  526. int tb_drom_read(struct tb_switch *sw)
  527. {
  528. u16 size;
  529. struct tb_drom_header *header;
  530. int res, retries = 1;
  531. if (sw->drom)
  532. return 0;
  533. if (tb_route(sw) == 0) {
  534. /*
  535. * Apple's NHI EFI driver supplies a DROM for the root switch
  536. * in a device property. Use it if available.
  537. */
  538. if (tb_drom_copy_efi(sw, &size) == 0)
  539. goto parse;
  540. /* Non-Apple hardware has the DROM as part of NVM */
  541. if (tb_drom_copy_nvm(sw, &size) == 0)
  542. goto parse;
  543. /*
  544. * USB4 hosts may support reading DROM through router
  545. * operations.
  546. */
  547. if (tb_switch_is_usb4(sw)) {
  548. usb4_switch_read_uid(sw, &sw->uid);
  549. if (!usb4_copy_host_drom(sw, &size))
  550. goto parse;
  551. } else {
  552. /*
  553. * The root switch contains only a dummy drom
  554. * (header only, no entries). Hardcode the
  555. * configuration here.
  556. */
  557. tb_drom_read_uid_only(sw, &sw->uid);
  558. }
  559. return 0;
  560. }
  561. res = tb_drom_read_n(sw, 14, (u8 *) &size, 2);
  562. if (res)
  563. return res;
  564. size &= 0x3ff;
  565. size += TB_DROM_DATA_START;
  566. tb_sw_dbg(sw, "reading drom (length: %#x)\n", size);
  567. if (size < sizeof(*header)) {
  568. tb_sw_warn(sw, "drom too small, aborting\n");
  569. return -EIO;
  570. }
  571. sw->drom = kzalloc(size, GFP_KERNEL);
  572. if (!sw->drom)
  573. return -ENOMEM;
  574. read:
  575. res = tb_drom_read_n(sw, 0, sw->drom, size);
  576. if (res)
  577. goto err;
  578. parse:
  579. header = (void *) sw->drom;
  580. if (header->data_len + TB_DROM_DATA_START != size) {
  581. tb_sw_warn(sw, "drom size mismatch\n");
  582. if (retries--) {
  583. msleep(100);
  584. goto read;
  585. }
  586. goto err;
  587. }
  588. tb_sw_dbg(sw, "DROM version: %d\n", header->device_rom_revision);
  589. switch (header->device_rom_revision) {
  590. case 3:
  591. res = usb4_drom_parse(sw);
  592. break;
  593. default:
  594. tb_sw_warn(sw, "DROM device_rom_revision %#x unknown\n",
  595. header->device_rom_revision);
  596. fallthrough;
  597. case 1:
  598. res = tb_drom_parse(sw);
  599. break;
  600. }
  601. /* If the DROM parsing fails, wait a moment and retry once */
  602. if (res == -EILSEQ && retries--) {
  603. tb_sw_warn(sw, "parsing DROM failed\n");
  604. msleep(100);
  605. goto read;
  606. }
  607. if (!res)
  608. return 0;
  609. err:
  610. kfree(sw->drom);
  611. sw->drom = NULL;
  612. return -EIO;
  613. }