main.c 30 KB

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  1. /*
  2. * Sonics Silicon Backplane
  3. * Subsystem core
  4. *
  5. * Copyright 2005, Broadcom Corporation
  6. * Copyright 2006, 2007, Michael Buesch <[email protected]>
  7. *
  8. * Licensed under the GNU/GPL. See COPYING for details.
  9. */
  10. #include "ssb_private.h"
  11. #include <linux/delay.h>
  12. #include <linux/io.h>
  13. #include <linux/module.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/ssb/ssb.h>
  16. #include <linux/ssb/ssb_regs.h>
  17. #include <linux/ssb/ssb_driver_gige.h>
  18. #include <linux/dma-mapping.h>
  19. #include <linux/pci.h>
  20. #include <linux/mmc/sdio_func.h>
  21. #include <linux/slab.h>
  22. #include <pcmcia/cistpl.h>
  23. #include <pcmcia/ds.h>
  24. MODULE_DESCRIPTION("Sonics Silicon Backplane driver");
  25. MODULE_LICENSE("GPL");
  26. /* Temporary list of yet-to-be-attached buses */
  27. static LIST_HEAD(attach_queue);
  28. /* List if running buses */
  29. static LIST_HEAD(buses);
  30. /* Software ID counter */
  31. static unsigned int next_busnumber;
  32. /* buses_mutes locks the two buslists and the next_busnumber.
  33. * Don't lock this directly, but use ssb_buses_[un]lock() below.
  34. */
  35. static DEFINE_MUTEX(buses_mutex);
  36. /* There are differences in the codeflow, if the bus is
  37. * initialized from early boot, as various needed services
  38. * are not available early. This is a mechanism to delay
  39. * these initializations to after early boot has finished.
  40. * It's also used to avoid mutex locking, as that's not
  41. * available and needed early.
  42. */
  43. static bool ssb_is_early_boot = 1;
  44. static void ssb_buses_lock(void);
  45. static void ssb_buses_unlock(void);
  46. #ifdef CONFIG_SSB_PCIHOST
  47. struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev)
  48. {
  49. struct ssb_bus *bus;
  50. ssb_buses_lock();
  51. list_for_each_entry(bus, &buses, list) {
  52. if (bus->bustype == SSB_BUSTYPE_PCI &&
  53. bus->host_pci == pdev)
  54. goto found;
  55. }
  56. bus = NULL;
  57. found:
  58. ssb_buses_unlock();
  59. return bus;
  60. }
  61. #endif /* CONFIG_SSB_PCIHOST */
  62. #ifdef CONFIG_SSB_PCMCIAHOST
  63. struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev)
  64. {
  65. struct ssb_bus *bus;
  66. ssb_buses_lock();
  67. list_for_each_entry(bus, &buses, list) {
  68. if (bus->bustype == SSB_BUSTYPE_PCMCIA &&
  69. bus->host_pcmcia == pdev)
  70. goto found;
  71. }
  72. bus = NULL;
  73. found:
  74. ssb_buses_unlock();
  75. return bus;
  76. }
  77. #endif /* CONFIG_SSB_PCMCIAHOST */
  78. int ssb_for_each_bus_call(unsigned long data,
  79. int (*func)(struct ssb_bus *bus, unsigned long data))
  80. {
  81. struct ssb_bus *bus;
  82. int res;
  83. ssb_buses_lock();
  84. list_for_each_entry(bus, &buses, list) {
  85. res = func(bus, data);
  86. if (res >= 0) {
  87. ssb_buses_unlock();
  88. return res;
  89. }
  90. }
  91. ssb_buses_unlock();
  92. return -ENODEV;
  93. }
  94. static struct ssb_device *ssb_device_get(struct ssb_device *dev)
  95. {
  96. if (dev)
  97. get_device(dev->dev);
  98. return dev;
  99. }
  100. static void ssb_device_put(struct ssb_device *dev)
  101. {
  102. if (dev)
  103. put_device(dev->dev);
  104. }
  105. static int ssb_device_resume(struct device *dev)
  106. {
  107. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  108. struct ssb_driver *ssb_drv;
  109. int err = 0;
  110. if (dev->driver) {
  111. ssb_drv = drv_to_ssb_drv(dev->driver);
  112. if (ssb_drv && ssb_drv->resume)
  113. err = ssb_drv->resume(ssb_dev);
  114. if (err)
  115. goto out;
  116. }
  117. out:
  118. return err;
  119. }
  120. static int ssb_device_suspend(struct device *dev, pm_message_t state)
  121. {
  122. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  123. struct ssb_driver *ssb_drv;
  124. int err = 0;
  125. if (dev->driver) {
  126. ssb_drv = drv_to_ssb_drv(dev->driver);
  127. if (ssb_drv && ssb_drv->suspend)
  128. err = ssb_drv->suspend(ssb_dev, state);
  129. if (err)
  130. goto out;
  131. }
  132. out:
  133. return err;
  134. }
  135. int ssb_bus_resume(struct ssb_bus *bus)
  136. {
  137. int err;
  138. /* Reset HW state information in memory, so that HW is
  139. * completely reinitialized.
  140. */
  141. bus->mapped_device = NULL;
  142. #ifdef CONFIG_SSB_DRIVER_PCICORE
  143. bus->pcicore.setup_done = 0;
  144. #endif
  145. err = ssb_bus_powerup(bus, 0);
  146. if (err)
  147. return err;
  148. err = ssb_pcmcia_hardware_setup(bus);
  149. if (err) {
  150. ssb_bus_may_powerdown(bus);
  151. return err;
  152. }
  153. ssb_chipco_resume(&bus->chipco);
  154. ssb_bus_may_powerdown(bus);
  155. return 0;
  156. }
  157. EXPORT_SYMBOL(ssb_bus_resume);
  158. int ssb_bus_suspend(struct ssb_bus *bus)
  159. {
  160. ssb_chipco_suspend(&bus->chipco);
  161. ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
  162. return 0;
  163. }
  164. EXPORT_SYMBOL(ssb_bus_suspend);
  165. #ifdef CONFIG_SSB_SPROM
  166. /** ssb_devices_freeze - Freeze all devices on the bus.
  167. *
  168. * After freezing no device driver will be handling a device
  169. * on this bus anymore. ssb_devices_thaw() must be called after
  170. * a successful freeze to reactivate the devices.
  171. *
  172. * @bus: The bus.
  173. * @ctx: Context structure. Pass this to ssb_devices_thaw().
  174. */
  175. int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx)
  176. {
  177. struct ssb_device *sdev;
  178. struct ssb_driver *sdrv;
  179. unsigned int i;
  180. memset(ctx, 0, sizeof(*ctx));
  181. ctx->bus = bus;
  182. WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen));
  183. for (i = 0; i < bus->nr_devices; i++) {
  184. sdev = ssb_device_get(&bus->devices[i]);
  185. if (!sdev->dev || !sdev->dev->driver ||
  186. !device_is_registered(sdev->dev)) {
  187. ssb_device_put(sdev);
  188. continue;
  189. }
  190. sdrv = drv_to_ssb_drv(sdev->dev->driver);
  191. if (WARN_ON(!sdrv->remove))
  192. continue;
  193. sdrv->remove(sdev);
  194. ctx->device_frozen[i] = 1;
  195. }
  196. return 0;
  197. }
  198. /** ssb_devices_thaw - Unfreeze all devices on the bus.
  199. *
  200. * This will re-attach the device drivers and re-init the devices.
  201. *
  202. * @ctx: The context structure from ssb_devices_freeze()
  203. */
  204. int ssb_devices_thaw(struct ssb_freeze_context *ctx)
  205. {
  206. struct ssb_bus *bus = ctx->bus;
  207. struct ssb_device *sdev;
  208. struct ssb_driver *sdrv;
  209. unsigned int i;
  210. int err, result = 0;
  211. for (i = 0; i < bus->nr_devices; i++) {
  212. if (!ctx->device_frozen[i])
  213. continue;
  214. sdev = &bus->devices[i];
  215. if (WARN_ON(!sdev->dev || !sdev->dev->driver))
  216. continue;
  217. sdrv = drv_to_ssb_drv(sdev->dev->driver);
  218. if (WARN_ON(!sdrv || !sdrv->probe))
  219. continue;
  220. err = sdrv->probe(sdev, &sdev->id);
  221. if (err) {
  222. dev_err(sdev->dev,
  223. "Failed to thaw device %s\n",
  224. dev_name(sdev->dev));
  225. result = err;
  226. }
  227. ssb_device_put(sdev);
  228. }
  229. return result;
  230. }
  231. #endif /* CONFIG_SSB_SPROM */
  232. static void ssb_device_shutdown(struct device *dev)
  233. {
  234. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  235. struct ssb_driver *ssb_drv;
  236. if (!dev->driver)
  237. return;
  238. ssb_drv = drv_to_ssb_drv(dev->driver);
  239. if (ssb_drv && ssb_drv->shutdown)
  240. ssb_drv->shutdown(ssb_dev);
  241. }
  242. static void ssb_device_remove(struct device *dev)
  243. {
  244. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  245. struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
  246. if (ssb_drv && ssb_drv->remove)
  247. ssb_drv->remove(ssb_dev);
  248. ssb_device_put(ssb_dev);
  249. }
  250. static int ssb_device_probe(struct device *dev)
  251. {
  252. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  253. struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
  254. int err = 0;
  255. ssb_device_get(ssb_dev);
  256. if (ssb_drv && ssb_drv->probe)
  257. err = ssb_drv->probe(ssb_dev, &ssb_dev->id);
  258. if (err)
  259. ssb_device_put(ssb_dev);
  260. return err;
  261. }
  262. static int ssb_match_devid(const struct ssb_device_id *tabid,
  263. const struct ssb_device_id *devid)
  264. {
  265. if ((tabid->vendor != devid->vendor) &&
  266. tabid->vendor != SSB_ANY_VENDOR)
  267. return 0;
  268. if ((tabid->coreid != devid->coreid) &&
  269. tabid->coreid != SSB_ANY_ID)
  270. return 0;
  271. if ((tabid->revision != devid->revision) &&
  272. tabid->revision != SSB_ANY_REV)
  273. return 0;
  274. return 1;
  275. }
  276. static int ssb_bus_match(struct device *dev, struct device_driver *drv)
  277. {
  278. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  279. struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv);
  280. const struct ssb_device_id *id;
  281. for (id = ssb_drv->id_table;
  282. id->vendor || id->coreid || id->revision;
  283. id++) {
  284. if (ssb_match_devid(id, &ssb_dev->id))
  285. return 1; /* found */
  286. }
  287. return 0;
  288. }
  289. static int ssb_device_uevent(struct device *dev, struct kobj_uevent_env *env)
  290. {
  291. struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
  292. if (!dev)
  293. return -ENODEV;
  294. return add_uevent_var(env,
  295. "MODALIAS=ssb:v%04Xid%04Xrev%02X",
  296. ssb_dev->id.vendor, ssb_dev->id.coreid,
  297. ssb_dev->id.revision);
  298. }
  299. #define ssb_config_attr(attrib, field, format_string) \
  300. static ssize_t \
  301. attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \
  302. { \
  303. return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \
  304. } \
  305. static DEVICE_ATTR_RO(attrib);
  306. ssb_config_attr(core_num, core_index, "%u\n")
  307. ssb_config_attr(coreid, id.coreid, "0x%04x\n")
  308. ssb_config_attr(vendor, id.vendor, "0x%04x\n")
  309. ssb_config_attr(revision, id.revision, "%u\n")
  310. ssb_config_attr(irq, irq, "%u\n")
  311. static ssize_t
  312. name_show(struct device *dev, struct device_attribute *attr, char *buf)
  313. {
  314. return sprintf(buf, "%s\n",
  315. ssb_core_name(dev_to_ssb_dev(dev)->id.coreid));
  316. }
  317. static DEVICE_ATTR_RO(name);
  318. static struct attribute *ssb_device_attrs[] = {
  319. &dev_attr_name.attr,
  320. &dev_attr_core_num.attr,
  321. &dev_attr_coreid.attr,
  322. &dev_attr_vendor.attr,
  323. &dev_attr_revision.attr,
  324. &dev_attr_irq.attr,
  325. NULL,
  326. };
  327. ATTRIBUTE_GROUPS(ssb_device);
  328. static struct bus_type ssb_bustype = {
  329. .name = "ssb",
  330. .match = ssb_bus_match,
  331. .probe = ssb_device_probe,
  332. .remove = ssb_device_remove,
  333. .shutdown = ssb_device_shutdown,
  334. .suspend = ssb_device_suspend,
  335. .resume = ssb_device_resume,
  336. .uevent = ssb_device_uevent,
  337. .dev_groups = ssb_device_groups,
  338. };
  339. static void ssb_buses_lock(void)
  340. {
  341. /* See the comment at the ssb_is_early_boot definition */
  342. if (!ssb_is_early_boot)
  343. mutex_lock(&buses_mutex);
  344. }
  345. static void ssb_buses_unlock(void)
  346. {
  347. /* See the comment at the ssb_is_early_boot definition */
  348. if (!ssb_is_early_boot)
  349. mutex_unlock(&buses_mutex);
  350. }
  351. static void ssb_devices_unregister(struct ssb_bus *bus)
  352. {
  353. struct ssb_device *sdev;
  354. int i;
  355. for (i = bus->nr_devices - 1; i >= 0; i--) {
  356. sdev = &(bus->devices[i]);
  357. if (sdev->dev)
  358. device_unregister(sdev->dev);
  359. }
  360. #ifdef CONFIG_SSB_EMBEDDED
  361. if (bus->bustype == SSB_BUSTYPE_SSB)
  362. platform_device_unregister(bus->watchdog);
  363. #endif
  364. }
  365. void ssb_bus_unregister(struct ssb_bus *bus)
  366. {
  367. int err;
  368. err = ssb_gpio_unregister(bus);
  369. if (err)
  370. pr_debug("Can not unregister GPIO driver: %i\n", err);
  371. ssb_buses_lock();
  372. ssb_devices_unregister(bus);
  373. list_del(&bus->list);
  374. ssb_buses_unlock();
  375. ssb_pcmcia_exit(bus);
  376. ssb_pci_exit(bus);
  377. ssb_iounmap(bus);
  378. }
  379. EXPORT_SYMBOL(ssb_bus_unregister);
  380. static void ssb_release_dev(struct device *dev)
  381. {
  382. struct __ssb_dev_wrapper *devwrap;
  383. devwrap = container_of(dev, struct __ssb_dev_wrapper, dev);
  384. kfree(devwrap);
  385. }
  386. static int ssb_devices_register(struct ssb_bus *bus)
  387. {
  388. struct ssb_device *sdev;
  389. struct device *dev;
  390. struct __ssb_dev_wrapper *devwrap;
  391. int i, err = 0;
  392. int dev_idx = 0;
  393. for (i = 0; i < bus->nr_devices; i++) {
  394. sdev = &(bus->devices[i]);
  395. /* We don't register SSB-system devices to the kernel,
  396. * as the drivers for them are built into SSB.
  397. */
  398. switch (sdev->id.coreid) {
  399. case SSB_DEV_CHIPCOMMON:
  400. case SSB_DEV_PCI:
  401. case SSB_DEV_PCIE:
  402. case SSB_DEV_PCMCIA:
  403. case SSB_DEV_MIPS:
  404. case SSB_DEV_MIPS_3302:
  405. case SSB_DEV_EXTIF:
  406. continue;
  407. }
  408. devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL);
  409. if (!devwrap) {
  410. err = -ENOMEM;
  411. goto error;
  412. }
  413. dev = &devwrap->dev;
  414. devwrap->sdev = sdev;
  415. dev->release = ssb_release_dev;
  416. dev->bus = &ssb_bustype;
  417. dev_set_name(dev, "ssb%u:%d", bus->busnumber, dev_idx);
  418. switch (bus->bustype) {
  419. case SSB_BUSTYPE_PCI:
  420. #ifdef CONFIG_SSB_PCIHOST
  421. sdev->irq = bus->host_pci->irq;
  422. dev->parent = &bus->host_pci->dev;
  423. sdev->dma_dev = dev->parent;
  424. #endif
  425. break;
  426. case SSB_BUSTYPE_PCMCIA:
  427. #ifdef CONFIG_SSB_PCMCIAHOST
  428. sdev->irq = bus->host_pcmcia->irq;
  429. dev->parent = &bus->host_pcmcia->dev;
  430. #endif
  431. break;
  432. case SSB_BUSTYPE_SDIO:
  433. #ifdef CONFIG_SSB_SDIOHOST
  434. dev->parent = &bus->host_sdio->dev;
  435. #endif
  436. break;
  437. case SSB_BUSTYPE_SSB:
  438. dev->dma_mask = &dev->coherent_dma_mask;
  439. sdev->dma_dev = dev;
  440. break;
  441. }
  442. sdev->dev = dev;
  443. err = device_register(dev);
  444. if (err) {
  445. pr_err("Could not register %s\n", dev_name(dev));
  446. /* Set dev to NULL to not unregister
  447. * dev on error unwinding.
  448. */
  449. sdev->dev = NULL;
  450. put_device(dev);
  451. goto error;
  452. }
  453. dev_idx++;
  454. }
  455. #ifdef CONFIG_SSB_DRIVER_MIPS
  456. if (bus->mipscore.pflash.present) {
  457. err = platform_device_register(&ssb_pflash_dev);
  458. if (err)
  459. pr_err("Error registering parallel flash\n");
  460. }
  461. #endif
  462. #ifdef CONFIG_SSB_SFLASH
  463. if (bus->mipscore.sflash.present) {
  464. err = platform_device_register(&ssb_sflash_dev);
  465. if (err)
  466. pr_err("Error registering serial flash\n");
  467. }
  468. #endif
  469. return 0;
  470. error:
  471. /* Unwind the already registered devices. */
  472. ssb_devices_unregister(bus);
  473. return err;
  474. }
  475. /* Needs ssb_buses_lock() */
  476. static int ssb_attach_queued_buses(void)
  477. {
  478. struct ssb_bus *bus, *n;
  479. int err = 0;
  480. int drop_them_all = 0;
  481. list_for_each_entry_safe(bus, n, &attach_queue, list) {
  482. if (drop_them_all) {
  483. list_del(&bus->list);
  484. continue;
  485. }
  486. /* Can't init the PCIcore in ssb_bus_register(), as that
  487. * is too early in boot for embedded systems
  488. * (no udelay() available). So do it here in attach stage.
  489. */
  490. err = ssb_bus_powerup(bus, 0);
  491. if (err)
  492. goto error;
  493. ssb_pcicore_init(&bus->pcicore);
  494. if (bus->bustype == SSB_BUSTYPE_SSB)
  495. ssb_watchdog_register(bus);
  496. err = ssb_gpio_init(bus);
  497. if (err == -ENOTSUPP)
  498. pr_debug("GPIO driver not activated\n");
  499. else if (err)
  500. pr_debug("Error registering GPIO driver: %i\n", err);
  501. ssb_bus_may_powerdown(bus);
  502. err = ssb_devices_register(bus);
  503. error:
  504. if (err) {
  505. drop_them_all = 1;
  506. list_del(&bus->list);
  507. continue;
  508. }
  509. list_move_tail(&bus->list, &buses);
  510. }
  511. return err;
  512. }
  513. static int ssb_fetch_invariants(struct ssb_bus *bus,
  514. ssb_invariants_func_t get_invariants)
  515. {
  516. struct ssb_init_invariants iv;
  517. int err;
  518. memset(&iv, 0, sizeof(iv));
  519. err = get_invariants(bus, &iv);
  520. if (err)
  521. goto out;
  522. memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo));
  523. memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom));
  524. bus->has_cardbus_slot = iv.has_cardbus_slot;
  525. out:
  526. return err;
  527. }
  528. static int __maybe_unused
  529. ssb_bus_register(struct ssb_bus *bus,
  530. ssb_invariants_func_t get_invariants,
  531. unsigned long baseaddr)
  532. {
  533. int err;
  534. spin_lock_init(&bus->bar_lock);
  535. INIT_LIST_HEAD(&bus->list);
  536. #ifdef CONFIG_SSB_EMBEDDED
  537. spin_lock_init(&bus->gpio_lock);
  538. #endif
  539. /* Powerup the bus */
  540. err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
  541. if (err)
  542. goto out;
  543. /* Init SDIO-host device (if any), before the scan */
  544. err = ssb_sdio_init(bus);
  545. if (err)
  546. goto err_disable_xtal;
  547. ssb_buses_lock();
  548. bus->busnumber = next_busnumber;
  549. /* Scan for devices (cores) */
  550. err = ssb_bus_scan(bus, baseaddr);
  551. if (err)
  552. goto err_sdio_exit;
  553. /* Init PCI-host device (if any) */
  554. err = ssb_pci_init(bus);
  555. if (err)
  556. goto err_unmap;
  557. /* Init PCMCIA-host device (if any) */
  558. err = ssb_pcmcia_init(bus);
  559. if (err)
  560. goto err_pci_exit;
  561. /* Initialize basic system devices (if available) */
  562. err = ssb_bus_powerup(bus, 0);
  563. if (err)
  564. goto err_pcmcia_exit;
  565. ssb_chipcommon_init(&bus->chipco);
  566. ssb_extif_init(&bus->extif);
  567. ssb_mipscore_init(&bus->mipscore);
  568. err = ssb_fetch_invariants(bus, get_invariants);
  569. if (err) {
  570. ssb_bus_may_powerdown(bus);
  571. goto err_pcmcia_exit;
  572. }
  573. ssb_bus_may_powerdown(bus);
  574. /* Queue it for attach.
  575. * See the comment at the ssb_is_early_boot definition.
  576. */
  577. list_add_tail(&bus->list, &attach_queue);
  578. if (!ssb_is_early_boot) {
  579. /* This is not early boot, so we must attach the bus now */
  580. err = ssb_attach_queued_buses();
  581. if (err)
  582. goto err_dequeue;
  583. }
  584. next_busnumber++;
  585. ssb_buses_unlock();
  586. out:
  587. return err;
  588. err_dequeue:
  589. list_del(&bus->list);
  590. err_pcmcia_exit:
  591. ssb_pcmcia_exit(bus);
  592. err_pci_exit:
  593. ssb_pci_exit(bus);
  594. err_unmap:
  595. ssb_iounmap(bus);
  596. err_sdio_exit:
  597. ssb_sdio_exit(bus);
  598. err_disable_xtal:
  599. ssb_buses_unlock();
  600. ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
  601. return err;
  602. }
  603. #ifdef CONFIG_SSB_PCIHOST
  604. int ssb_bus_pcibus_register(struct ssb_bus *bus, struct pci_dev *host_pci)
  605. {
  606. int err;
  607. bus->bustype = SSB_BUSTYPE_PCI;
  608. bus->host_pci = host_pci;
  609. bus->ops = &ssb_pci_ops;
  610. err = ssb_bus_register(bus, ssb_pci_get_invariants, 0);
  611. if (!err) {
  612. dev_info(&host_pci->dev,
  613. "Sonics Silicon Backplane found on PCI device %s\n",
  614. dev_name(&host_pci->dev));
  615. } else {
  616. dev_err(&host_pci->dev,
  617. "Failed to register PCI version of SSB with error %d\n",
  618. err);
  619. }
  620. return err;
  621. }
  622. #endif /* CONFIG_SSB_PCIHOST */
  623. #ifdef CONFIG_SSB_PCMCIAHOST
  624. int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
  625. struct pcmcia_device *pcmcia_dev,
  626. unsigned long baseaddr)
  627. {
  628. int err;
  629. bus->bustype = SSB_BUSTYPE_PCMCIA;
  630. bus->host_pcmcia = pcmcia_dev;
  631. bus->ops = &ssb_pcmcia_ops;
  632. err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr);
  633. if (!err) {
  634. dev_info(&pcmcia_dev->dev,
  635. "Sonics Silicon Backplane found on PCMCIA device %s\n",
  636. pcmcia_dev->devname);
  637. }
  638. return err;
  639. }
  640. #endif /* CONFIG_SSB_PCMCIAHOST */
  641. #ifdef CONFIG_SSB_SDIOHOST
  642. int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
  643. unsigned int quirks)
  644. {
  645. int err;
  646. bus->bustype = SSB_BUSTYPE_SDIO;
  647. bus->host_sdio = func;
  648. bus->ops = &ssb_sdio_ops;
  649. bus->quirks = quirks;
  650. err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0);
  651. if (!err) {
  652. dev_info(&func->dev,
  653. "Sonics Silicon Backplane found on SDIO device %s\n",
  654. sdio_func_id(func));
  655. }
  656. return err;
  657. }
  658. EXPORT_SYMBOL(ssb_bus_sdiobus_register);
  659. #endif /* CONFIG_SSB_PCMCIAHOST */
  660. #ifdef CONFIG_SSB_HOST_SOC
  661. int ssb_bus_host_soc_register(struct ssb_bus *bus, unsigned long baseaddr)
  662. {
  663. int err;
  664. bus->bustype = SSB_BUSTYPE_SSB;
  665. bus->ops = &ssb_host_soc_ops;
  666. err = ssb_bus_register(bus, ssb_host_soc_get_invariants, baseaddr);
  667. if (!err) {
  668. pr_info("Sonics Silicon Backplane found at address 0x%08lX\n",
  669. baseaddr);
  670. }
  671. return err;
  672. }
  673. #endif
  674. int __ssb_driver_register(struct ssb_driver *drv, struct module *owner)
  675. {
  676. drv->drv.name = drv->name;
  677. drv->drv.bus = &ssb_bustype;
  678. drv->drv.owner = owner;
  679. return driver_register(&drv->drv);
  680. }
  681. EXPORT_SYMBOL(__ssb_driver_register);
  682. void ssb_driver_unregister(struct ssb_driver *drv)
  683. {
  684. driver_unregister(&drv->drv);
  685. }
  686. EXPORT_SYMBOL(ssb_driver_unregister);
  687. void ssb_set_devtypedata(struct ssb_device *dev, void *data)
  688. {
  689. struct ssb_bus *bus = dev->bus;
  690. struct ssb_device *ent;
  691. int i;
  692. for (i = 0; i < bus->nr_devices; i++) {
  693. ent = &(bus->devices[i]);
  694. if (ent->id.vendor != dev->id.vendor)
  695. continue;
  696. if (ent->id.coreid != dev->id.coreid)
  697. continue;
  698. ent->devtypedata = data;
  699. }
  700. }
  701. EXPORT_SYMBOL(ssb_set_devtypedata);
  702. static u32 clkfactor_f6_resolve(u32 v)
  703. {
  704. /* map the magic values */
  705. switch (v) {
  706. case SSB_CHIPCO_CLK_F6_2:
  707. return 2;
  708. case SSB_CHIPCO_CLK_F6_3:
  709. return 3;
  710. case SSB_CHIPCO_CLK_F6_4:
  711. return 4;
  712. case SSB_CHIPCO_CLK_F6_5:
  713. return 5;
  714. case SSB_CHIPCO_CLK_F6_6:
  715. return 6;
  716. case SSB_CHIPCO_CLK_F6_7:
  717. return 7;
  718. }
  719. return 0;
  720. }
  721. /* Calculate the speed the backplane would run at a given set of clockcontrol values */
  722. u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m)
  723. {
  724. u32 n1, n2, clock, m1, m2, m3, mc;
  725. n1 = (n & SSB_CHIPCO_CLK_N1);
  726. n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT);
  727. switch (plltype) {
  728. case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
  729. if (m & SSB_CHIPCO_CLK_T6_MMASK)
  730. return SSB_CHIPCO_CLK_T6_M1;
  731. return SSB_CHIPCO_CLK_T6_M0;
  732. case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
  733. case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
  734. case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
  735. case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
  736. n1 = clkfactor_f6_resolve(n1);
  737. n2 += SSB_CHIPCO_CLK_F5_BIAS;
  738. break;
  739. case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */
  740. n1 += SSB_CHIPCO_CLK_T2_BIAS;
  741. n2 += SSB_CHIPCO_CLK_T2_BIAS;
  742. WARN_ON(!((n1 >= 2) && (n1 <= 7)));
  743. WARN_ON(!((n2 >= 5) && (n2 <= 23)));
  744. break;
  745. case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */
  746. return 100000000;
  747. default:
  748. WARN_ON(1);
  749. }
  750. switch (plltype) {
  751. case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
  752. case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
  753. clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2;
  754. break;
  755. default:
  756. clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2;
  757. }
  758. if (!clock)
  759. return 0;
  760. m1 = (m & SSB_CHIPCO_CLK_M1);
  761. m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT);
  762. m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT);
  763. mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT);
  764. switch (plltype) {
  765. case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
  766. case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
  767. case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
  768. case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
  769. m1 = clkfactor_f6_resolve(m1);
  770. if ((plltype == SSB_PLLTYPE_1) ||
  771. (plltype == SSB_PLLTYPE_3))
  772. m2 += SSB_CHIPCO_CLK_F5_BIAS;
  773. else
  774. m2 = clkfactor_f6_resolve(m2);
  775. m3 = clkfactor_f6_resolve(m3);
  776. switch (mc) {
  777. case SSB_CHIPCO_CLK_MC_BYPASS:
  778. return clock;
  779. case SSB_CHIPCO_CLK_MC_M1:
  780. return (clock / m1);
  781. case SSB_CHIPCO_CLK_MC_M1M2:
  782. return (clock / (m1 * m2));
  783. case SSB_CHIPCO_CLK_MC_M1M2M3:
  784. return (clock / (m1 * m2 * m3));
  785. case SSB_CHIPCO_CLK_MC_M1M3:
  786. return (clock / (m1 * m3));
  787. }
  788. return 0;
  789. case SSB_PLLTYPE_2:
  790. m1 += SSB_CHIPCO_CLK_T2_BIAS;
  791. m2 += SSB_CHIPCO_CLK_T2M2_BIAS;
  792. m3 += SSB_CHIPCO_CLK_T2_BIAS;
  793. WARN_ON(!((m1 >= 2) && (m1 <= 7)));
  794. WARN_ON(!((m2 >= 3) && (m2 <= 10)));
  795. WARN_ON(!((m3 >= 2) && (m3 <= 7)));
  796. if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP))
  797. clock /= m1;
  798. if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP))
  799. clock /= m2;
  800. if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP))
  801. clock /= m3;
  802. return clock;
  803. default:
  804. WARN_ON(1);
  805. }
  806. return 0;
  807. }
  808. /* Get the current speed the backplane is running at */
  809. u32 ssb_clockspeed(struct ssb_bus *bus)
  810. {
  811. u32 rate;
  812. u32 plltype;
  813. u32 clkctl_n, clkctl_m;
  814. if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
  815. return ssb_pmu_get_controlclock(&bus->chipco);
  816. if (ssb_extif_available(&bus->extif))
  817. ssb_extif_get_clockcontrol(&bus->extif, &plltype,
  818. &clkctl_n, &clkctl_m);
  819. else if (bus->chipco.dev)
  820. ssb_chipco_get_clockcontrol(&bus->chipco, &plltype,
  821. &clkctl_n, &clkctl_m);
  822. else
  823. return 0;
  824. if (bus->chip_id == 0x5365) {
  825. rate = 100000000;
  826. } else {
  827. rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
  828. if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
  829. rate /= 2;
  830. }
  831. return rate;
  832. }
  833. EXPORT_SYMBOL(ssb_clockspeed);
  834. static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev)
  835. {
  836. u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
  837. /* The REJECT bit seems to be different for Backplane rev 2.3 */
  838. switch (rev) {
  839. case SSB_IDLOW_SSBREV_22:
  840. case SSB_IDLOW_SSBREV_24:
  841. case SSB_IDLOW_SSBREV_26:
  842. return SSB_TMSLOW_REJECT;
  843. case SSB_IDLOW_SSBREV_23:
  844. return SSB_TMSLOW_REJECT_23;
  845. case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
  846. case SSB_IDLOW_SSBREV_27: /* same here */
  847. return SSB_TMSLOW_REJECT; /* this is a guess */
  848. case SSB_IDLOW_SSBREV:
  849. break;
  850. default:
  851. WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
  852. }
  853. return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
  854. }
  855. int ssb_device_is_enabled(struct ssb_device *dev)
  856. {
  857. u32 val;
  858. u32 reject;
  859. reject = ssb_tmslow_reject_bitmask(dev);
  860. val = ssb_read32(dev, SSB_TMSLOW);
  861. val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | reject;
  862. return (val == SSB_TMSLOW_CLOCK);
  863. }
  864. EXPORT_SYMBOL(ssb_device_is_enabled);
  865. static void ssb_flush_tmslow(struct ssb_device *dev)
  866. {
  867. /* Make _really_ sure the device has finished the TMSLOW
  868. * register write transaction, as we risk running into
  869. * a machine check exception otherwise.
  870. * Do this by reading the register back to commit the
  871. * PCI write and delay an additional usec for the device
  872. * to react to the change.
  873. */
  874. ssb_read32(dev, SSB_TMSLOW);
  875. udelay(1);
  876. }
  877. void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags)
  878. {
  879. u32 val;
  880. ssb_device_disable(dev, core_specific_flags);
  881. ssb_write32(dev, SSB_TMSLOW,
  882. SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK |
  883. SSB_TMSLOW_FGC | core_specific_flags);
  884. ssb_flush_tmslow(dev);
  885. /* Clear SERR if set. This is a hw bug workaround. */
  886. if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR)
  887. ssb_write32(dev, SSB_TMSHIGH, 0);
  888. val = ssb_read32(dev, SSB_IMSTATE);
  889. if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
  890. val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
  891. ssb_write32(dev, SSB_IMSTATE, val);
  892. }
  893. ssb_write32(dev, SSB_TMSLOW,
  894. SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC |
  895. core_specific_flags);
  896. ssb_flush_tmslow(dev);
  897. ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK |
  898. core_specific_flags);
  899. ssb_flush_tmslow(dev);
  900. }
  901. EXPORT_SYMBOL(ssb_device_enable);
  902. /* Wait for bitmask in a register to get set or cleared.
  903. * timeout is in units of ten-microseconds
  904. */
  905. static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,
  906. int timeout, int set)
  907. {
  908. int i;
  909. u32 val;
  910. for (i = 0; i < timeout; i++) {
  911. val = ssb_read32(dev, reg);
  912. if (set) {
  913. if ((val & bitmask) == bitmask)
  914. return 0;
  915. } else {
  916. if (!(val & bitmask))
  917. return 0;
  918. }
  919. udelay(10);
  920. }
  921. dev_err(dev->dev,
  922. "Timeout waiting for bitmask %08X on register %04X to %s\n",
  923. bitmask, reg, set ? "set" : "clear");
  924. return -ETIMEDOUT;
  925. }
  926. void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
  927. {
  928. u32 reject, val;
  929. if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
  930. return;
  931. reject = ssb_tmslow_reject_bitmask(dev);
  932. if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) {
  933. ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
  934. ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1);
  935. ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
  936. if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
  937. val = ssb_read32(dev, SSB_IMSTATE);
  938. val |= SSB_IMSTATE_REJECT;
  939. ssb_write32(dev, SSB_IMSTATE, val);
  940. ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000,
  941. 0);
  942. }
  943. ssb_write32(dev, SSB_TMSLOW,
  944. SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
  945. reject | SSB_TMSLOW_RESET |
  946. core_specific_flags);
  947. ssb_flush_tmslow(dev);
  948. if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
  949. val = ssb_read32(dev, SSB_IMSTATE);
  950. val &= ~SSB_IMSTATE_REJECT;
  951. ssb_write32(dev, SSB_IMSTATE, val);
  952. }
  953. }
  954. ssb_write32(dev, SSB_TMSLOW,
  955. reject | SSB_TMSLOW_RESET |
  956. core_specific_flags);
  957. ssb_flush_tmslow(dev);
  958. }
  959. EXPORT_SYMBOL(ssb_device_disable);
  960. /* Some chipsets need routing known for PCIe and 64-bit DMA */
  961. static bool ssb_dma_translation_special_bit(struct ssb_device *dev)
  962. {
  963. u16 chip_id = dev->bus->chip_id;
  964. if (dev->id.coreid == SSB_DEV_80211) {
  965. return (chip_id == 0x4322 || chip_id == 43221 ||
  966. chip_id == 43231 || chip_id == 43222);
  967. }
  968. return false;
  969. }
  970. u32 ssb_dma_translation(struct ssb_device *dev)
  971. {
  972. switch (dev->bus->bustype) {
  973. case SSB_BUSTYPE_SSB:
  974. return 0;
  975. case SSB_BUSTYPE_PCI:
  976. if (pci_is_pcie(dev->bus->host_pci) &&
  977. ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
  978. return SSB_PCIE_DMA_H32;
  979. } else {
  980. if (ssb_dma_translation_special_bit(dev))
  981. return SSB_PCIE_DMA_H32;
  982. else
  983. return SSB_PCI_DMA;
  984. }
  985. default:
  986. __ssb_dma_not_implemented(dev);
  987. }
  988. return 0;
  989. }
  990. EXPORT_SYMBOL(ssb_dma_translation);
  991. int ssb_bus_may_powerdown(struct ssb_bus *bus)
  992. {
  993. struct ssb_chipcommon *cc;
  994. int err = 0;
  995. /* On buses where more than one core may be working
  996. * at a time, we must not powerdown stuff if there are
  997. * still cores that may want to run.
  998. */
  999. if (bus->bustype == SSB_BUSTYPE_SSB)
  1000. goto out;
  1001. cc = &bus->chipco;
  1002. if (!cc->dev)
  1003. goto out;
  1004. if (cc->dev->id.revision < 5)
  1005. goto out;
  1006. ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
  1007. err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
  1008. if (err)
  1009. goto error;
  1010. out:
  1011. bus->powered_up = 0;
  1012. return err;
  1013. error:
  1014. pr_err("Bus powerdown failed\n");
  1015. goto out;
  1016. }
  1017. EXPORT_SYMBOL(ssb_bus_may_powerdown);
  1018. int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
  1019. {
  1020. int err;
  1021. enum ssb_clkmode mode;
  1022. err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
  1023. if (err)
  1024. goto error;
  1025. bus->powered_up = 1;
  1026. mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
  1027. ssb_chipco_set_clockmode(&bus->chipco, mode);
  1028. return 0;
  1029. error:
  1030. pr_err("Bus powerup failed\n");
  1031. return err;
  1032. }
  1033. EXPORT_SYMBOL(ssb_bus_powerup);
  1034. static void ssb_broadcast_value(struct ssb_device *dev,
  1035. u32 address, u32 data)
  1036. {
  1037. #ifdef CONFIG_SSB_DRIVER_PCICORE
  1038. /* This is used for both, PCI and ChipCommon core, so be careful. */
  1039. BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
  1040. BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
  1041. #endif
  1042. ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
  1043. ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
  1044. ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
  1045. ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
  1046. }
  1047. void ssb_commit_settings(struct ssb_bus *bus)
  1048. {
  1049. struct ssb_device *dev;
  1050. #ifdef CONFIG_SSB_DRIVER_PCICORE
  1051. dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
  1052. #else
  1053. dev = bus->chipco.dev;
  1054. #endif
  1055. if (WARN_ON(!dev))
  1056. return;
  1057. /* This forces an update of the cached registers. */
  1058. ssb_broadcast_value(dev, 0xFD8, 0);
  1059. }
  1060. EXPORT_SYMBOL(ssb_commit_settings);
  1061. u32 ssb_admatch_base(u32 adm)
  1062. {
  1063. u32 base = 0;
  1064. switch (adm & SSB_ADM_TYPE) {
  1065. case SSB_ADM_TYPE0:
  1066. base = (adm & SSB_ADM_BASE0);
  1067. break;
  1068. case SSB_ADM_TYPE1:
  1069. WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
  1070. base = (adm & SSB_ADM_BASE1);
  1071. break;
  1072. case SSB_ADM_TYPE2:
  1073. WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
  1074. base = (adm & SSB_ADM_BASE2);
  1075. break;
  1076. default:
  1077. WARN_ON(1);
  1078. }
  1079. return base;
  1080. }
  1081. EXPORT_SYMBOL(ssb_admatch_base);
  1082. u32 ssb_admatch_size(u32 adm)
  1083. {
  1084. u32 size = 0;
  1085. switch (adm & SSB_ADM_TYPE) {
  1086. case SSB_ADM_TYPE0:
  1087. size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT);
  1088. break;
  1089. case SSB_ADM_TYPE1:
  1090. WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
  1091. size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT);
  1092. break;
  1093. case SSB_ADM_TYPE2:
  1094. WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
  1095. size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT);
  1096. break;
  1097. default:
  1098. WARN_ON(1);
  1099. }
  1100. size = (1 << (size + 1));
  1101. return size;
  1102. }
  1103. EXPORT_SYMBOL(ssb_admatch_size);
  1104. static int __init ssb_modinit(void)
  1105. {
  1106. int err;
  1107. /* See the comment at the ssb_is_early_boot definition */
  1108. ssb_is_early_boot = 0;
  1109. err = bus_register(&ssb_bustype);
  1110. if (err)
  1111. return err;
  1112. /* Maybe we already registered some buses at early boot.
  1113. * Check for this and attach them
  1114. */
  1115. ssb_buses_lock();
  1116. err = ssb_attach_queued_buses();
  1117. ssb_buses_unlock();
  1118. if (err) {
  1119. bus_unregister(&ssb_bustype);
  1120. goto out;
  1121. }
  1122. err = b43_pci_ssb_bridge_init();
  1123. if (err) {
  1124. pr_err("Broadcom 43xx PCI-SSB-bridge initialization failed\n");
  1125. /* don't fail SSB init because of this */
  1126. }
  1127. err = ssb_host_pcmcia_init();
  1128. if (err) {
  1129. pr_err("PCMCIA host initialization failed\n");
  1130. /* don't fail SSB init because of this */
  1131. }
  1132. err = ssb_gige_init();
  1133. if (err) {
  1134. pr_err("SSB Broadcom Gigabit Ethernet driver initialization failed\n");
  1135. /* don't fail SSB init because of this */
  1136. err = 0;
  1137. }
  1138. out:
  1139. return err;
  1140. }
  1141. /* ssb must be initialized after PCI but before the ssb drivers.
  1142. * That means we must use some initcall between subsys_initcall
  1143. * and device_initcall.
  1144. */
  1145. fs_initcall(ssb_modinit);
  1146. static void __exit ssb_modexit(void)
  1147. {
  1148. ssb_gige_exit();
  1149. ssb_host_pcmcia_exit();
  1150. b43_pci_ssb_bridge_exit();
  1151. bus_unregister(&ssb_bustype);
  1152. }
  1153. module_exit(ssb_modexit)