r8a779a0-sysc.c 3.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Renesas R-Car V3U System Controller
  4. *
  5. * Copyright (C) 2020 Renesas Electronics Corp.
  6. */
  7. #include <linux/bits.h>
  8. #include <linux/clk/renesas.h>
  9. #include <linux/delay.h>
  10. #include <linux/err.h>
  11. #include <linux/io.h>
  12. #include <linux/iopoll.h>
  13. #include <linux/kernel.h>
  14. #include <linux/mm.h>
  15. #include <linux/of_address.h>
  16. #include <linux/pm_domain.h>
  17. #include <linux/slab.h>
  18. #include <linux/spinlock.h>
  19. #include <linux/types.h>
  20. #include <dt-bindings/power/r8a779a0-sysc.h>
  21. #include "rcar-gen4-sysc.h"
  22. static struct rcar_gen4_sysc_area r8a779a0_areas[] __initdata = {
  23. { "always-on", R8A779A0_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
  24. { "a3e0", R8A779A0_PD_A3E0, R8A779A0_PD_ALWAYS_ON, PD_SCU },
  25. { "a3e1", R8A779A0_PD_A3E1, R8A779A0_PD_ALWAYS_ON, PD_SCU },
  26. { "a2e0d0", R8A779A0_PD_A2E0D0, R8A779A0_PD_A3E0, PD_SCU },
  27. { "a2e0d1", R8A779A0_PD_A2E0D1, R8A779A0_PD_A3E0, PD_SCU },
  28. { "a2e1d0", R8A779A0_PD_A2E1D0, R8A779A0_PD_A3E1, PD_SCU },
  29. { "a2e1d1", R8A779A0_PD_A2E1D1, R8A779A0_PD_A3E1, PD_SCU },
  30. { "a1e0d0c0", R8A779A0_PD_A1E0D0C0, R8A779A0_PD_A2E0D0, PD_CPU_NOCR },
  31. { "a1e0d0c1", R8A779A0_PD_A1E0D0C1, R8A779A0_PD_A2E0D0, PD_CPU_NOCR },
  32. { "a1e0d1c0", R8A779A0_PD_A1E0D1C0, R8A779A0_PD_A2E0D1, PD_CPU_NOCR },
  33. { "a1e0d1c1", R8A779A0_PD_A1E0D1C1, R8A779A0_PD_A2E0D1, PD_CPU_NOCR },
  34. { "a1e1d0c0", R8A779A0_PD_A1E1D0C0, R8A779A0_PD_A2E1D0, PD_CPU_NOCR },
  35. { "a1e1d0c1", R8A779A0_PD_A1E1D0C1, R8A779A0_PD_A2E1D0, PD_CPU_NOCR },
  36. { "a1e1d1c0", R8A779A0_PD_A1E1D1C0, R8A779A0_PD_A2E1D1, PD_CPU_NOCR },
  37. { "a1e1d1c1", R8A779A0_PD_A1E1D1C1, R8A779A0_PD_A2E1D1, PD_CPU_NOCR },
  38. { "3dg-a", R8A779A0_PD_3DG_A, R8A779A0_PD_ALWAYS_ON },
  39. { "3dg-b", R8A779A0_PD_3DG_B, R8A779A0_PD_3DG_A },
  40. { "a3vip0", R8A779A0_PD_A3VIP0, R8A779A0_PD_ALWAYS_ON },
  41. { "a3vip1", R8A779A0_PD_A3VIP1, R8A779A0_PD_ALWAYS_ON },
  42. { "a3vip3", R8A779A0_PD_A3VIP3, R8A779A0_PD_ALWAYS_ON },
  43. { "a3vip2", R8A779A0_PD_A3VIP2, R8A779A0_PD_ALWAYS_ON },
  44. { "a3isp01", R8A779A0_PD_A3ISP01, R8A779A0_PD_ALWAYS_ON },
  45. { "a3isp23", R8A779A0_PD_A3ISP23, R8A779A0_PD_ALWAYS_ON },
  46. { "a3ir", R8A779A0_PD_A3IR, R8A779A0_PD_ALWAYS_ON },
  47. { "a2cn0", R8A779A0_PD_A2CN0, R8A779A0_PD_A3IR },
  48. { "a2imp01", R8A779A0_PD_A2IMP01, R8A779A0_PD_A3IR },
  49. { "a2dp0", R8A779A0_PD_A2DP0, R8A779A0_PD_A3IR },
  50. { "a2cv0", R8A779A0_PD_A2CV0, R8A779A0_PD_A3IR },
  51. { "a2cv1", R8A779A0_PD_A2CV1, R8A779A0_PD_A3IR },
  52. { "a2cv4", R8A779A0_PD_A2CV4, R8A779A0_PD_A3IR },
  53. { "a2cv6", R8A779A0_PD_A2CV6, R8A779A0_PD_A3IR },
  54. { "a2cn2", R8A779A0_PD_A2CN2, R8A779A0_PD_A3IR },
  55. { "a2imp23", R8A779A0_PD_A2IMP23, R8A779A0_PD_A3IR },
  56. { "a2dp1", R8A779A0_PD_A2DP1, R8A779A0_PD_A3IR },
  57. { "a2cv2", R8A779A0_PD_A2CV2, R8A779A0_PD_A3IR },
  58. { "a2cv3", R8A779A0_PD_A2CV3, R8A779A0_PD_A3IR },
  59. { "a2cv5", R8A779A0_PD_A2CV5, R8A779A0_PD_A3IR },
  60. { "a2cv7", R8A779A0_PD_A2CV7, R8A779A0_PD_A3IR },
  61. { "a2cn1", R8A779A0_PD_A2CN1, R8A779A0_PD_A3IR },
  62. { "a1cnn0", R8A779A0_PD_A1CNN0, R8A779A0_PD_A2CN0 },
  63. { "a1cnn2", R8A779A0_PD_A1CNN2, R8A779A0_PD_A2CN2 },
  64. { "a1dsp0", R8A779A0_PD_A1DSP0, R8A779A0_PD_A2CN2 },
  65. { "a1cnn1", R8A779A0_PD_A1CNN1, R8A779A0_PD_A2CN1 },
  66. { "a1dsp1", R8A779A0_PD_A1DSP1, R8A779A0_PD_A2CN1 },
  67. };
  68. const struct rcar_gen4_sysc_info r8a779a0_sysc_info __initconst = {
  69. .areas = r8a779a0_areas,
  70. .num_areas = ARRAY_SIZE(r8a779a0_areas),
  71. };